STAR
Cal STAR — firmware, DAQ server, and engine design
Loading...
Searching...
No Matches
Collaboration diagram for ADCx CFGR fields:

Macros

#define ADC_CFGR_FIELDS

Detailed Description

Macro Definition Documentation

◆ ADC_CFGR_FIELDS

#define ADC_CFGR_FIELDS
Value:
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
#define ADC_CFGR_JAUTO
ADC Automatic injected group conversion.
#define ADC_CFGR_DISCEN
ADC Discontinuous mode for regular channels.
#define ADC_CFGR_DISCNUM
ADC Discontinuous mode channel count.
#define ADC_CFGR_AUTDLY
ADC Delayed conversion mode.
#define ADC_CFGR_JAWD1EN
ADC Analog watchdog 1 enable on injected Channels.
#define ADC_CFGR_CONT
ADC Single/continuous conversion mode for regular conversion.
#define ADC_CFGR_AWD1CH
ADC Analog watchdog 1 Channel selection.
#define ADC_CFGR_AWD1EN
ADC Analog watchdog 1 enable on regular Channels.
#define ADC_CFGR_EXTSEL
ADC External trigger selection for regular group.
#define ADC_CFGR_AWD1SGL
Enable the watchdog 1 on a single channel or on all channels.
#define ADC_CFGR_JQM
ADC JSQR Queue mode.
#define ADC_CFGR_JDISCEN
ADC Discontinuous mode on injected channels.
#define ADC_CFGR_RES
ADC Data resolution.
#define ADC_CFGR_OVRMOD
ADC overrun mode.
#define ADC_CFGR_EXTEN
ADC External trigger enable and polarity selection for regular channels.

Definition at line 372 of file stm32h7xx_hal_adc_ex.h.