Macros
#define	D1_ITCMRAM_BASE (0x00000000UL)
	Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM.
#define	D1_ITCMICP_BASE (0x00100000UL)
	Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM.
#define	D1_DTCMRAM_BASE (0x20000000UL)
	Base address of : 128KB system data RAM accessible over DTCM.
#define	D1_AXIFLASH_BASE (0x08000000UL)
	Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI.
#define	D1_AXIICP_BASE (0x1FF00000UL)
	Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI.
#define	D1_AXISRAM1_BASE (0x24000000UL)
	Base address of : (up to 128KB) system data RAM1 accessible over over AXI.
#define	D1_AXISRAM2_BASE (0x24020000UL)
	Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity).
#define	D1_AXISRAM_BASE D1_AXISRAM1_BASE
	Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI.
#define	D2_AHBSRAM1_BASE (0x30000000UL)
	Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge.
#define	D2_AHBSRAM2_BASE (0x30004000UL)
	Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge.
#define	D2_AHBSRAM_BASE D2_AHBSRAM1_BASE
	Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge.
#define	D3_BKPSRAM_BASE (0x38800000UL)
	Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge.
#define	D3_SRAM_BASE (0x38000000UL)
	Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge.
#define	PERIPH_BASE (0x40000000UL)
	Base address of : AHB/APB Peripherals.
#define	OCTOSPI1_BASE (0x90000000UL)
	Base address of : OCTOSPI1 memories accessible over AXI.
#define	OCTOSPI2_BASE (0x70000000UL)
	Base address of : OCTOSPI2 memories accessible over AXI.
#define	FLASH_BANK1_BASE (0x08000000UL)
	Base address of : (up to 1 MB) Flash Bank1 accessible over AXI.
#define	FLASH_END (0x080FFFFFUL)
	FLASH end address.
#define	FLASH_BASE FLASH_BANK1_BASE
	Device electronic signature memory map.
#define	UID_BASE (0x1FF1E800UL)
	Unique device ID register base address.
#define	FLASHSIZE_BASE (0x1FF1E880UL)
	FLASH Size register base address.
#define	D2_APB1PERIPH_BASE PERIPH_BASE
#define	D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define	D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define	D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
#define	D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
#define	D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
#define	D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
#define	D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
	Legacy Peripheral memory map.
#define	APB1PERIPH_BASE PERIPH_BASE
#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
	D1_AHB1PERIPH peripherals.
#define	MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
#define	DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
#define	FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
#define	FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
#define	OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
#define	DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
#define	SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
#define	DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
#define	RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
#define	OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL)
#define	DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL)
#define	OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL)
	D2_AHB1PERIPH peripherals.
#define	DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
#define	DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
#define	DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
#define	ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
#define	ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
#define	ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
#define	ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
#define	ETH_MAC_BASE (ETH_BASE)
	USB registers base address.
#define	USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
#define	USB_OTG_GLOBAL_BASE (0x000UL)
#define	USB_OTG_DEVICE_BASE (0x800UL)
#define	USB_OTG_IN_ENDPOINT_BASE (0x900UL)
#define	USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
#define	USB_OTG_EP_REG_SIZE (0x20UL)
#define	USB_OTG_HOST_BASE (0x400UL)
#define	USB_OTG_HOST_PORT_BASE (0x440UL)
#define	USB_OTG_HOST_CHANNEL_BASE (0x500UL)
#define	USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
#define	USB_OTG_PCGCCTL_BASE (0xE00UL)
#define	USB_OTG_FIFO_BASE (0x1000UL)
#define	USB_OTG_FIFO_SIZE (0x1000UL)
	D2_AHB2PERIPH peripherals.
#define	DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
#define	PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL)
#define	RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
#define	SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
#define	DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
#define	RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
#define	FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL)
#define	CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL)
	D3_AHB1PERIPH peripherals.
#define	GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
#define	GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
#define	GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
#define	GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
#define	GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
#define	GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
#define	GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
#define	GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
#define	GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
#define	GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
#define	RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
#define	PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
#define	CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
#define	BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
#define	DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
#define	ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
#define	ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
#define	HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
#define	RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
	D1_APB1PERIPH peripherals.
#define	LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
#define	LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
#define	LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
#define	WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
	D2_APB1PERIPH peripherals.
#define	TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
#define	TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
#define	TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
#define	TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
#define	TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
#define	TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
#define	TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
#define	TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
#define	TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
#define	LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
#define	SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
#define	SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
#define	SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
#define	USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
#define	USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
#define	UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
#define	UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
#define	I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
#define	I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
#define	I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
#define	I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL)
#define	CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
#define	DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
#define	UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
#define	UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
#define	CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
#define	SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
#define	OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
#define	OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
#define	OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
#define	MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
#define	FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
#define	FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
#define	FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
#define	SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
#define	FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL)
#define	TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL)
#define	TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL)
	D2_APB2PERIPH peripherals.
#define	TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
#define	TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
#define	USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
#define	USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
#define	UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL)
#define	USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL)
#define	SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
#define	SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
#define	TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
#define	TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
#define	TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
#define	SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
#define	SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
#define	SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
#define	SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
#define	DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL)
#define	DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
#define	DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
#define	DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
#define	DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
#define	DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
#define	DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
#define	DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
#define	DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
#define	DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
#define	DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
#define	DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
#define	DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
	D3_APB1PERIPH peripherals.
#define	EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
#define	EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
#define	EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
#define	SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
#define	LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
#define	SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
#define	I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
#define	LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
#define	LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
#define	LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
#define	LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
#define	COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
#define	COMP1_BASE (COMP12_BASE + 0x0CUL)
#define	COMP2_BASE (COMP12_BASE + 0x10UL)
#define	VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
#define	RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
#define	IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
#define	SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
#define	SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
#define	SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
#define	DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL)
#define	BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
#define	BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
#define	BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
#define	BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
#define	BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
#define	BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
#define	BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
#define	BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
#define	DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
#define	DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
#define	DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
#define	DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
#define	DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
#define	DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
#define	DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
#define	DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
#define	DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
#define	DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
#define	DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
#define	DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
#define	DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
#define	DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
#define	DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
#define	DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
#define	DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
#define	DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
#define	DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define	DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define	DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define	DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define	DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define	DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define	DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
#define	DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
#define	DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
#define	DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
#define	DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
#define	DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
#define	DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
#define	DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
#define	DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
#define	DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
#define	DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define	DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define	DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define	DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define	DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
#define	DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
#define	DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
#define	DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
#define	DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define	DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
	FMC Banks registers base address.
#define	FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
#define	FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
#define	FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
#define	FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
#define	FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
#define	DBGMCU_BASE (0x5C001000UL)
#define	MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
#define	MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
#define	MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
#define	MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
#define	MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
#define	MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
#define	MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
#define	MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
#define	MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
#define	MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
#define	MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
#define	MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
#define	MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
#define	MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
#define	MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
#define	MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
#define	RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
#define	RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
#define	RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
#define	RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
#define	RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
#define	RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL)
#define	RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
#define	RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
#define	RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
#define	RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
#define	RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
#define	GPV_BASE (PERIPH_BASE + 0x11000000UL)
	GPV_BASE (PERIPH_BASE + 0x11000000UL).

Detailed Description

Macro Definition Documentation

◆ ADC12_COMMON_BASE

#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)

Definition at line 2127 of file stm32h723xx.h.

◆ ADC1_BASE

#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2125 of file stm32h723xx.h.

◆ ADC2_BASE

#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)

Definition at line 2126 of file stm32h723xx.h.

◆ ADC3_BASE

#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)

Definition at line 2173 of file stm32h723xx.h.

◆ ADC3_COMMON_BASE

#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)

Definition at line 2174 of file stm32h723xx.h.

◆ AHB1PERIPH_BASE

#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)

Definition at line 2101 of file stm32h723xx.h.

◆ AHB2PERIPH_BASE

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)

D1_AHB1PERIPH peripherals.

Definition at line 2102 of file stm32h723xx.h.

◆ APB1PERIPH_BASE

#define APB1PERIPH_BASE PERIPH_BASE

Definition at line 2099 of file stm32h723xx.h.

◆ APB2PERIPH_BASE

#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

Definition at line 2100 of file stm32h723xx.h.

◆ BDMA_BASE

#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)

Definition at line 2171 of file stm32h723xx.h.

◆ BDMA_Channel0_BASE

#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)

Definition at line 2286 of file stm32h723xx.h.

◆ BDMA_Channel1_BASE

#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)

Definition at line 2287 of file stm32h723xx.h.

◆ BDMA_Channel2_BASE

#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)

Definition at line 2288 of file stm32h723xx.h.

◆ BDMA_Channel3_BASE

#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)

Definition at line 2289 of file stm32h723xx.h.

◆ BDMA_Channel4_BASE

#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)

Definition at line 2290 of file stm32h723xx.h.

◆ BDMA_Channel5_BASE

#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)

Definition at line 2291 of file stm32h723xx.h.

◆ BDMA_Channel6_BASE

#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)

Definition at line 2292 of file stm32h723xx.h.

◆ BDMA_Channel7_BASE

#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)

Definition at line 2293 of file stm32h723xx.h.

◆ CEC_BASE

#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)

Definition at line 2208 of file stm32h723xx.h.

◆ COMP12_BASE

#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)

Definition at line 2270 of file stm32h723xx.h.

◆ COMP1_BASE

#define COMP1_BASE (COMP12_BASE + 0x0CUL)

Definition at line 2271 of file stm32h723xx.h.

◆ COMP2_BASE

#define COMP2_BASE (COMP12_BASE + 0x10UL)

Definition at line 2272 of file stm32h723xx.h.

◆ CORDIC_BASE

#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL)

D3_AHB1PERIPH peripherals.

Definition at line 2155 of file stm32h723xx.h.

◆ CRC_BASE

#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)

Definition at line 2170 of file stm32h723xx.h.

◆ CRS_BASE

#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)

Definition at line 2212 of file stm32h723xx.h.

◆ D1_AHB1PERIPH_BASE

#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)

Definition at line 2093 of file stm32h723xx.h.

◆ D1_APB1PERIPH_BASE

#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)

Definition at line 2092 of file stm32h723xx.h.

◆ D1_AXIFLASH_BASE

#define D1_AXIFLASH_BASE (0x08000000UL)

Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI.

Definition at line 2057 of file stm32h723xx.h.

◆ D1_AXIICP_BASE

#define D1_AXIICP_BASE (0x1FF00000UL)

Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI.

Definition at line 2058 of file stm32h723xx.h.

◆ D1_AXISRAM1_BASE

#define D1_AXISRAM1_BASE (0x24000000UL)

Base address of : (up to 128KB) system data RAM1 accessible over over AXI.

Definition at line 2059 of file stm32h723xx.h.

◆ D1_AXISRAM2_BASE

#define D1_AXISRAM2_BASE (0x24020000UL)

Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity).

Definition at line 2060 of file stm32h723xx.h.

◆ D1_AXISRAM_BASE

#define D1_AXISRAM_BASE D1_AXISRAM1_BASE

Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI.

Definition at line 2061 of file stm32h723xx.h.

◆ D1_DTCMRAM_BASE

#define D1_DTCMRAM_BASE (0x20000000UL)

Base address of : 128KB system data RAM accessible over DTCM.

Definition at line 2056 of file stm32h723xx.h.

◆ D1_ITCMICP_BASE

#define D1_ITCMICP_BASE (0x00100000UL)

Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM.

Definition at line 2055 of file stm32h723xx.h.

◆ D1_ITCMRAM_BASE

#define D1_ITCMRAM_BASE (0x00000000UL)

Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM.

Definition at line 2054 of file stm32h723xx.h.

◆ D2_AHB1PERIPH_BASE

#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)

Definition at line 2089 of file stm32h723xx.h.

◆ D2_AHB2PERIPH_BASE

#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)

Definition at line 2090 of file stm32h723xx.h.

◆ D2_AHBSRAM1_BASE

#define D2_AHBSRAM1_BASE (0x30000000UL)

Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge.

Definition at line 2063 of file stm32h723xx.h.

◆ D2_AHBSRAM2_BASE

#define D2_AHBSRAM2_BASE (0x30004000UL)

Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge.

Definition at line 2064 of file stm32h723xx.h.

◆ D2_AHBSRAM_BASE

#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE

Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge.

Definition at line 2065 of file stm32h723xx.h.

◆ D2_APB1PERIPH_BASE

#define D2_APB1PERIPH_BASE PERIPH_BASE

Definition at line 2087 of file stm32h723xx.h.

◆ D2_APB2PERIPH_BASE

#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

Definition at line 2088 of file stm32h723xx.h.

◆ D3_AHB1PERIPH_BASE

#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)

Legacy Peripheral memory map.

Definition at line 2096 of file stm32h723xx.h.

◆ D3_APB1PERIPH_BASE

#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)

Definition at line 2095 of file stm32h723xx.h.

◆ D3_BKPSRAM_BASE

#define D3_BKPSRAM_BASE (0x38800000UL)

Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge.

Definition at line 2067 of file stm32h723xx.h.

◆ D3_SRAM_BASE

#define D3_SRAM_BASE (0x38000000UL)

Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge.

Definition at line 2068 of file stm32h723xx.h.

◆ DAC1_BASE

#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)

Definition at line 2209 of file stm32h723xx.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE (0x5C001000UL)

Definition at line 2371 of file stm32h723xx.h.

◆ DCMI_BASE

#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)

Definition at line 2148 of file stm32h723xx.h.

◆ DFSDM1_BASE

#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL)

Definition at line 2243 of file stm32h723xx.h.

◆ DFSDM1_Channel0_BASE

#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)

Definition at line 2244 of file stm32h723xx.h.

◆ DFSDM1_Channel1_BASE

#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)

Definition at line 2245 of file stm32h723xx.h.

◆ DFSDM1_Channel2_BASE

#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)

Definition at line 2246 of file stm32h723xx.h.

◆ DFSDM1_Channel3_BASE

#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)

Definition at line 2247 of file stm32h723xx.h.

◆ DFSDM1_Channel4_BASE

#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)

Definition at line 2248 of file stm32h723xx.h.

◆ DFSDM1_Channel5_BASE

#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)

Definition at line 2249 of file stm32h723xx.h.

◆ DFSDM1_Channel6_BASE

#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)

Definition at line 2250 of file stm32h723xx.h.

◆ DFSDM1_Channel7_BASE

#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)

Definition at line 2251 of file stm32h723xx.h.

◆ DFSDM1_Filter0_BASE

#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)

Definition at line 2252 of file stm32h723xx.h.

◆ DFSDM1_Filter1_BASE

#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)

Definition at line 2253 of file stm32h723xx.h.

◆ DFSDM1_Filter2_BASE

#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)

Definition at line 2254 of file stm32h723xx.h.

◆ DFSDM1_Filter3_BASE

#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)

D3_APB1PERIPH peripherals.

Definition at line 2255 of file stm32h723xx.h.

◆ DLYB_OCTOSPI1_BASE

#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)

Definition at line 2112 of file stm32h723xx.h.

◆ DLYB_OCTOSPI2_BASE

#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL)

Definition at line 2117 of file stm32h723xx.h.

◆ DLYB_SDMMC1_BASE

#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)

Definition at line 2114 of file stm32h723xx.h.

◆ DLYB_SDMMC2_BASE

#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)

Definition at line 2152 of file stm32h723xx.h.

◆ DMA1_BASE

#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2122 of file stm32h723xx.h.

◆ DMA1_Stream0_BASE

#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)

Definition at line 2316 of file stm32h723xx.h.

◆ DMA1_Stream1_BASE

#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)

Definition at line 2317 of file stm32h723xx.h.

◆ DMA1_Stream2_BASE

#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)

Definition at line 2318 of file stm32h723xx.h.

◆ DMA1_Stream3_BASE

#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)

Definition at line 2319 of file stm32h723xx.h.

◆ DMA1_Stream4_BASE

#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)

Definition at line 2320 of file stm32h723xx.h.

◆ DMA1_Stream5_BASE

#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)

Definition at line 2321 of file stm32h723xx.h.

◆ DMA1_Stream6_BASE

#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)

Definition at line 2322 of file stm32h723xx.h.

◆ DMA1_Stream7_BASE

#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)

Definition at line 2323 of file stm32h723xx.h.

◆ DMA2_BASE

#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)

Definition at line 2123 of file stm32h723xx.h.

◆ DMA2_Stream0_BASE

#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)

Definition at line 2325 of file stm32h723xx.h.

◆ DMA2_Stream1_BASE

#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)

Definition at line 2326 of file stm32h723xx.h.

◆ DMA2_Stream2_BASE

#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)

Definition at line 2327 of file stm32h723xx.h.

◆ DMA2_Stream3_BASE

#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)

Definition at line 2328 of file stm32h723xx.h.

◆ DMA2_Stream4_BASE

#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)

Definition at line 2329 of file stm32h723xx.h.

◆ DMA2_Stream5_BASE

#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)

Definition at line 2330 of file stm32h723xx.h.

◆ DMA2_Stream6_BASE

#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)

Definition at line 2331 of file stm32h723xx.h.

◆ DMA2_Stream7_BASE

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)

Definition at line 2332 of file stm32h723xx.h.

◆ DMA2D_BASE

#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)

Definition at line 2108 of file stm32h723xx.h.

◆ DMAMUX1_BASE

#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)

Definition at line 2124 of file stm32h723xx.h.

◆ DMAMUX1_Channel0_BASE

#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)

Definition at line 2334 of file stm32h723xx.h.

◆ DMAMUX1_Channel10_BASE

#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)

Definition at line 2344 of file stm32h723xx.h.

◆ DMAMUX1_Channel11_BASE

#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)

Definition at line 2345 of file stm32h723xx.h.

◆ DMAMUX1_Channel12_BASE

#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)

Definition at line 2346 of file stm32h723xx.h.

◆ DMAMUX1_Channel13_BASE

#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)

Definition at line 2347 of file stm32h723xx.h.

◆ DMAMUX1_Channel14_BASE

#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)

Definition at line 2348 of file stm32h723xx.h.

◆ DMAMUX1_Channel15_BASE

#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)

Definition at line 2349 of file stm32h723xx.h.

◆ DMAMUX1_Channel1_BASE

#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)

Definition at line 2335 of file stm32h723xx.h.

◆ DMAMUX1_Channel2_BASE

#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)

Definition at line 2336 of file stm32h723xx.h.

◆ DMAMUX1_Channel3_BASE

#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)

Definition at line 2337 of file stm32h723xx.h.

◆ DMAMUX1_Channel4_BASE

#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)

Definition at line 2338 of file stm32h723xx.h.

◆ DMAMUX1_Channel5_BASE

#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)

Definition at line 2339 of file stm32h723xx.h.

◆ DMAMUX1_Channel6_BASE

#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)

Definition at line 2340 of file stm32h723xx.h.

◆ DMAMUX1_Channel7_BASE

#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)

Definition at line 2341 of file stm32h723xx.h.

◆ DMAMUX1_Channel8_BASE

#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)

Definition at line 2342 of file stm32h723xx.h.

◆ DMAMUX1_Channel9_BASE

#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)

Definition at line 2343 of file stm32h723xx.h.

◆ DMAMUX1_ChannelStatus_BASE

#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)

Definition at line 2360 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator0_BASE

#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)

Definition at line 2351 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator1_BASE

#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)

Definition at line 2352 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator2_BASE

#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)

Definition at line 2353 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator3_BASE

#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)

Definition at line 2354 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator4_BASE

#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)

Definition at line 2355 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator5_BASE

#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)

Definition at line 2356 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator6_BASE

#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)

Definition at line 2357 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenerator7_BASE

#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)

Definition at line 2358 of file stm32h723xx.h.

◆ DMAMUX1_RequestGenStatus_BASE

#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)

FMC Banks registers base address.

Definition at line 2361 of file stm32h723xx.h.

◆ DMAMUX2_BASE

#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)

Definition at line 2172 of file stm32h723xx.h.

◆ DMAMUX2_Channel0_BASE

#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)

Definition at line 2295 of file stm32h723xx.h.

◆ DMAMUX2_Channel1_BASE

#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)

Definition at line 2296 of file stm32h723xx.h.

◆ DMAMUX2_Channel2_BASE

#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)

Definition at line 2297 of file stm32h723xx.h.

◆ DMAMUX2_Channel3_BASE

#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)

Definition at line 2298 of file stm32h723xx.h.

◆ DMAMUX2_Channel4_BASE

#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)

Definition at line 2299 of file stm32h723xx.h.

◆ DMAMUX2_Channel5_BASE

#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)

Definition at line 2300 of file stm32h723xx.h.

◆ DMAMUX2_Channel6_BASE

#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)

Definition at line 2301 of file stm32h723xx.h.

◆ DMAMUX2_Channel7_BASE

#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)

Definition at line 2302 of file stm32h723xx.h.

◆ DMAMUX2_ChannelStatus_BASE

#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)

Definition at line 2313 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator0_BASE

#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)

Definition at line 2304 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator1_BASE

#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)

Definition at line 2305 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator2_BASE

#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)

Definition at line 2306 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator3_BASE

#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)

Definition at line 2307 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator4_BASE

#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)

Definition at line 2308 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator5_BASE

#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)

Definition at line 2309 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator6_BASE

#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)

Definition at line 2310 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenerator7_BASE

#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)

Definition at line 2311 of file stm32h723xx.h.

◆ DMAMUX2_RequestGenStatus_BASE

#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)

Definition at line 2314 of file stm32h723xx.h.

◆ DTS_BASE

#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL)

Definition at line 2282 of file stm32h723xx.h.

◆ ETH_BASE

#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)

Definition at line 2128 of file stm32h723xx.h.

◆ ETH_MAC_BASE

#define ETH_MAC_BASE (ETH_BASE)

USB registers base address.

Definition at line 2129 of file stm32h723xx.h.

◆ EXTI_BASE

#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)

Definition at line 2259 of file stm32h723xx.h.

◆ EXTI_D1_BASE

#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)

Definition at line 2260 of file stm32h723xx.h.

◆ EXTI_D2_BASE

#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)

Definition at line 2261 of file stm32h723xx.h.

◆ FDCAN1_BASE

#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)

Definition at line 2218 of file stm32h723xx.h.

◆ FDCAN2_BASE

#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)

Definition at line 2219 of file stm32h723xx.h.

◆ FDCAN3_BASE

#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL)

Definition at line 2222 of file stm32h723xx.h.

◆ FDCAN_CCU_BASE

#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)

Definition at line 2220 of file stm32h723xx.h.

◆ FLASH_BANK1_BASE

#define FLASH_BANK1_BASE (0x08000000UL)

Base address of : (up to 1 MB) Flash Bank1 accessible over AXI.

Definition at line 2074 of file stm32h723xx.h.

◆ FLASH_BASE

#define FLASH_BASE FLASH_BANK1_BASE

Device electronic signature memory map.

Definition at line 2079 of file stm32h723xx.h.

◆ FLASH_END

#define FLASH_END (0x080FFFFFUL)

FLASH end address.

Definition at line 2075 of file stm32h723xx.h.

◆ FLASH_R_BASE

#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)

Definition at line 2109 of file stm32h723xx.h.

◆ FLASHSIZE_BASE

#define FLASHSIZE_BASE (0x1FF1E880UL)

FLASH Size register base address.

Peripheral memory map

Definition at line 2083 of file stm32h723xx.h.

◆ FMAC_BASE

#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL)

Definition at line 2154 of file stm32h723xx.h.

◆ FMC_Bank1_R_BASE

#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)

Definition at line 2364 of file stm32h723xx.h.

◆ FMC_Bank1E_R_BASE

#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)

Definition at line 2365 of file stm32h723xx.h.

◆ FMC_Bank2_R_BASE

#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)

Definition at line 2366 of file stm32h723xx.h.

◆ FMC_Bank3_R_BASE

#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)

Definition at line 2367 of file stm32h723xx.h.

◆ FMC_Bank5_6_R_BASE

#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)

Definition at line 2368 of file stm32h723xx.h.

◆ FMC_R_BASE

#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)

Definition at line 2110 of file stm32h723xx.h.

◆ GPIOA_BASE

#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2158 of file stm32h723xx.h.

◆ GPIOB_BASE

#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)

Definition at line 2159 of file stm32h723xx.h.

◆ GPIOC_BASE

#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)

Definition at line 2160 of file stm32h723xx.h.

◆ GPIOD_BASE

#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)

Definition at line 2161 of file stm32h723xx.h.

◆ GPIOE_BASE

#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)

Definition at line 2162 of file stm32h723xx.h.

◆ GPIOF_BASE

#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)

Definition at line 2163 of file stm32h723xx.h.

◆ GPIOG_BASE

#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)

Definition at line 2164 of file stm32h723xx.h.

◆ GPIOH_BASE

#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)

Definition at line 2165 of file stm32h723xx.h.

◆ GPIOJ_BASE

#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)

Definition at line 2166 of file stm32h723xx.h.

◆ GPIOK_BASE

#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)

Definition at line 2167 of file stm32h723xx.h.

◆ GPV_BASE

#define GPV_BASE (PERIPH_BASE + 0x11000000UL)

GPV_BASE (PERIPH_BASE + 0x11000000UL).

Definition at line 2406 of file stm32h723xx.h.

◆ HSEM_BASE

#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)

Definition at line 2175 of file stm32h723xx.h.

◆ I2C1_BASE

#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)

Definition at line 2204 of file stm32h723xx.h.

◆ I2C2_BASE

#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)

Definition at line 2205 of file stm32h723xx.h.

◆ I2C3_BASE

#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)

Definition at line 2206 of file stm32h723xx.h.

◆ I2C4_BASE

#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)

Definition at line 2265 of file stm32h723xx.h.

◆ I2C5_BASE

#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL)

Definition at line 2207 of file stm32h723xx.h.

◆ IWDG1_BASE

#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)

Definition at line 2275 of file stm32h723xx.h.

◆ LPTIM1_BASE

#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)

Definition at line 2194 of file stm32h723xx.h.

◆ LPTIM2_BASE

#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)

Definition at line 2266 of file stm32h723xx.h.

◆ LPTIM3_BASE

#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)

Definition at line 2267 of file stm32h723xx.h.

◆ LPTIM4_BASE

#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)

Definition at line 2268 of file stm32h723xx.h.

◆ LPTIM5_BASE

#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)

Definition at line 2269 of file stm32h723xx.h.

◆ LPUART1_BASE

#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)

Definition at line 2263 of file stm32h723xx.h.

◆ LTDC_BASE

#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)

Definition at line 2179 of file stm32h723xx.h.

◆ LTDC_Layer1_BASE

#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)

Definition at line 2180 of file stm32h723xx.h.

◆ LTDC_Layer2_BASE

#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)

Definition at line 2181 of file stm32h723xx.h.

◆ MDIOS_BASE

#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)

Definition at line 2217 of file stm32h723xx.h.

◆ MDMA_BASE

#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)

Definition at line 2107 of file stm32h723xx.h.

◆ MDMA_Channel0_BASE

#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)

Definition at line 2373 of file stm32h723xx.h.

◆ MDMA_Channel10_BASE

#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)

Definition at line 2383 of file stm32h723xx.h.

◆ MDMA_Channel11_BASE

#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)

Definition at line 2384 of file stm32h723xx.h.

◆ MDMA_Channel12_BASE

#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)

Definition at line 2385 of file stm32h723xx.h.

◆ MDMA_Channel13_BASE

#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)

Definition at line 2386 of file stm32h723xx.h.

◆ MDMA_Channel14_BASE

#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)

Definition at line 2387 of file stm32h723xx.h.

◆ MDMA_Channel15_BASE

#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)

Definition at line 2388 of file stm32h723xx.h.

◆ MDMA_Channel1_BASE

#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)

Definition at line 2374 of file stm32h723xx.h.

◆ MDMA_Channel2_BASE

#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)

Definition at line 2375 of file stm32h723xx.h.

◆ MDMA_Channel3_BASE

#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)

Definition at line 2376 of file stm32h723xx.h.

◆ MDMA_Channel4_BASE

#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)

Definition at line 2377 of file stm32h723xx.h.

◆ MDMA_Channel5_BASE

#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)

Definition at line 2378 of file stm32h723xx.h.

◆ MDMA_Channel6_BASE

#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)

Definition at line 2379 of file stm32h723xx.h.

◆ MDMA_Channel7_BASE

#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)

Definition at line 2380 of file stm32h723xx.h.

◆ MDMA_Channel8_BASE

#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)

Definition at line 2381 of file stm32h723xx.h.

◆ MDMA_Channel9_BASE

#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)

Definition at line 2382 of file stm32h723xx.h.

◆ OCTOSPI1_BASE

#define OCTOSPI1_BASE (0x90000000UL)

Base address of : OCTOSPI1 memories accessible over AXI.

Definition at line 2071 of file stm32h723xx.h.

◆ OCTOSPI1_R_BASE

#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)

Definition at line 2111 of file stm32h723xx.h.

◆ OCTOSPI2_BASE

#define OCTOSPI2_BASE (0x70000000UL)

Base address of : OCTOSPI2 memories accessible over AXI.

Definition at line 2072 of file stm32h723xx.h.

◆ OCTOSPI2_R_BASE

#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL)

Definition at line 2116 of file stm32h723xx.h.

◆ OCTOSPIM_BASE

#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL)

D2_AHB1PERIPH peripherals.

Definition at line 2118 of file stm32h723xx.h.

◆ OPAMP1_BASE

#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)

Definition at line 2215 of file stm32h723xx.h.

◆ OPAMP2_BASE

#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)

Definition at line 2216 of file stm32h723xx.h.

◆ OPAMP_BASE

#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)

Definition at line 2214 of file stm32h723xx.h.

◆ PERIPH_BASE

#define PERIPH_BASE (0x40000000UL)

Base address of : AHB/APB Peripherals.

Definition at line 2070 of file stm32h723xx.h.

◆ PSSI_BASE

#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL)

Definition at line 2149 of file stm32h723xx.h.

◆ PWR_BASE

#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)

Definition at line 2169 of file stm32h723xx.h.

◆ RAMECC1_BASE

#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)

Definition at line 2115 of file stm32h723xx.h.

◆ RAMECC1_Monitor1_BASE

#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

Definition at line 2390 of file stm32h723xx.h.

◆ RAMECC1_Monitor2_BASE

#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

Definition at line 2391 of file stm32h723xx.h.

◆ RAMECC1_Monitor3_BASE

#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

Definition at line 2392 of file stm32h723xx.h.

◆ RAMECC1_Monitor4_BASE

#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

Definition at line 2393 of file stm32h723xx.h.

◆ RAMECC1_Monitor5_BASE

#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

Definition at line 2394 of file stm32h723xx.h.

◆ RAMECC1_Monitor6_BASE

#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL)

Definition at line 2395 of file stm32h723xx.h.

◆ RAMECC2_BASE

#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)

Definition at line 2153 of file stm32h723xx.h.

◆ RAMECC2_Monitor1_BASE

#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

Definition at line 2397 of file stm32h723xx.h.

◆ RAMECC2_Monitor2_BASE

#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

Definition at line 2398 of file stm32h723xx.h.

◆ RAMECC2_Monitor3_BASE

#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

Definition at line 2399 of file stm32h723xx.h.

◆ RAMECC3_BASE

#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)

D1_APB1PERIPH peripherals.

Definition at line 2176 of file stm32h723xx.h.

◆ RAMECC3_Monitor1_BASE

#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

Definition at line 2401 of file stm32h723xx.h.

◆ RAMECC3_Monitor2_BASE

#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

Definition at line 2402 of file stm32h723xx.h.

◆ RCC_BASE

#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)

Definition at line 2168 of file stm32h723xx.h.

◆ RNG_BASE

#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)

Definition at line 2150 of file stm32h723xx.h.

◆ RTC_BASE

#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)

Definition at line 2274 of file stm32h723xx.h.

◆ SAI1_BASE

#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)

Definition at line 2240 of file stm32h723xx.h.

◆ SAI1_Block_A_BASE

#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)

Definition at line 2241 of file stm32h723xx.h.

◆ SAI1_Block_B_BASE

#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)

Definition at line 2242 of file stm32h723xx.h.

◆ SAI4_BASE

#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)

Definition at line 2278 of file stm32h723xx.h.

◆ SAI4_Block_A_BASE

#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)

Definition at line 2279 of file stm32h723xx.h.

◆ SAI4_Block_B_BASE

#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)

Definition at line 2280 of file stm32h723xx.h.

◆ SDMMC1_BASE

#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)

Definition at line 2113 of file stm32h723xx.h.

◆ SDMMC2_BASE

#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)

Definition at line 2151 of file stm32h723xx.h.

◆ SPDIFRX_BASE

#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)

Definition at line 2199 of file stm32h723xx.h.

◆ SPI1_BASE

#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)

Definition at line 2234 of file stm32h723xx.h.

◆ SPI2_BASE

#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)

Definition at line 2197 of file stm32h723xx.h.

◆ SPI3_BASE

#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)

Definition at line 2198 of file stm32h723xx.h.

◆ SPI4_BASE

#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)

Definition at line 2235 of file stm32h723xx.h.

◆ SPI5_BASE

#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)

Definition at line 2239 of file stm32h723xx.h.

◆ SPI6_BASE

#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)

Definition at line 2264 of file stm32h723xx.h.

◆ SRAMCAN_BASE

#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)

Definition at line 2221 of file stm32h723xx.h.

◆ SWPMI1_BASE

#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)

Definition at line 2213 of file stm32h723xx.h.

◆ SYSCFG_BASE

#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)

Definition at line 2262 of file stm32h723xx.h.

◆ TIM12_BASE

#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)

Definition at line 2191 of file stm32h723xx.h.

◆ TIM13_BASE

#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)

Definition at line 2192 of file stm32h723xx.h.

◆ TIM14_BASE

#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)

Definition at line 2193 of file stm32h723xx.h.

◆ TIM15_BASE

#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)

Definition at line 2236 of file stm32h723xx.h.

◆ TIM16_BASE

#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)

Definition at line 2237 of file stm32h723xx.h.

◆ TIM17_BASE

#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)

Definition at line 2238 of file stm32h723xx.h.

◆ TIM1_BASE

#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)

Definition at line 2228 of file stm32h723xx.h.

◆ TIM23_BASE

#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL)

Definition at line 2223 of file stm32h723xx.h.

◆ TIM24_BASE

#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL)

D2_APB2PERIPH peripherals.

Definition at line 2224 of file stm32h723xx.h.

◆ TIM2_BASE

#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)

Definition at line 2185 of file stm32h723xx.h.

◆ TIM3_BASE

#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)

Definition at line 2186 of file stm32h723xx.h.

◆ TIM4_BASE

#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)

Definition at line 2187 of file stm32h723xx.h.

◆ TIM5_BASE

#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)

Definition at line 2188 of file stm32h723xx.h.

◆ TIM6_BASE

#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)

Definition at line 2189 of file stm32h723xx.h.

◆ TIM7_BASE

#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)

Definition at line 2190 of file stm32h723xx.h.

◆ TIM8_BASE

#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)

Definition at line 2229 of file stm32h723xx.h.

◆ UART4_BASE

#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)

Definition at line 2202 of file stm32h723xx.h.

◆ UART5_BASE

#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)

Definition at line 2203 of file stm32h723xx.h.

◆ UART7_BASE

#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)

Definition at line 2210 of file stm32h723xx.h.

◆ UART8_BASE

#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)

Definition at line 2211 of file stm32h723xx.h.

◆ UART9_BASE

#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL)

Definition at line 2232 of file stm32h723xx.h.

◆ UID_BASE

#define UID_BASE (0x1FF1E800UL)

Unique device ID register base address.

Definition at line 2082 of file stm32h723xx.h.

Referenced by HAL_GetUIDw0(), HAL_GetUIDw1(), and HAL_GetUIDw2().

◆ USART10_BASE

#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL)

Definition at line 2233 of file stm32h723xx.h.

◆ USART1_BASE

#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)

Definition at line 2230 of file stm32h723xx.h.

◆ USART2_BASE

#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)

Definition at line 2200 of file stm32h723xx.h.

◆ USART3_BASE

#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)

Definition at line 2201 of file stm32h723xx.h.

◆ USART6_BASE

#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)

Definition at line 2231 of file stm32h723xx.h.

◆ USB1_OTG_HS_PERIPH_BASE

#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)

Definition at line 2132 of file stm32h723xx.h.

◆ USB_OTG_DEVICE_BASE

#define USB_OTG_DEVICE_BASE (0x800UL)

Definition at line 2134 of file stm32h723xx.h.

◆ USB_OTG_EP_REG_SIZE

#define USB_OTG_EP_REG_SIZE (0x20UL)

Definition at line 2137 of file stm32h723xx.h.

◆ USB_OTG_FIFO_BASE

#define USB_OTG_FIFO_BASE (0x1000UL)

Definition at line 2143 of file stm32h723xx.h.

◆ USB_OTG_FIFO_SIZE

#define USB_OTG_FIFO_SIZE (0x1000UL)

D2_AHB2PERIPH peripherals.

Definition at line 2144 of file stm32h723xx.h.

◆ USB_OTG_GLOBAL_BASE

#define USB_OTG_GLOBAL_BASE (0x000UL)

Definition at line 2133 of file stm32h723xx.h.

◆ USB_OTG_HOST_BASE

#define USB_OTG_HOST_BASE (0x400UL)

Definition at line 2138 of file stm32h723xx.h.

◆ USB_OTG_HOST_CHANNEL_BASE

#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)

Definition at line 2140 of file stm32h723xx.h.

◆ USB_OTG_HOST_CHANNEL_SIZE

#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)

Definition at line 2141 of file stm32h723xx.h.

◆ USB_OTG_HOST_PORT_BASE

#define USB_OTG_HOST_PORT_BASE (0x440UL)

Definition at line 2139 of file stm32h723xx.h.

◆ USB_OTG_IN_ENDPOINT_BASE

#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)

Definition at line 2135 of file stm32h723xx.h.

◆ USB_OTG_OUT_ENDPOINT_BASE

#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)

Definition at line 2136 of file stm32h723xx.h.

◆ USB_OTG_PCGCCTL_BASE

#define USB_OTG_PCGCCTL_BASE (0xE00UL)

Definition at line 2142 of file stm32h723xx.h.

◆ VREFBUF_BASE

#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)

Definition at line 2273 of file stm32h723xx.h.

◆ WWDG1_BASE

#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)

D2_APB1PERIPH peripherals.

Definition at line 2182 of file stm32h723xx.h.

Macros