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STAR
Cal STAR — firmware, DAQ server, and engine design
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Macros | |
| #define | RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 |
| Clock range frequency between 1 and 2 MHz. | |
| #define | RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 |
| Clock range frequency between 2 and 4 MHz. | |
| #define | RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 |
| Clock range frequency between 4 and 8 MHz. | |
| #define | RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 |
| Clock range frequency between 8 and 16 MHz. | |
| #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 |
Clock range frequency between 1 and 2 MHz.
Definition at line 287 of file stm32h7xx_hal_rcc.h.
| #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 |
Clock range frequency between 2 and 4 MHz.
Definition at line 288 of file stm32h7xx_hal_rcc.h.
Referenced by SystemClock_Config().
| #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 |
Clock range frequency between 4 and 8 MHz.
Definition at line 289 of file stm32h7xx_hal_rcc.h.
| #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 |
Clock range frequency between 8 and 16 MHz.
Definition at line 290 of file stm32h7xx_hal_rcc.h.