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Cal STAR — firmware, DAQ server, and engine design
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SPI Reception FIFO Status Level
Collaboration diagram for SPI Reception FIFO Status Level:

Macros

#define SPI_RX_FIFO_0PACKET   (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
#define SPI_RX_FIFO_1PACKET   (SPI_SR_RXPLVL_0)
#define SPI_RX_FIFO_2PACKET   (SPI_SR_RXPLVL_1)
#define SPI_RX_FIFO_3PACKET   (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Detailed Description

Macro Definition Documentation

◆ SPI_RX_FIFO_0PACKET

#define SPI_RX_FIFO_0PACKET   (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */

Definition at line 643 of file stm32h7xx_hal_spi.h.

◆ SPI_RX_FIFO_1PACKET

#define SPI_RX_FIFO_1PACKET   (SPI_SR_RXPLVL_0)

Definition at line 644 of file stm32h7xx_hal_spi.h.

◆ SPI_RX_FIFO_2PACKET

#define SPI_RX_FIFO_2PACKET   (SPI_SR_RXPLVL_1)

Definition at line 645 of file stm32h7xx_hal_spi.h.

◆ SPI_RX_FIFO_3PACKET

#define SPI_RX_FIFO_3PACKET   (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Definition at line 646 of file stm32h7xx_hal_spi.h.