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stm32h7xx_hal_cortex.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_hal_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_CORTEX_H
21#define STM32H7xx_HAL_CORTEX_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
30/** @addtogroup STM32H7xx_HAL_Driver
31 * @{
32 */
33
34/** @addtogroup CORTEX
35 * @{
36 */
37/* Exported types ------------------------------------------------------------*/
38/** @defgroup CORTEX_Exported_Types Cortex Exported Types
39 * @{
40 */
41
42#if (__MPU_PRESENT == 1)
43/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
44 * @brief MPU Region initialization structure
45 * @{
46 */
47typedef struct
48{
49 uint8_t Enable; /*!< Specifies the status of the region.
50 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
51 uint8_t Number; /*!< Specifies the number of the region to protect.
52 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
53 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
54 uint8_t Size; /*!< Specifies the size of the region to protect.
55 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
56 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
57 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
58 uint8_t TypeExtField; /*!< Specifies the TEX field level.
59 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
60 uint8_t AccessPermission; /*!< Specifies the region access permission type.
61 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
62 uint8_t DisableExec; /*!< Specifies the instruction access status.
63 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
64 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
65 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
66 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
67 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
68 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
69 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
70}MPU_Region_InitTypeDef;
71/**
72 * @}
73 */
74#endif /* __MPU_PRESENT */
75
76/**
77 * @}
78 */
79
80/* Exported constants --------------------------------------------------------*/
81
82/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
83 * @{
84 */
85
86/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
87 * @{
88 */
89#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
90 4 bits for subpriority */
91#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
92 3 bits for subpriority */
93#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
94 2 bits for subpriority */
95#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
96 1 bits for subpriority */
97#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
98 0 bits for subpriority */
99/**
100 * @}
101 */
102
103/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
104 * @{
105 */
106#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
107#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
108
109/**
110 * @}
111 */
112
113#if (__MPU_PRESENT == 1)
114/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
115 * @{
116 */
117#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
118#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
119#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
120#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
121/**
122 * @}
123 */
124
125/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
126 * @{
127 */
128#define MPU_REGION_ENABLE ((uint8_t)0x01)
129#define MPU_REGION_DISABLE ((uint8_t)0x00)
130/**
131 * @}
132 */
133
134/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
135 * @{
136 */
137#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
138#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
139/**
140 * @}
141 */
142
143/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
144 * @{
145 */
146#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
147#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
148/**
149 * @}
150 */
151
152/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
153 * @{
154 */
155#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
156#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
157/**
158 * @}
159 */
160
161/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
162 * @{
163 */
164#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
165#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
166/**
167 * @}
168 */
169
170/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
171 * @{
172 */
173#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
174#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
175#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
176/**
177 * @}
178 */
179
180/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
181 * @{
182 */
183#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
184#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
185#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
186#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
187#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
188#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
189#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
190#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
191#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
192#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
193#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
194#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
195#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
196#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
197#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
198#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
199#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
200#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
201#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
202#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
203#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
204#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
205#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
206#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
207#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
208#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
209#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
210#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
211/**
212 * @}
213 */
214
215/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
216 * @{
217 */
218#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
219#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
220#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
221#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
222#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
223#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
224/**
225 * @}
226 */
227
228/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
229 * @{
230 */
231#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
232#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
233#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
234#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
235#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
236#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
237#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
238#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
239#if !defined(CORE_CM4)
240#define MPU_REGION_NUMBER8 ((uint8_t)0x08)
241#define MPU_REGION_NUMBER9 ((uint8_t)0x09)
242#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)
243#define MPU_REGION_NUMBER11 ((uint8_t)0x0B)
244#define MPU_REGION_NUMBER12 ((uint8_t)0x0C)
245#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)
246#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)
247#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)
248#endif /* !defined(CORE_CM4) */
249
250/**
251 * @}
252 */
253#endif /* __MPU_PRESENT */
254
255/**
256 * @}
257 */
258
259
260/* Exported Macros -----------------------------------------------------------*/
261/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
262 * @{
263 */
264
265/**
266 * @}
267 */
268
269
270
271/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
272 * @{
273 */
274#define CM7_CPUID ((uint32_t)0x00000003)
275
276#if defined(DUAL_CORE)
277#define CM4_CPUID ((uint32_t)0x00000001)
278#endif /*DUAL_CORE*/
279/**
280 * @}
281 */
282
283
284/* Exported functions --------------------------------------------------------*/
285/** @addtogroup CORTEX_Exported_Functions
286 * @{
287 */
288
289/** @addtogroup CORTEX_Exported_Functions_Group1
290 * @{
291 */
292/* Initialization and de-initialization functions *****************************/
293void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
294void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
295void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
296void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
297void HAL_NVIC_SystemReset(void);
298uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
299/**
300 * @}
301 */
302
303/** @addtogroup CORTEX_Exported_Functions_Group2
304 * @{
305 */
306/* Peripheral Control functions ***********************************************/
307#if (__MPU_PRESENT == 1)
308void HAL_MPU_Enable(uint32_t MPU_Control);
309void HAL_MPU_Disable(void);
310void HAL_MPU_EnableRegion(uint32_t RegionNumber);
311void HAL_MPU_DisableRegion(uint32_t RegionNumber);
312void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init);
313#endif /* __MPU_PRESENT */
314uint32_t HAL_NVIC_GetPriorityGrouping(void);
315void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
316uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
317void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
318void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
319uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
320void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
321void HAL_SYSTICK_IRQHandler(void);
322void HAL_SYSTICK_Callback(void);
323uint32_t HAL_GetCurrentCPUID(void);
324
325
326/**
327 * @}
328 */
329
330/**
331 * @}
332 */
333
334/* Private types -------------------------------------------------------------*/
335/* Private variables ---------------------------------------------------------*/
336/* Private constants ---------------------------------------------------------*/
337/* Private macros ------------------------------------------------------------*/
338/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
339 * @{
340 */
341#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
342 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
343 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
344 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
345 ((GROUP) == NVIC_PRIORITYGROUP_4))
346
347#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
348
349#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
350
351#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00)
352
353#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
354 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
355
356#if (__MPU_PRESENT == 1)
357#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
358 ((STATE) == MPU_REGION_DISABLE))
359
360#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
361 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
362
363#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
364 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
365
366#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
367 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
368
369#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
370 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
371
372#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
373 ((TYPE) == MPU_TEX_LEVEL1) || \
374 ((TYPE) == MPU_TEX_LEVEL2))
375
376#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
377 ((TYPE) == MPU_REGION_PRIV_RW) || \
378 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
379 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
380 ((TYPE) == MPU_REGION_PRIV_RO) || \
381 ((TYPE) == MPU_REGION_PRIV_RO_URO))
382
383#if !defined(CORE_CM4)
384#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
385 ((NUMBER) == MPU_REGION_NUMBER1) || \
386 ((NUMBER) == MPU_REGION_NUMBER2) || \
387 ((NUMBER) == MPU_REGION_NUMBER3) || \
388 ((NUMBER) == MPU_REGION_NUMBER4) || \
389 ((NUMBER) == MPU_REGION_NUMBER5) || \
390 ((NUMBER) == MPU_REGION_NUMBER6) || \
391 ((NUMBER) == MPU_REGION_NUMBER7) || \
392 ((NUMBER) == MPU_REGION_NUMBER8) || \
393 ((NUMBER) == MPU_REGION_NUMBER9) || \
394 ((NUMBER) == MPU_REGION_NUMBER10) || \
395 ((NUMBER) == MPU_REGION_NUMBER11) || \
396 ((NUMBER) == MPU_REGION_NUMBER12) || \
397 ((NUMBER) == MPU_REGION_NUMBER13) || \
398 ((NUMBER) == MPU_REGION_NUMBER14) || \
399 ((NUMBER) == MPU_REGION_NUMBER15))
400#else
401#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
402 ((NUMBER) == MPU_REGION_NUMBER1) || \
403 ((NUMBER) == MPU_REGION_NUMBER2) || \
404 ((NUMBER) == MPU_REGION_NUMBER3) || \
405 ((NUMBER) == MPU_REGION_NUMBER4) || \
406 ((NUMBER) == MPU_REGION_NUMBER5) || \
407 ((NUMBER) == MPU_REGION_NUMBER6) || \
408 ((NUMBER) == MPU_REGION_NUMBER7))
409#endif /* !defined(CORE_CM4) */
410
411#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
412 ((SIZE) == MPU_REGION_SIZE_64B) || \
413 ((SIZE) == MPU_REGION_SIZE_128B) || \
414 ((SIZE) == MPU_REGION_SIZE_256B) || \
415 ((SIZE) == MPU_REGION_SIZE_512B) || \
416 ((SIZE) == MPU_REGION_SIZE_1KB) || \
417 ((SIZE) == MPU_REGION_SIZE_2KB) || \
418 ((SIZE) == MPU_REGION_SIZE_4KB) || \
419 ((SIZE) == MPU_REGION_SIZE_8KB) || \
420 ((SIZE) == MPU_REGION_SIZE_16KB) || \
421 ((SIZE) == MPU_REGION_SIZE_32KB) || \
422 ((SIZE) == MPU_REGION_SIZE_64KB) || \
423 ((SIZE) == MPU_REGION_SIZE_128KB) || \
424 ((SIZE) == MPU_REGION_SIZE_256KB) || \
425 ((SIZE) == MPU_REGION_SIZE_512KB) || \
426 ((SIZE) == MPU_REGION_SIZE_1MB) || \
427 ((SIZE) == MPU_REGION_SIZE_2MB) || \
428 ((SIZE) == MPU_REGION_SIZE_4MB) || \
429 ((SIZE) == MPU_REGION_SIZE_8MB) || \
430 ((SIZE) == MPU_REGION_SIZE_16MB) || \
431 ((SIZE) == MPU_REGION_SIZE_32MB) || \
432 ((SIZE) == MPU_REGION_SIZE_64MB) || \
433 ((SIZE) == MPU_REGION_SIZE_128MB) || \
434 ((SIZE) == MPU_REGION_SIZE_256MB) || \
435 ((SIZE) == MPU_REGION_SIZE_512MB) || \
436 ((SIZE) == MPU_REGION_SIZE_1GB) || \
437 ((SIZE) == MPU_REGION_SIZE_2GB) || \
438 ((SIZE) == MPU_REGION_SIZE_4GB))
439
440#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
441#endif /* __MPU_PRESENT */
442
443/**
444 * @}
445 */
446
447/**
448 * @}
449 */
450
451/**
452 * @}
453 */
454
455#ifdef __cplusplus
456}
457#endif
458
459#endif /* STM32H7xx_HAL_CORTEX_H */
460
461
HAL_NVIC_DisableIRQ
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
HAL_NVIC_SetPriority
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
HAL_NVIC_EnableIRQ
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
HAL_SYSTICK_Config
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
HAL_NVIC_SystemReset
void HAL_NVIC_SystemReset(void)
HAL_NVIC_SetPriorityGrouping
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
HAL_NVIC_ClearPendingIRQ
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
HAL_SYSTICK_CLKSourceConfig
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
HAL_NVIC_GetPendingIRQ
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
HAL_GetCurrentCPUID
uint32_t HAL_GetCurrentCPUID(void)
HAL_SYSTICK_Callback
void HAL_SYSTICK_Callback(void)
HAL_SYSTICK_IRQHandler
void HAL_SYSTICK_IRQHandler(void)
HAL_NVIC_GetPriority
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
HAL_NVIC_GetPriorityGrouping
uint32_t HAL_NVIC_GetPriorityGrouping(void)
HAL_NVIC_GetActive
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
HAL_NVIC_SetPendingIRQ
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32h723xx.h:49
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.