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stm32h7xx_ll_adc.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_ADC_H
21#define STM32H7xx_LL_ADC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36/** @defgroup ADC_LL ADC
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
44/** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48/* Internal mask for ADC calibration: */
49/* Internal register offset for ADC calibration factors configuration */
50
51/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
52/* the relevant bits for: */
53/* (concatenation of multiple bits used in different registers) */
54/* - ADC calibration configuration: configuration before calibration start */
55/* - ADC calibration factors: register offset */
56#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
57#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
58#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
59#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
60#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
61
62
63/* Internal mask for ADC group regular sequencer: */
64/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
65/* - sequencer register offset */
66/* - sequencer rank bits position into the selected register */
67
68/* Internal register offset for ADC group regular sequencer configuration */
69/* (offset placed into a spare area of literal definition) */
70#define ADC_SQR1_REGOFFSET (0x00000000UL)
71#define ADC_SQR2_REGOFFSET (0x00000100UL)
72#define ADC_SQR3_REGOFFSET (0x00000200UL)
73#define ADC_SQR4_REGOFFSET (0x00000300UL)
74
75#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
76#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
77#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
78
79/* Definition of ADC group regular sequencer bits information to be inserted */
80/* into ADC group regular sequencer ranks literals definition. */
81#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
82#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
83#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
84#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
85#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
86#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
87#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
88#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
89#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
90#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
91#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
92#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
93#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
94#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
95#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
96#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
97
98
99
100/* Internal mask for ADC group injected sequencer: */
101/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
102/* - data register offset */
103/* - sequencer rank bits position into the selected register */
104
105/* Internal register offset for ADC group injected data register */
106/* (offset placed into a spare area of literal definition) */
107#define ADC_JDR1_REGOFFSET (0x00000000UL)
108#define ADC_JDR2_REGOFFSET (0x00000100UL)
109#define ADC_JDR3_REGOFFSET (0x00000200UL)
110#define ADC_JDR4_REGOFFSET (0x00000300UL)
111
112#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
113#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
114#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
115
116/* Definition of ADC group injected sequencer bits information to be inserted */
117/* into ADC group injected sequencer ranks literals definition. */
118#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
119#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
120#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
121#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
122
123
124
125/* Internal mask for ADC group regular trigger: */
126/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
127/* - regular trigger source */
128/* - regular trigger edge */
129#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
130
131/* Mask containing trigger source masks for each of possible */
132/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
133/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
134#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
135 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
136 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
138
139/* Mask containing trigger edge masks for each of possible */
140/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
141/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
142#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
143 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
144 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
146
147/* Definition of ADC group regular trigger bits information. */
148#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
149#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
150
151
152
153/* Internal mask for ADC group injected trigger: */
154/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
155/* - injected trigger source */
156/* - injected trigger edge */
157#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
158
159/* Mask containing trigger source masks for each of possible */
160/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
161/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
162#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
163 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
164 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
166
167/* Mask containing trigger edge masks for each of possible */
168/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
169/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
170#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
171 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
172 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
174
175/* Definition of ADC group injected trigger bits information. */
176#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
177#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
178
179
180
181
182
183
184/* Internal mask for ADC channel: */
185/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
186/* - channel identifier defined by number */
187/* - channel identifier defined by bitfield */
188/* - channel differentiation between external channels (connected to */
189/* GPIO pins) and internal channels (connected to internal paths) */
190/* - channel sampling time defined by SMPRx register offset */
191/* and SMPx bits positions into SMPRx register */
192#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
193#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
194#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
195#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
196/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
197#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
198
199/* Channel differentiation between external and internal channels */
200#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
201#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
202
203/* Internal register offset for ADC channel sampling time configuration */
204/* (offset placed into a spare area of literal definition) */
205#define ADC_SMPR1_REGOFFSET (0x00000000UL)
206#define ADC_SMPR2_REGOFFSET (0x02000000UL)
207#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
208#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
209
210#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
211#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
212
213/* Definition of channels ID number information to be inserted into */
214/* channels literals definition. */
215#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
216#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
217#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
218#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
219#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
220#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
221#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
222#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
223#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
224#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
225#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
226#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
227#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
228#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
229#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
230#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
231#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
232#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
233#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
234#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
235
236/* Definition of channels ID bitfield information to be inserted into */
237/* channels literals definition. */
238#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
239#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
240#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
241#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
242#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
243#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
244#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
245#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
246#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
247#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
248#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
249#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
250#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
251#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
252#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
253#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
254#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
255#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
256#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
257#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
258
259/* Definition of channels sampling time information to be inserted into */
260/* channels literals definition. */
261#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
262#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
263#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
264#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
265#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
266#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
267#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
268#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
269#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
270#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
271#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
272#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
273#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
274#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
275#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
276#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
277#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
278#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
279#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
280#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
281
282
283/* Internal mask for ADC mode single or differential ended: */
284/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
285/* the relevant bits for: */
286/* (concatenation of multiple bits used in different registers) */
287/* - ADC calibration: calibration start, calibration factor get or set */
288/* - ADC channels: set each ADC channel ending mode */
289#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
290#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
291#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
292#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
293#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
294#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
295#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
296
297/* Internal mask for ADC analog watchdog: */
298/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
299/* (concatenation of multiple bits used in different analog watchdogs, */
300/* (feature of several watchdogs not available on all STM32 families)). */
301/* - analog watchdog 1: monitored channel defined by number, */
302/* selection of ADC group (ADC groups regular and-or injected). */
303/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
304/* selection on groups. */
305
306/* Internal register offset for ADC analog watchdog channel configuration */
307#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
308#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
309#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
310
311/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
312/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
313#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
314#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
315
316#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
317
318#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
319#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
320#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
321
322#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
323
324/* Internal register offset for ADC analog watchdog threshold configuration */
325#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
326#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
327#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
328#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
329#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
330#if defined(ADC_VER_V5_V90)
331#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
332#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
333#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
334#endif /* ADC_VER_V5_V90 */
335
336/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
337/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
338#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
339#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
340
341/* Legacy literals */
342#define LL_ADC_AWD1_TR LL_ADC_AWD1
343#define LL_ADC_AWD2_TR LL_ADC_AWD2
344#define LL_ADC_AWD3_TR LL_ADC_AWD3
345
346/* Internal mask for ADC offset: */
347/* Internal register offset for ADC offset number configuration */
348#define ADC_OFR1_REGOFFSET (0x00000000UL)
349#define ADC_OFR2_REGOFFSET (0x00000001UL)
350#define ADC_OFR3_REGOFFSET (0x00000002UL)
351#define ADC_OFR4_REGOFFSET (0x00000003UL)
352#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
353
354
355/* ADC registers bits positions */
356#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
357#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
358#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
359#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
360#if defined(ADC_VER_V5_V90)
361#define ADC_CFGR_RES_BITOFFSET_POS_ADC3 (ADC3_CFGR_RES_Pos)
362#endif /* ADC_VER_V5_V90 */
363
364
365/* ADC registers bits groups */
366#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
367
368
369/* ADC internal channels related definitions */
370/* Internal voltage reference VrefInt */
371#if defined(ADC_VER_V5_3)
372#define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
373 /* Address related to STM32H7A3 */
374#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
375#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
376#endif /* ADC_VER_V5_3 */
377#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
378/* Temperature sensor */
379#if defined(ADC_VER_V5_3)
380#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
381#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
382 /* Addresses related to STM32H7A3 */
383#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
384#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
385#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
386#endif /* ADC_VER_V5_3 */
387
388#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
389#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx)
390#define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor ,
391 temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
392 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */
393#else
394#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been
395 calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
396#endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */
397#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
398
399/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
400#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
401#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
402#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
403#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
404#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
405#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
406#define ADC_LINEAR_CALIB_REG_COUNT (6UL)
407/**
408 * @}
409 */
410
411/** @defgroup ADC_LL_Alias_definition ADC Alias definition
412 * @{
413 */
414#define LL_ADC_SetChannelPreSelection LL_ADC_SetChannelPreselection /* Alias of LL_ADC_SetChannelPreselection for backward compatibility. */
415
416/**
417 * @}
418 */
419
420/* Private macros ------------------------------------------------------------*/
421/** @defgroup ADC_LL_Private_Macros ADC Private Macros
422 * @{
423 */
424
425/**
426 * @brief Driver macro reserved for internal use: set a pointer to
427 * a register from a register basis from which an offset
428 * is applied.
429 * @param __REG__ Register basis from which the offset is applied.
430 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
431 * @retval Pointer to register address
432 */
433#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
434 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
435
436/**
437 * @}
438 */
439
440
441/* Exported types ------------------------------------------------------------*/
442#if defined(USE_FULL_LL_DRIVER)
443/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
444 * @{
445 */
446
447/**
448 * @brief Structure definition of some features of ADC common parameters
449 * and multimode
450 * (all ADC instances belonging to the same ADC common instance).
451 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
452 * is conditioned to ADC instances state (all ADC instances
453 * sharing the same ADC common instance):
454 * All ADC instances sharing the same ADC common instance must be
455 * disabled.
456 */
457typedef struct
458{
459 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
460 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
461 @note On this STM32 series, if ADC group injected is used, some
462 clock ratio constraints between ADC clock and AHB clock
463 must be respected. Refer to reference manual.
464
465 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
466
467 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
468 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
469
470 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
471
472 uint32_t MultiDMATransfer; /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.
473 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
474
475 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
476
477 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
478 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
479
480 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
481
482} LL_ADC_CommonInitTypeDef;
483
484/**
485 * @brief Structure definition of some features of ADC instance.
486 * @note These parameters have an impact on ADC scope: ADC instance.
487 * Affects both group regular and group injected (availability
488 * of ADC group injected depends on STM32 families).
489 * Refer to corresponding unitary functions into
490 * @ref ADC_LL_EF_Configuration_ADC_Instance .
491 * @note The setting of these parameters by function @ref LL_ADC_Init()
492 * is conditioned to ADC state:
493 * ADC instance must be disabled.
494 * This condition is applied to all ADC features, for efficiency
495 * and compatibility over all STM32 families. However, the different
496 * features can be set under different ADC state conditions
497 * (setting possible with ADC enabled without conversion on going,
498 * ADC enabled with conversion on going, ...)
499 * Each feature can be updated afterwards with a unitary function
500 * and potentially with ADC in a different state than disabled,
501 * refer to description of each function for setting
502 * conditioned to ADC state.
503 */
504typedef struct
505{
506 uint32_t Resolution; /*!< Set ADC resolution.
507 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
508
509 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
510
511 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
512 This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
513
514 uint32_t LowPowerMode; /*!< Set ADC low power mode.
515 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
516
517 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
518
519} LL_ADC_InitTypeDef;
520
521/**
522 * @brief Structure definition of some features of ADC group regular.
523 * @note These parameters have an impact on ADC scope: ADC group regular.
524 * Refer to corresponding unitary functions into
525 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
526 * (functions with prefix "REG").
527 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
528 * is conditioned to ADC state:
529 * ADC instance must be disabled.
530 * This condition is applied to all ADC features, for efficiency
531 * and compatibility over all STM32 families. However, the different
532 * features can be set under different ADC state conditions
533 * (setting possible with ADC enabled without conversion on going,
534 * ADC enabled with conversion on going, ...)
535 * Each feature can be updated afterwards with a unitary function
536 * and potentially with ADC in a different state than disabled,
537 * refer to description of each function for setting
538 * conditioned to ADC state.
539 */
540typedef struct
541{
542 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
543 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
544 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
545 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
546 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
547
548 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
549
550 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
551 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
552
553 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
554
555 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
556 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
557 @note This parameter has an effect only if group regular sequencer is enabled
558 (scan length of 2 ranks or more).
559
560 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
561
562 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
563 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
564 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
565
566 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
567
568 uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.
569 This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
570
571 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */
572
573 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
574 data preserved or overwritten.
575 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
576
577 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
578
579} LL_ADC_REG_InitTypeDef;
580
581/**
582 * @brief Structure definition of some features of ADC group injected.
583 * @note These parameters have an impact on ADC scope: ADC group injected.
584 * Refer to corresponding unitary functions into
585 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
586 * (functions with prefix "INJ").
587 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
588 * is conditioned to ADC state:
589 * ADC instance must be disabled.
590 * This condition is applied to all ADC features, for efficiency
591 * and compatibility over all STM32 families. However, the different
592 * features can be set under different ADC state conditions
593 * (setting possible with ADC enabled without conversion on going,
594 * ADC enabled with conversion on going, ...)
595 * Each feature can be updated afterwards with a unitary function
596 * and potentially with ADC in a different state than disabled,
597 * refer to description of each function for setting
598 * conditioned to ADC state.
599 */
600typedef struct
601{
602 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
603 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
604 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
605 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
606 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
607
608 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
609
610 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
611 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
612
613 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
614
615 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
616 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
617 @note This parameter has an effect only if group injected sequencer is enabled
618 (scan length of 2 ranks or more).
619
620 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
621
622 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
623 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
624 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
625
626 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
627
628} LL_ADC_INJ_InitTypeDef;
629
630/**
631 * @}
632 */
633#endif /* USE_FULL_LL_DRIVER */
634
635/* Exported constants --------------------------------------------------------*/
636/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
637 * @{
638 */
639
640/** @defgroup ADC_LL_EC_FLAG ADC flags
641 * @brief Flags defines which can be used with LL_ADC_ReadReg function
642 * @{
643 */
644#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
645#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
646#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
647#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
648#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
649#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
650#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
651#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
652#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
653#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
654#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
655#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag ADC LDO output voltage ready bit */
656#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
657#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
658#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
659#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
660#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
661#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
662#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
663#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
664#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
665#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
666#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
667#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
668#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
669#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
670#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
671#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
672#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
673#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
674#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
675#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
676#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
677#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
678/**
679 * @}
680 */
681
682/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
683 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
684 * @{
685 */
686#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
687#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
688#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
689#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
690#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
691#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
692#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
693#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
694#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
695#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
696#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
697/**
698 * @}
699 */
700
701/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
702 * @{
703 */
704/* List of ADC registers intended to be used (most commonly) with */
705/* DMA transfer. */
706/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
707#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
708#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
709/**
710 * @}
711 */
712
713/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
714 * @{
715 */
716#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
717#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
718#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
719#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
720#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
721#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
722#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
723#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
724#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
725#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
726#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
727#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
728#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
729#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
730#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
731/**
732 * @}
733 */
734
735/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
736 * @{
737 */
738/* Note: Other measurement paths to internal channels may be available */
739/* (connections to other peripherals). */
740/* If they are not listed below, they do not require any specific */
741/* path enable. In this case, Access to measurement path is done */
742/* only by selecting the corresponding ADC internal channel. */
743#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
744#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
745#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
746#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
747/**
748 * @}
749 */
750
751/** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode
752 * @{
753 */
754#define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL) /*!< Boost mode is configured for frequency <= 6.25Mhz */
755#define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0) /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */
756#define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz */
757#define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 20Mhz < frequency <= 25Mhz */
758#define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0) /*!< Boost mode is configured for frequency > 25Mhz */
759/**
760 * @}
761 */
762
763/** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
764 * @{
765 */
766#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */
767#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET) /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */
768#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */
769/**
770 * @}
771 */
772
773/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words
774 * @{
775 */
776#define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1) /*!< ADC calibration linearity word 1 */
777#define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2) /*!< ADC calibration linearity word 2 */
778#define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3) /*!< ADC calibration linearity word 3 */
779#define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4) /*!< ADC calibration linearity word 4 */
780#define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5) /*!< ADC calibration linearity word 5 */
781#define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6) /*!< ADC calibration linearity word 6 */
782/**
783 * @}
784 */
785
786/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
787 * @{
788 */
789#define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */
790#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
791#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */
792#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
793
794#if defined (ADC_VER_V5_X)
795#define LL_ADC_RESOLUTION_14B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_0) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */
796#define LL_ADC_RESOLUTION_12B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */
797#endif
798
799#if defined (ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
800#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 8 bits */
801#else
802#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */
803 /*!< The resolution setting is managed internally in the driver:
804 "LL_ADC_RESOLUTION_8B" definition: keep using the "100b" value (corresponding to STM32H74x/5x rev Y).
805 Rev.V value "111b" is handled through functions "LL_ADC_SetResolution/LL_ADC_GetResolution" with a dedicated check on DBGMCU IDCODE register */
806#endif
807#if defined(ADC_VER_V5_V90)
808#define LL_ADC_RESOLUTION_6B (ADC3_CFGR_RES_1 | ADC3_CFGR_RES_0) /*!< ADC resolution 6 bits. Value available for ADC3 on STM32H72xx/3xx devices only*/
809#endif /* ADC_VER_V5_V90 */
810/**
811 * @}
812 */
813
814#if defined(ADC_VER_V5_V90)
815/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
816 * @{
817 */
818#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
819#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
820/**
821 * @}
822 */
823
824#endif /* ADC_VER_V5_V90 */
825
826/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
827 * @{
828 */
829#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
830#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
831#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
832#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
833#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
834#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
835#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
836#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
837#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
838#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
839#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
840#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
841#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
842#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
843#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
844#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
845/**
846 * @}
847 */
848
849/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
850 * @{
851 */
852#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
853#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
854/**
855 * @}
856 */
857
858/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
859 * @{
860 */
861#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
862#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
863#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
864#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
865/**
866 * @}
867 */
868
869/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
870 * @{
871 */
872#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
873#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
874/**
875 * @}
876 */
877
878/** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift
879 * @{
880 */
881#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */
882#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shift is enabled (among ADC selected offset number 1, 2, 3 or 4) */
883/**
884 * @}
885 */
886#if defined(ADC_VER_V5_V90)
887/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
888 * @{
889 */
890#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
891#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC3_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
892/**
893 * @}
894 */
895
896/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
897 * @{
898 */
899#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
900#define LL_ADC_OFFSET_ENABLE (ADC3_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
901/**
902 * @}
903 */
904#if defined(ADC_VER_V5_V90)
905/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
906 * @{
907 */
908#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
909#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
910/**
911 * @}
912 */
913#endif /* ADC_VER_V5_V90 */
914
915#endif /* ADC_VER_V5_V90 */
916
917/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
918 * @{
919 */
920#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
921#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
922#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
923/**
924 * @}
925 */
926
927/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
928 * @{
929 */
930#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
931#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
932#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
933#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
934#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
935#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
936#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
937#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
938#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
939#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
940#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
941#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
942#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
943#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
944#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
945#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
946#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
947#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
948#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
949#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
950#if defined(ADC3)
951#if defined(ADC_VER_V5_V90)
952#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
953#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
954#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
955#else
956#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
957#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
958#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
959#endif /* ADC_VER_V5_V90 */
960#else
961/*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
962#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */
963#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC2. */
964#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC2. */
965#endif
966#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
967#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
968#if defined(DAC2)
969/*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
970#define LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
971#endif
972/**
973 * @}
974 */
975
976/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
977 * @{
978 */
979#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
980#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
981#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
982#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
983#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
984#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
985#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
986#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
987#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
988#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
989#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
990#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
991#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
992#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
993#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
994#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
995#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
996#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
997#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */
998#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
999#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
1000#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
1001#if defined (TIM23)
1002#define LL_ADC_REG_TRIG_EXT_TIM23_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
1003#endif /* TIM23 */
1004#if defined (TIM24)
1005#define LL_ADC_REG_TRIG_EXT_TIM24_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
1006#endif /* TIM24 */
1007/**
1008 * @}
1009 */
1010
1011/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1012 * @{
1013 */
1014#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
1015#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
1016#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
1017/**
1018 * @}
1019 */
1020#if defined(ADC_VER_V5_V90)
1021 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1022 * @{
1023 */
1024#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. On devices STM32H72xx and STM32H73xx */
1025#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
1026 Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME). On devices STM32H72xx and STM32H73xx */
1027#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
1028 Trigger rising edge = start sampling
1029 Trigger falling edge = stop sampling and start conversion. On devices STM32H72xx and STM32H73xx */
1030/**
1031 * @}
1032 */
1033#endif /* ADC_VER_V5_V90 */
1034
1035/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1036* @{
1037*/
1038#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
1039#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
1040/**
1041 * @}
1042 */
1043
1044/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
1045 * @{
1046 */
1047#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
1048#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
1049#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
1050#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
1051/**
1052 * @}
1053 */
1054
1055#if defined(ADC_VER_V5_V90)
1056/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1057 * @{
1058 */
1059
1060#define LL_ADC3_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA. On ADC3 of devices STM32H72xx and STM32H73xx */
1061#define LL_ADC3_REG_DMA_TRANSFER_LIMITED ( ADC3_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. On ADC3 of devices STM32H72xx and STM32H73xx */
1062#define LL_ADC3_REG_DMA_TRANSFER_UNLIMITED (ADC3_CFGR_DMACFG | ADC3_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. On ADC3 of devices STM32H72xx and STM32H73xx*/
1063/**
1064 * @}
1065 */
1066#endif /* ADC_VER_V5_V90 */
1067
1068/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1069* @{
1070*/
1071#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
1072#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
1073/**
1074 * @}
1075 */
1076
1077/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1078 * @{
1079 */
1080#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1081#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1082#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1083#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1084#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1085#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1086#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1087#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1088#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
1089#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
1090#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1091#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1092#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1093#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1094#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1095#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1096/**
1097 * @}
1098 */
1099
1100/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1101 * @{
1102 */
1103#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1104#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1105#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1106#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1107#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1108#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1109#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1110#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1111#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1112/**
1113 * @}
1114 */
1115
1116/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1117 * @{
1118 */
1119#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1120#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1121#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1122#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1123#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1124#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1125#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1126#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1127#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1128#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1129#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1130#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1131#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1132#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1133#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1134#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1135/**
1136 * @}
1137 */
1138
1139/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1140 * @{
1141 */
1142#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
1143#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
1144#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1145#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
1146#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1147#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1148#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1149#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1150#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1151#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1152#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1153#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1154#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1155#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1156#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1157#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1158#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1159#if defined(HRTIM1)
1160#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
1161#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
1162#endif /* HRTIM1 */
1163#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
1164#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
1165#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1166#define LL_ADC_INJ_TRIG_EXT_TIM23_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
1167#define LL_ADC_INJ_TRIG_EXT_TIM24_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
1168/**
1169 * @}
1170 */
1171
1172/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1173 * @{
1174 */
1175#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1176#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1177#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1178/**
1179 * @}
1180 */
1181
1182/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1183* @{
1184*/
1185#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1186#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1187/**
1188 * @}
1189 */
1190
1191/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1192 * @{
1193 */
1194#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1195#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1196#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1197/**
1198 * @}
1199 */
1200
1201/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1202 * @{
1203 */
1204#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1205#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1206#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1207#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1208/**
1209 * @}
1210 */
1211
1212/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1213 * @{
1214 */
1215#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1216#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1217/**
1218 * @}
1219 */
1220
1221/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1222 * @{
1223 */
1224#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1225#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1226#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1227#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1228/**
1229 * @}
1230 */
1231
1232/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1233 * @{
1234 */
1235#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycles */
1236#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1237#define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 8.5 ADC clock cycles */
1238#define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */
1239#define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 32.5 ADC clock cycles */
1240#define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */
1241#define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 387.5 ADC clock cycles */
1242#define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */
1243/**
1244 * @}
1245 */
1246#if defined(ADC_VER_V5_V90)
1247/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1248 * @{
1249 */
1250#define LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1251#define LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1252#define LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1253#define LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1254#define LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1255#define LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1256#define LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1257#define LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1258/**
1259 * @}
1260 */
1261#endif /* ADC_VER_V5_V90 */
1262
1263/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1264 * @{
1265 */
1266#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1267#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1268#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1269/**
1270 * @}
1271 */
1272
1273/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1274 * @{
1275 */
1276#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1277#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1278#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1279/**
1280 * @}
1281 */
1282
1283/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1284 * @{
1285 */
1286#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1287#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1288#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1289#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1290#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1291#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1292#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1293#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1294#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1295#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1296#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1297#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1298#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1299#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1300#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1301#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1302#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1303#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1304#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1305#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1306#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1307#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1308#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1309#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1310#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1311#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1312#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1313#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1314#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1315#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1316#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1317#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1318#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1319#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1320#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1321#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1322#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1323#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1324#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1325#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1326#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1327#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1328#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1329#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1330#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1331#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1332#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1333#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1334#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1335#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1336#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1337#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1338#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1339#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1340#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1341#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1342#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1343#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1344#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1345#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1346#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1347#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1348#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1349#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1350#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1351#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1352#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1353#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1354#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1355#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1356#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
1357#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
1358#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
1359#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1360#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1361#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1362#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1363#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1364#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1365/**
1366 * @}
1367 */
1368
1369/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1370 * @{
1371 */
1372#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
1373#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
1374/**
1375 * @}
1376 */
1377#if defined(ADC_VER_V5_V90)
1378/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1379 * @{
1380 */
1381#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1382#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1383#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 ) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1384#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1385#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 ) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1386#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1387#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 ) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1388#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1389/**
1390 * @}
1391 */
1392#endif /* ADC_VER_V5_V90 */
1393
1394/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1395 * @{
1396 */
1397#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1398#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1399#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1400#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1401#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1402/**
1403 * @}
1404 */
1405
1406/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1407 * @{
1408 */
1409#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1410#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1411/**
1412 * @}
1413 */
1414#if defined(ADC_VER_V5_V90)
1415/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1416 * @{
1417 */
1418#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1419#define LL_ADC_OVS_RATIO_4 ( ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1420#define LL_ADC_OVS_RATIO_8 ( ADC3_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1421#define LL_ADC_OVS_RATIO_16 ( ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1422#define LL_ADC_OVS_RATIO_32 (ADC3_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1423#define LL_ADC_OVS_RATIO_64 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1424#define LL_ADC_OVS_RATIO_128 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1425#define LL_ADC_OVS_RATIO_256 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1426/**
1427 * @}
1428 */
1429#endif /* ADC_VER_V5_V90 */
1430
1431/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1432 * @{
1433 */
1434#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1435#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1436#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1437#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1438#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1439#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1440#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1441#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1442#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1443#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
1444#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
1445#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
1446/**
1447 * @}
1448 */
1449
1450/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1451 * @{
1452 */
1453#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1454#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1455#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1456#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1457#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1458#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1459#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1460#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1461/**
1462 * @}
1463 */
1464
1465/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1466 * @{
1467 */
1468#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1469#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
1470#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
1471/**
1472 * @}
1473 */
1474
1475/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1476 * @{
1477 */
1478#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */
1479#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */
1480#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */
1481#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */
1482#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */
1483#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */
1484#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */
1485#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution */
1486#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */
1487#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */
1488#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */
1489#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution */
1490#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution */
1491/**
1492 * @}
1493 */
1494
1495/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1496 * @{
1497 */
1498#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1499#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1500#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1501/**
1502 * @}
1503 */
1504
1505
1506
1507/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1508 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1509 * not timeout values.
1510 * For details on delays values, refer to descriptions in source code
1511 * above each literal definition.
1512 * @{
1513 */
1514
1515/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1516/* not timeout values. */
1517/* Timeout values for ADC operations are dependent to device clock */
1518/* configuration (system clock versus ADC clock), */
1519/* and therefore must be defined in user application. */
1520/* Indications for estimation of ADC timeout delays, for this */
1521/* STM32 series: */
1522/* - ADC calibration time: maximum delay is 16384/fADC. */
1523/* (refer to device datasheet, parameter "tCAL") */
1524/* - ADC enable time: maximum delay is 1 conversion cycle. */
1525/* (refer to device datasheet, parameter "tSTAB") */
1526/* - ADC disable time: maximum delay should be a few ADC clock cycles */
1527/* - ADC stop conversion time: maximum delay should be a few ADC clock */
1528/* cycles */
1529/* - ADC conversion time: duration depending on ADC clock and ADC */
1530/* configuration. */
1531/* (refer to device reference manual, section "Timing") */
1532
1533/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1534/* Delay set to maximum value (refer to device datasheet, */
1535/* parameter "tADCVREG_STUP"). */
1536/* Unit: us */
1537#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1538
1539/* Delay for internal voltage reference stabilization time. */
1540/* Delay set to maximum value (refer to device datasheet, */
1541/* parameter "ts_vrefint"). */
1542/* Unit: us */
1543#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
1544
1545/* Delay for temperature sensor stabilization time. */
1546/* Literal set to maximum value (refer to device datasheet, */
1547/* parameter "tSTART_RUN"). */
1548/* Unit: us */
1549#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
1550
1551/* Delay required between ADC end of calibration and ADC enable. */
1552/* Note: On this STM32 series, a minimum number of ADC clock cycles */
1553/* are required between ADC end of calibration and ADC enable. */
1554/* Wait time can be computed in user application by waiting for the */
1555/* equivalent number of CPU cycles, by taking into account */
1556/* ratio of CPU clock versus ADC clock prescalers. */
1557/* Unit: ADC clock cycles. */
1558#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1559
1560/* Fixed timeout value for ADC linearity word bit set/clear delay. */
1561/* Values defined to be higher than worst cases: low clock frequency, */
1562/* maximum prescalers. */
1563/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
1564/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
1565/* 6 / 4577 = 1,311ms */
1566/* At maximum CPU speed (400 MHz), this means */
1567/* 3.58 * 400 MHz = 524400 CPU cycles */
1568#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
1569
1570/**
1571 * @}
1572 */
1573
1574/**
1575 * @}
1576 */
1577
1578
1579/* Exported macro ------------------------------------------------------------*/
1580/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1581 * @{
1582 */
1583
1584/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1585 * @{
1586 */
1587
1588/**
1589 * @brief Write a value in ADC register
1590 * @param __INSTANCE__ ADC Instance
1591 * @param __REG__ Register to be written
1592 * @param __VALUE__ Value to be written in the register
1593 * @retval None
1594 */
1595#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1596
1597/**
1598 * @brief Read a value in ADC register
1599 * @param __INSTANCE__ ADC Instance
1600 * @param __REG__ Register to be read
1601 * @retval Register value
1602 */
1603#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1604/**
1605 * @}
1606 */
1607
1608/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1609 * @{
1610 */
1611
1612#if defined(ADC_VER_V5_V90)
1613/**
1614 * @brief Helper macro to convert the resolution defines to STM32H73x/2x ADC3 registers values
1615 * value corresponding to the ADC3 resolution according to the STM32H73x/2x RefMan.
1616 * @note The input can be a value from ADC3 resolution (12b, 10b, 8b,6b)
1617 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1618 * @arg @ref LL_ADC_RESOLUTION_12B
1619 * @arg @ref LL_ADC_RESOLUTION_10B
1620 * @arg @ref LL_ADC_RESOLUTION_8B
1621 * @arg @ref LL_ADC_RESOLUTION_6B
1622 * @retval Returned value can be one of the following values:
1623 * @arg 0x00000000UL (value correspodning to ADC3 12 bits)
1624 * @arg ADC_CFGR_RES_0 = 0x00000004 (value corresponding to ADC3 10 bits)
1625 * @arg ADC_CFGR_RES_1 = 0x00000008 (value corresponding to ADC3 8 bits)
1626 * @arg 0x0000001C (value corresponding to ADC3 6 bits)
1627 * @note This helper macro is applicable for STM32H73x/2x devices only
1628 */
1629#define __LL_ADC12_RESOLUTION_TO_ADC3(__ADC_RESOLUTION__) \
1630 ( \
1631 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
1632 ?(0x00000000UL) \
1633 : \
1634 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
1635 ?(ADC_CFGR_RES_0) \
1636 : \
1637 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
1638 ?(ADC_CFGR_RES_1) \
1639 : \
1640 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
1641 ?((ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
1642 :(0x00000000UL) \
1643 )
1644
1645#endif /* ADC_VER_V5_V90 */
1646
1647/**
1648 * @brief Helper macro to get ADC channel number in decimal format
1649 * from literals LL_ADC_CHANNEL_x.
1650 * @note Example:
1651 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1652 * will return decimal number "4".
1653 * @note The input can be a value from functions where a channel
1654 * number is returned, either defined with number
1655 * or with bitfield (only one bit must be set).
1656 * @param __CHANNEL__ This parameter can be one of the following values:
1657 * @arg @ref LL_ADC_CHANNEL_0 (3)
1658 * @arg @ref LL_ADC_CHANNEL_1 (3)
1659 * @arg @ref LL_ADC_CHANNEL_2 (3)
1660 * @arg @ref LL_ADC_CHANNEL_3 (3)
1661 * @arg @ref LL_ADC_CHANNEL_4 (3)
1662 * @arg @ref LL_ADC_CHANNEL_5 (3)
1663 * @arg @ref LL_ADC_CHANNEL_6
1664 * @arg @ref LL_ADC_CHANNEL_7
1665 * @arg @ref LL_ADC_CHANNEL_8
1666 * @arg @ref LL_ADC_CHANNEL_9
1667 * @arg @ref LL_ADC_CHANNEL_10
1668 * @arg @ref LL_ADC_CHANNEL_11
1669 * @arg @ref LL_ADC_CHANNEL_12
1670 * @arg @ref LL_ADC_CHANNEL_13
1671 * @arg @ref LL_ADC_CHANNEL_14
1672 * @arg @ref LL_ADC_CHANNEL_15
1673 * @arg @ref LL_ADC_CHANNEL_16
1674 * @arg @ref LL_ADC_CHANNEL_17
1675 * @arg @ref LL_ADC_CHANNEL_18
1676 * @arg @ref LL_ADC_CHANNEL_19
1677 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1678 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1679 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1680 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1681 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1682 *
1683 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1684 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1685 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1686 * Other channels are slow channels (conversion rate: refer to reference manual).
1687 * @retval Value between Min_Data=0 and Max_Data=18
1688 */
1689#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1690 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1691 ? ( \
1692 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1693 ) \
1694 : \
1695 ( \
1696 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1697 ) \
1698 )
1699
1700/**
1701 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1702 * from number in decimal format.
1703 * @note Example:
1704 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1705 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1706 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1707 * @retval Returned value can be one of the following values:
1708 * @arg @ref LL_ADC_CHANNEL_0 (3)
1709 * @arg @ref LL_ADC_CHANNEL_1 (3)
1710 * @arg @ref LL_ADC_CHANNEL_2 (3)
1711 * @arg @ref LL_ADC_CHANNEL_3 (3)
1712 * @arg @ref LL_ADC_CHANNEL_4 (3)
1713 * @arg @ref LL_ADC_CHANNEL_5 (3)
1714 * @arg @ref LL_ADC_CHANNEL_6
1715 * @arg @ref LL_ADC_CHANNEL_7
1716 * @arg @ref LL_ADC_CHANNEL_8
1717 * @arg @ref LL_ADC_CHANNEL_9
1718 * @arg @ref LL_ADC_CHANNEL_10
1719 * @arg @ref LL_ADC_CHANNEL_11
1720 * @arg @ref LL_ADC_CHANNEL_12
1721 * @arg @ref LL_ADC_CHANNEL_13
1722 * @arg @ref LL_ADC_CHANNEL_14
1723 * @arg @ref LL_ADC_CHANNEL_15
1724 * @arg @ref LL_ADC_CHANNEL_16
1725 * @arg @ref LL_ADC_CHANNEL_17
1726 * @arg @ref LL_ADC_CHANNEL_18
1727 * @arg @ref LL_ADC_CHANNEL_19
1728 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1729 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1730 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1731 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1732 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1733 *
1734 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1735 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1736 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1737 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1738 * (1, 2) For ADC channel read back from ADC register,
1739 * comparison with internal channel parameter to be done
1740 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1741 */
1742#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1743 (((__DECIMAL_NB__) <= 9UL) \
1744 ? ( \
1745 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1746 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1747 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1748 ) \
1749 : \
1750 ( \
1751 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1752 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1753 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1754 ) \
1755 )
1756
1757/**
1758 * @brief Helper macro to determine whether the selected channel
1759 * corresponds to literal definitions of driver.
1760 * @note The different literal definitions of ADC channels are:
1761 * - ADC internal channel:
1762 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1763 * - ADC external channel (channel connected to a GPIO pin):
1764 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1765 * @note The channel parameter must be a value defined from literal
1766 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1767 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1768 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1769 * must not be a value from functions where a channel number is
1770 * returned from ADC registers,
1771 * because internal and external channels share the same channel
1772 * number in ADC registers. The differentiation is made only with
1773 * parameters definitions of driver.
1774 * @param __CHANNEL__ This parameter can be one of the following values:
1775 * @arg @ref LL_ADC_CHANNEL_0 (3)
1776 * @arg @ref LL_ADC_CHANNEL_1 (3)
1777 * @arg @ref LL_ADC_CHANNEL_2 (3)
1778 * @arg @ref LL_ADC_CHANNEL_3 (3)
1779 * @arg @ref LL_ADC_CHANNEL_4 (3)
1780 * @arg @ref LL_ADC_CHANNEL_5 (3)
1781 * @arg @ref LL_ADC_CHANNEL_6
1782 * @arg @ref LL_ADC_CHANNEL_7
1783 * @arg @ref LL_ADC_CHANNEL_8
1784 * @arg @ref LL_ADC_CHANNEL_9
1785 * @arg @ref LL_ADC_CHANNEL_10
1786 * @arg @ref LL_ADC_CHANNEL_11
1787 * @arg @ref LL_ADC_CHANNEL_12
1788 * @arg @ref LL_ADC_CHANNEL_13
1789 * @arg @ref LL_ADC_CHANNEL_14
1790 * @arg @ref LL_ADC_CHANNEL_15
1791 * @arg @ref LL_ADC_CHANNEL_16
1792 * @arg @ref LL_ADC_CHANNEL_17
1793 * @arg @ref LL_ADC_CHANNEL_18
1794 * @arg @ref LL_ADC_CHANNEL_19
1795 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1796 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1797 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1798 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1799 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1800 *
1801 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1802 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1803 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1804 * Other channels are slow channels (conversion rate: refer to reference manual).
1805 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1806 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1807 */
1808#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1809 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1810
1811/**
1812 * @brief Helper macro to convert a channel defined from parameter
1813 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1814 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1815 * to its equivalent parameter definition of a ADC external channel
1816 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1817 * @note The channel parameter can be, additionally to a value
1818 * defined from parameter definition of a ADC internal channel
1819 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1820 * a value defined from parameter definition of
1821 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1822 * or a value from functions where a channel number is returned
1823 * from ADC registers.
1824 * @param __CHANNEL__ This parameter can be one of the following values:
1825 * @arg @ref LL_ADC_CHANNEL_0 (3)
1826 * @arg @ref LL_ADC_CHANNEL_1 (3)
1827 * @arg @ref LL_ADC_CHANNEL_2 (3)
1828 * @arg @ref LL_ADC_CHANNEL_3 (3)
1829 * @arg @ref LL_ADC_CHANNEL_4 (3)
1830 * @arg @ref LL_ADC_CHANNEL_5 (3)
1831 * @arg @ref LL_ADC_CHANNEL_6
1832 * @arg @ref LL_ADC_CHANNEL_7
1833 * @arg @ref LL_ADC_CHANNEL_8
1834 * @arg @ref LL_ADC_CHANNEL_9
1835 * @arg @ref LL_ADC_CHANNEL_10
1836 * @arg @ref LL_ADC_CHANNEL_11
1837 * @arg @ref LL_ADC_CHANNEL_12
1838 * @arg @ref LL_ADC_CHANNEL_13
1839 * @arg @ref LL_ADC_CHANNEL_14
1840 * @arg @ref LL_ADC_CHANNEL_15
1841 * @arg @ref LL_ADC_CHANNEL_16
1842 * @arg @ref LL_ADC_CHANNEL_17
1843 * @arg @ref LL_ADC_CHANNEL_18
1844 * @arg @ref LL_ADC_CHANNEL_19
1845 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1846 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1847 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1848 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1849 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1850 *
1851 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1852 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1853 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1854 * Other channels are slow channels (conversion rate: refer to reference manual).
1855 * @retval Returned value can be one of the following values:
1856 * @arg @ref LL_ADC_CHANNEL_0
1857 * @arg @ref LL_ADC_CHANNEL_1
1858 * @arg @ref LL_ADC_CHANNEL_2
1859 * @arg @ref LL_ADC_CHANNEL_3
1860 * @arg @ref LL_ADC_CHANNEL_4
1861 * @arg @ref LL_ADC_CHANNEL_5
1862 * @arg @ref LL_ADC_CHANNEL_6
1863 * @arg @ref LL_ADC_CHANNEL_7
1864 * @arg @ref LL_ADC_CHANNEL_8
1865 * @arg @ref LL_ADC_CHANNEL_9
1866 * @arg @ref LL_ADC_CHANNEL_10
1867 * @arg @ref LL_ADC_CHANNEL_11
1868 * @arg @ref LL_ADC_CHANNEL_12
1869 * @arg @ref LL_ADC_CHANNEL_13
1870 * @arg @ref LL_ADC_CHANNEL_14
1871 * @arg @ref LL_ADC_CHANNEL_15
1872 * @arg @ref LL_ADC_CHANNEL_16
1873 * @arg @ref LL_ADC_CHANNEL_17
1874 * @arg @ref LL_ADC_CHANNEL_18
1875 * @arg @ref LL_ADC_CHANNEL_19
1876 */
1877#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1878 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1879
1880/**
1881 * @brief Helper macro to determine whether the internal channel
1882 * selected is available on the ADC instance selected.
1883 * @note The channel parameter must be a value defined from parameter
1884 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1885 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1886 * must not be a value defined from parameter definition of
1887 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1888 * or a value from functions where a channel number is
1889 * returned from ADC registers,
1890 * because internal and external channels share the same channel
1891 * number in ADC registers. The differentiation is made only with
1892 * parameters definitions of driver.
1893 * @param __ADC_INSTANCE__ ADC instance
1894 * @param __CHANNEL__ This parameter can be one of the following values:
1895 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1896 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1897 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1898 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1899 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1900 *
1901 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1902 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
1903 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1904 * Value "1" if the internal channel selected is available on the ADC instance selected.
1905 */
1906#if defined(ADC3)
1907#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1908 ((((__ADC_INSTANCE__) == ADC2) \
1909 &&( \
1910 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1911 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1912 ) \
1913 ) \
1914 || \
1915 (((__ADC_INSTANCE__) == ADC3) \
1916 &&( \
1917 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1918 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1919 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1920 ) \
1921 ) \
1922 )
1923#else
1924#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1925 ((((__ADC_INSTANCE__) == ADC2) \
1926 &&( \
1927 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1928 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) || \
1929 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1930 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1931 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1932 ) \
1933 ) \
1934 )
1935#endif
1936
1937/**
1938 * @brief Helper macro to define ADC analog watchdog parameter:
1939 * define a single channel to monitor with analog watchdog
1940 * from sequencer channel and groups definition.
1941 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1942 * Example:
1943 * LL_ADC_SetAnalogWDMonitChannels(
1944 * ADC1, LL_ADC_AWD1,
1945 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1946 * @param __CHANNEL__ This parameter can be one of the following values:
1947 * @arg @ref LL_ADC_CHANNEL_0 (3)
1948 * @arg @ref LL_ADC_CHANNEL_1 (3)
1949 * @arg @ref LL_ADC_CHANNEL_2 (3)
1950 * @arg @ref LL_ADC_CHANNEL_3 (3)
1951 * @arg @ref LL_ADC_CHANNEL_4 (3)
1952 * @arg @ref LL_ADC_CHANNEL_5 (3)
1953 * @arg @ref LL_ADC_CHANNEL_6
1954 * @arg @ref LL_ADC_CHANNEL_7
1955 * @arg @ref LL_ADC_CHANNEL_8
1956 * @arg @ref LL_ADC_CHANNEL_9
1957 * @arg @ref LL_ADC_CHANNEL_10
1958 * @arg @ref LL_ADC_CHANNEL_11
1959 * @arg @ref LL_ADC_CHANNEL_12
1960 * @arg @ref LL_ADC_CHANNEL_13
1961 * @arg @ref LL_ADC_CHANNEL_14
1962 * @arg @ref LL_ADC_CHANNEL_15
1963 * @arg @ref LL_ADC_CHANNEL_16
1964 * @arg @ref LL_ADC_CHANNEL_17
1965 * @arg @ref LL_ADC_CHANNEL_18
1966 * @arg @ref LL_ADC_CHANNEL_19
1967 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1968 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1969 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1970 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1971 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1972 *
1973 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1974 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1975 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1976 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1977 * (1, 2) For ADC channel read back from ADC register,
1978 * comparison with internal channel parameter to be done
1979 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1980 * @param __GROUP__ This parameter can be one of the following values:
1981 * @arg @ref LL_ADC_GROUP_REGULAR
1982 * @arg @ref LL_ADC_GROUP_INJECTED
1983 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1984 * @retval Returned value can be one of the following values:
1985 * @arg @ref LL_ADC_AWD_DISABLE
1986 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1987 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1988 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1989 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1990 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1991 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1992 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1993 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1994 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1995 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1996 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1997 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1998 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1999 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2000 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2001 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2002 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2003 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2004 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2005 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2006 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2007 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2008 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2009 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2010 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2011 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2012 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2013 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2014 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2015 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2016 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2017 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2018 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2019 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2020 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2021 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2022 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2023 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2024 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2025 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2026 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2027 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2028 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2029 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2030 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2031 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2032 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2033 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2034 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2035 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2036 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2037 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2038 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2039 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2040 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2041 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2042 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2043 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2044 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2045 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2046 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
2047 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
2048 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
2049 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2050 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2051 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2052 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2053 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2054 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2055 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2056 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2057 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2058 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
2059 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
2060 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
2061 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
2062 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
2063 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
2064 *
2065 * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
2066 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
2067 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
2068 */
2069#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2070 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2071 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2072 : \
2073 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2074 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2075 : \
2076 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2077 )
2078
2079/**
2080 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2081 * or low in function of ADC resolution, when ADC resolution is
2082 * different of 16 bits.
2083 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2084 * Example, with a ADC resolution of 8 bits, to set the value of
2085 * analog watchdog threshold high (on 18 bits):
2086 * LL_ADC_SetAnalogWDThresholds
2087 * (< ADCx param >,
2088 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)
2089 * );
2090 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2091 * @arg @ref LL_ADC_RESOLUTION_16B
2092 * @arg @ref LL_ADC_RESOLUTION_14B
2093 * @arg @ref LL_ADC_RESOLUTION_12B
2094 * @arg @ref LL_ADC_RESOLUTION_10B
2095 * @arg @ref LL_ADC_RESOLUTION_8B
2096 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2097 * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2098 */
2099#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2100 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2101
2102/**
2103 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2104 * or low in function of ADC resolution, when ADC resolution is
2105 * different of 16 bits.
2106 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2107 * Example, with a ADC resolution of 8 bits, to get the value of
2108 * analog watchdog threshold high (on 18 bits):
2109 * < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2110 * (LL_ADC_RESOLUTION_8B,
2111 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2112 * );
2113 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2114 * @arg @ref LL_ADC_RESOLUTION_16B
2115 * @arg @ref LL_ADC_RESOLUTION_14B
2116 * @arg @ref LL_ADC_RESOLUTION_12B
2117 * @arg @ref LL_ADC_RESOLUTION_10B
2118 * @arg @ref LL_ADC_RESOLUTION_8B
2119 * @param __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2120 * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2121 */
2122#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
2123 ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2124
2125/**
2126 * @brief Helper macro to set the ADC calibration value with both single ended
2127 * and differential modes calibration factors concatenated.
2128 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
2129 * Example, to set calibration factors single ended to 0x55
2130 * and differential ended to 0x2A:
2131 * LL_ADC_SetCalibrationOffsetFactor(
2132 * ADC1,
2133 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2134 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2135 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2136 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2137 */
2138#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2139 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2140
2141/**
2142 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2143 * or ADC slave from raw value with both ADC conversion data concatenated.
2144 * @note This macro is intended to be used when multimode transfer by DMA
2145 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2146 * In this case the transferred data need to processed with this macro
2147 * to separate the conversion data of ADC master and ADC slave.
2148 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2149 * @arg @ref LL_ADC_MULTI_MASTER
2150 * @arg @ref LL_ADC_MULTI_SLAVE
2151 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2152 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2153 */
2154#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2155 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2156
2157/**
2158 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2159 * it has a dependence in multimode (ADC master of the corresponding
2160 * ADC common instance).
2161 * @note In case of device with multimode available and a mix of
2162 * ADC instances compliant and not compliant with multimode feature,
2163 * ADC instances not compliant with multimode feature are
2164 * considered as master instances (do not depend to
2165 * any other ADC instance).
2166 * @param __ADCx__ ADC instance
2167 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2168 */
2169#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2170 ( ( ((__ADCx__) == ADC2) \
2171 )? \
2172 (ADC1) \
2173 : \
2174 (__ADCx__) \
2175 )
2176
2177/**
2178 * @brief Helper macro to select the ADC common instance
2179 * to which is belonging the selected ADC instance.
2180 * @note ADC common register instance can be used for:
2181 * - Set parameters common to several ADC instances
2182 * - Multimode (for devices with several ADC instances)
2183 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2184 * @param __ADCx__ ADC instance
2185 * @retval ADC common register instance
2186 */
2187#if defined(ADC3_COMMON)
2188#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2189 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2190 ? ( \
2191 (ADC12_COMMON) \
2192 ) \
2193 : \
2194 ( \
2195 (ADC3_COMMON) \
2196 ) \
2197 )
2198#else
2199#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2200#endif
2201
2202/**
2203 * @brief Helper macro to check if all ADC instances sharing the same
2204 * ADC common instance are disabled.
2205 * @note This check is required by functions with setting conditioned to
2206 * ADC state:
2207 * All ADC instances of the ADC common group must be disabled.
2208 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2209 * @note On devices with only 1 ADC common instance, parameter of this macro
2210 * is useless and can be ignored (parameter kept for compatibility
2211 * with devices featuring several ADC common instances).
2212 * @param __ADCXY_COMMON__ ADC common instance
2213 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2214 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2215 * are disabled.
2216 * Value "1" if at least one ADC instance sharing the same ADC common instance
2217 * is enabled.
2218 */
2219#if defined(ADC3_COMMON)
2220#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2221 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2222 ? ( \
2223 (LL_ADC_IsEnabled(ADC1) | \
2224 LL_ADC_IsEnabled(ADC2) ) \
2225 ) \
2226 : \
2227 ( \
2228 (LL_ADC_IsEnabled(ADC3)) \
2229 ) \
2230 )
2231#else
2232#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2233 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2234#endif
2235
2236/**
2237 * @brief Helper macro to define the ADC conversion data full-scale digital
2238 * value corresponding to the selected ADC resolution.
2239 * @note ADC conversion data full-scale corresponds to voltage range
2240 * determined by analog voltage references Vref+ and Vref-
2241 * (refer to reference manual).
2242 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2243 * @arg @ref LL_ADC_RESOLUTION_16B
2244 * @arg @ref LL_ADC_RESOLUTION_14B
2245 * @arg @ref LL_ADC_RESOLUTION_12B
2246 * @arg @ref LL_ADC_RESOLUTION_10B
2247 * @arg @ref LL_ADC_RESOLUTION_8B
2248 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2249 */
2250#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2251 (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2252
2253#if defined(ADC_VER_V5_V90)
2254/**
2255 * @brief Helper macro to define the ADC conversion data full-scale digital
2256 * value corresponding to the selected ADC resolution.
2257 * @note ADC conversion data full-scale corresponds to voltage range
2258 * determined by analog voltage references Vref+ and Vref-
2259 * (refer to reference manual).
2260 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2261 * @arg @ref LL_ADC_RESOLUTION_12B
2262 * @arg @ref LL_ADC_RESOLUTION_10B
2263 * @arg @ref LL_ADC_RESOLUTION_8B
2264 * @arg @ref LL_ADC_RESOLUTION_6B
2265 * @retval ADC conversion data equivalent voltage value (unit: digital value of ADC conversion bitfield)
2266 */
2267#define __LL_ADC3_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2268 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)))
2269#endif /* ADC_VER_V5_V90 */
2270/**
2271 * @brief Helper macro to convert the ADC conversion data from
2272 * a resolution to another resolution.
2273 * @param __DATA__ ADC conversion data to be converted
2274 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2275 * This parameter can be one of the following values:
2276 * @arg @ref LL_ADC_RESOLUTION_16B
2277 * @arg @ref LL_ADC_RESOLUTION_14B
2278 * @arg @ref LL_ADC_RESOLUTION_12B
2279 * @arg @ref LL_ADC_RESOLUTION_10B
2280 * @arg @ref LL_ADC_RESOLUTION_8B
2281 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2282 * This parameter can be one of the following values:
2283 * @arg @ref LL_ADC_RESOLUTION_16B
2284 * @arg @ref LL_ADC_RESOLUTION_14B
2285 * @arg @ref LL_ADC_RESOLUTION_12B
2286 * @arg @ref LL_ADC_RESOLUTION_10B
2287 * @arg @ref LL_ADC_RESOLUTION_8B
2288 * @retval ADC conversion data to the requested resolution
2289 */
2290#if defined(ADC_VER_V5_X) || defined(ADC_VER_V5_V90)
2291#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2292 __ADC_RESOLUTION_CURRENT__,\
2293 __ADC_RESOLUTION_TARGET__) \
2294( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2295 ?( \
2296 ((__DATA__) \
2297 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2298 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2299 ) \
2300 : \
2301 ( \
2302 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2303 ? ( \
2304 ((__DATA__) \
2305 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2306 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2307 ) \
2308 :\
2309 (\
2310 ((__DATA__) \
2311 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2312 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2313 ) \
2314 )\
2315 )
2316
2317
2318#else /* defined(ADC_VER_V5_3) */
2319#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2320 __ADC_RESOLUTION_CURRENT__,\
2321 __ADC_RESOLUTION_TARGET__) \
2322( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2323 ?( \
2324 ((__DATA__) \
2325 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2326 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2327 ) \
2328 : \
2329 ( \
2330 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2331 ? ( \
2332 ((__DATA__) \
2333 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2334 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2335 ) \
2336 :\
2337 (\
2338 ((__DATA__) \
2339 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2340 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2341 ) \
2342 )\
2343 )
2344
2345#endif
2346
2347#if defined(ADC_VER_V5_V90)
2348/**
2349* @brief Helper macro to convert the ADC conversion data from
2350* a resolution to another resolution.
2351* @param __DATA__ ADC conversion data to be converted
2352* @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2353* This parameter can be one of the following values:
2354* @arg @ref LL_ADC_RESOLUTION_12B
2355* @arg @ref LL_ADC_RESOLUTION_10B
2356* @arg @ref LL_ADC_RESOLUTION_8B
2357* @arg @ref LL_ADC_RESOLUTION_6B
2358* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2359* This parameter can be one of the following values:
2360* @arg @ref LL_ADC_RESOLUTION_12B
2361* @arg @ref LL_ADC_RESOLUTION_10B
2362* @arg @ref LL_ADC_RESOLUTION_8B
2363* @arg @ref LL_ADC_RESOLUTION_6B
2364* @retval ADC conversion data to the requested resolution
2365*/
2366#define __LL_ADC_CONVERT_DATA_RESOLUTION_ADC3(__DATA__,\
2367 __ADC_RESOLUTION_CURRENT__,\
2368 __ADC_RESOLUTION_TARGET__) \
2369 (((__DATA__) \
2370 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL))) \
2371 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)) \
2372 )
2373#endif /* ADC_VER_V5_V90 */
2374/**
2375 * @brief Helper macro to calculate the voltage (unit: mVolt)
2376 * corresponding to a ADC conversion data (unit: digital value).
2377 * @note Analog reference voltage (Vref+) must be either known from
2378 * user board environment or can be calculated using ADC measurement
2379 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2380 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2381 * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
2382 * (unit: digital value).
2383 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2384 * @arg @ref LL_ADC_RESOLUTION_16B
2385 * @arg @ref LL_ADC_RESOLUTION_14B
2386 * @arg @ref LL_ADC_RESOLUTION_12B
2387 * @arg @ref LL_ADC_RESOLUTION_10B
2388 * @arg @ref LL_ADC_RESOLUTION_8B
2389 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2390 */
2391#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2392 __ADC_DATA__,\
2393 __ADC_RESOLUTION__) \
2394 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2395 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2396 )
2397
2398/**
2399 * @brief Helper macro to calculate analog reference voltage (Vref+)
2400 * (unit: mVolt) from ADC conversion data of internal voltage
2401 * reference VrefInt.
2402 * @note Computation is using VrefInt calibration value
2403 * stored in system memory for each device during production.
2404 * @note This voltage depends on user board environment: voltage level
2405 * connected to pin Vref+.
2406 * On devices with small package, the pin Vref+ is not present
2407 * and internally bonded to pin Vdda.
2408 * @note On this STM32 series, calibration data of internal voltage reference
2409 * VrefInt corresponds to a resolution of 16 bits,
2410 * this is the recommended ADC resolution to convert voltage of
2411 * internal voltage reference VrefInt.
2412 * Otherwise, this macro performs the processing to scale
2413 * ADC conversion data to 16 bits.
2414 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
2415 * of internal voltage reference VrefInt (unit: digital value).
2416 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2417 * @arg @ref LL_ADC_RESOLUTION_16B
2418 * @arg @ref LL_ADC_RESOLUTION_14B
2419 * @arg @ref LL_ADC_RESOLUTION_12B
2420 * @arg @ref LL_ADC_RESOLUTION_10B
2421 * @arg @ref LL_ADC_RESOLUTION_8B
2422 * @retval Analog reference voltage (unit: mV)
2423 */
2424#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2425 __ADC_RESOLUTION__) \
2426 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2427 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2428 (__ADC_RESOLUTION__), \
2429 LL_ADC_RESOLUTION_12B) \
2430 )
2431
2432/**
2433 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2434 * from ADC conversion data of internal temperature sensor.
2435 * @note Computation is using temperature sensor calibration values
2436 * stored in system memory for each device during production.
2437 * @note Calculation formula:
2438 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2439 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2440 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2441 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2442 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2443 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2444 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2445 * TEMP_DEGC_CAL1 (calibrated in factory)
2446 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2447 * TEMP_DEGC_CAL2 (calibrated in factory)
2448 * Caution: Calculation relevancy under reserve that calibration
2449 * parameters are correct (address and data).
2450 * To calculate temperature using temperature sensor
2451 * datasheet typical values (generic values less, therefore
2452 * less accurate than calibrated values),
2453 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2454 * @note As calculation input, the analog reference voltage (Vref+) must be
2455 * defined as it impacts the ADC LSB equivalent voltage.
2456 * @note Analog reference voltage (Vref+) must be either known from
2457 * user board environment or can be calculated using ADC measurement
2458 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2459 * @note On this STM32 series, calibration data of temperature sensor
2460 * corresponds to a resolution of 16 bits,
2461 * this is the recommended ADC resolution to convert voltage of
2462 * temperature sensor.
2463 * Otherwise, this macro performs the processing to scale
2464 * ADC conversion data to 16 bits.
2465 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2466 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2467 * temperature sensor (unit: digital value).
2468 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2469 * sensor voltage has been measured.
2470 * This parameter can be one of the following values:
2471 * @arg @ref LL_ADC_RESOLUTION_16B
2472 * @arg @ref LL_ADC_RESOLUTION_14B
2473 * @arg @ref LL_ADC_RESOLUTION_12B
2474 * @arg @ref LL_ADC_RESOLUTION_10B
2475 * @arg @ref LL_ADC_RESOLUTION_8B
2476 * @retval Temperature (unit: degree Celsius)
2477 */
2478#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2479 __TEMPSENSOR_ADC_DATA__,\
2480 __ADC_RESOLUTION__) \
2481 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2482 (__ADC_RESOLUTION__), \
2483 LL_ADC_RESOLUTION_16B) \
2484 * (__VREFANALOG_VOLTAGE__)) \
2485 / TEMPSENSOR_CAL_VREFANALOG) \
2486 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2487 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2488 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2489 ) + TEMPSENSOR_CAL1_TEMP \
2490 )
2491
2492/**
2493 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2494 * from ADC conversion data of internal temperature sensor.
2495 * @note Computation is using temperature sensor typical values
2496 * (refer to device datasheet).
2497 * @note Calculation formula:
2498 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2499 * / Avg_Slope + CALx_TEMP
2500 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2501 * (unit: digital value)
2502 * Avg_Slope = temperature sensor slope
2503 * (unit: uV/Degree Celsius)
2504 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2505 * temperature CALx_TEMP (unit: mV)
2506 * Caution: Calculation relevancy under reserve the temperature sensor
2507 * of the current device has characteristics in line with
2508 * datasheet typical values.
2509 * If temperature sensor calibration values are available on
2510 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2511 * temperature calculation will be more accurate using
2512 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2513 * @note As calculation input, the analog reference voltage (Vref+) must be
2514 * defined as it impacts the ADC LSB equivalent voltage.
2515 * @note Analog reference voltage (Vref+) must be either known from
2516 * user board environment or can be calculated using ADC measurement
2517 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2518 * @note ADC measurement data must correspond to a resolution of 16 bits
2519 * (full scale digital value 4095). If not the case, the data must be
2520 * preliminarily rescaled to an equivalent resolution of 16 bits.
2521 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2522 * On STM32H7, refer to device datasheet parameter "Avg_Slope".
2523 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2524 * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2525 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2526 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2527 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2528 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2529 * This parameter can be one of the following values:
2530 * @arg @ref LL_ADC_RESOLUTION_16B
2531 * @arg @ref LL_ADC_RESOLUTION_14B
2532 * @arg @ref LL_ADC_RESOLUTION_12B
2533 * @arg @ref LL_ADC_RESOLUTION_10B
2534 * @arg @ref LL_ADC_RESOLUTION_8B
2535 * @retval Temperature (unit: degree Celsius)
2536 */
2537#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2538 __TEMPSENSOR_TYP_CALX_V__,\
2539 __TEMPSENSOR_CALX_TEMP__,\
2540 __VREFANALOG_VOLTAGE__,\
2541 __TEMPSENSOR_ADC_DATA__,\
2542 __ADC_RESOLUTION__) \
2543 ((( ( \
2544 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2545 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2546 * 1000UL) \
2547 - \
2548 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2549 * 1000UL) \
2550 ) \
2551 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2552 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2553 )
2554
2555/**
2556 * @}
2557 */
2558
2559/**
2560 * @}
2561 */
2562
2563
2564/* Exported functions --------------------------------------------------------*/
2565/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2566 * @{
2567 */
2568
2569/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2570 * @{
2571 */
2572
2573/**
2574 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2575 * ADC register address from ADC instance and a list of ADC registers
2576 * intended to be used (most commonly) with DMA transfer.
2577 * @note These ADC registers are data registers:
2578 * when ADC conversion data is available in ADC data registers,
2579 * ADC generates a DMA transfer request.
2580 * @note This macro is intended to be used with LL DMA driver, refer to
2581 * function "LL_DMA_ConfigAddresses()".
2582 * Example:
2583 * LL_DMA_ConfigAddresses(DMA1,
2584 * LL_DMA_CHANNEL_1,
2585 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2586 * (uint32_t)&< array or variable >,
2587 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2588 * @note For devices with several ADC: in multimode, some devices
2589 * use a different data register outside of ADC instance scope
2590 * (common data register). This macro manages this register difference,
2591 * only ADC instance has to be set as parameter.
2592 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2593 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2594 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2595 * @param ADCx ADC instance
2596 * @param Register This parameter can be one of the following values:
2597 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2598 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2599 *
2600 * (1) Available on devices with several ADC instances.
2601 * @retval ADC register address
2602 */
2603__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2604{
2605 uint32_t data_reg_addr;
2606
2607 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2608 {
2609 /* Retrieve address of register DR */
2610 data_reg_addr = (uint32_t) & (ADCx->DR);
2611 }
2612 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2613 {
2614 /* Retrieve address of register CDR */
2615 data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2616 }
2617
2618 return data_reg_addr;
2619}
2620
2621/**
2622 * @}
2623 */
2624
2625/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2626 * @{
2627 */
2628
2629/**
2630 * @brief Set parameter common to several ADC: Clock source and prescaler.
2631 * @note On this STM32 series, if ADC group injected is used, some
2632 * clock ratio constraints between ADC clock and AHB clock
2633 * must be respected.
2634 * Refer to reference manual.
2635 * @note On this STM32 series, setting of this feature is conditioned to
2636 * ADC state:
2637 * All ADC instances of the ADC common group must be disabled.
2638 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2639 * ADC instance or by using helper macro helper macro
2640 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2641 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2642 * CCR PRESC LL_ADC_SetCommonClock
2643 * @param ADCxy_COMMON ADC common instance
2644 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2645 * @param CommonClock This parameter can be one of the following values:
2646 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2647 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2648 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2649 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2650 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2651 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2652 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2653 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2654 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2655 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2656 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2657 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2658 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2659 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2660 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2661 * @retval None
2662 */
2663__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2664{
2665 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2666}
2667
2668/**
2669 * @brief Get parameter common to several ADC: Clock source and prescaler.
2670 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2671 * CCR PRESC LL_ADC_GetCommonClock
2672 * @param ADCxy_COMMON ADC common instance
2673 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2674 * @retval Returned value can be one of the following values:
2675 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2676 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2677 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2678 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2679 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2680 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2681 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2682 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2683 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2684 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2685 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2686 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2687 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2688 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2689 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2690 */
2691__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
2692{
2693 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2694}
2695
2696/**
2697 * @brief Set parameter common to several ADC: measurement path to internal
2698 * channels (VrefInt, temperature sensor, ...).
2699 * @note One or several values can be selected.
2700 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2701 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2702 * @note Stabilization time of measurement path to internal channel:
2703 * After enabling internal paths, before starting ADC conversion,
2704 * a delay is required for internal voltage reference and
2705 * temperature sensor stabilization time.
2706 * Refer to device datasheet.
2707 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2708 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2709 * @note ADC internal channel sampling time constraint:
2710 * For ADC conversion of internal channels,
2711 * a sampling time minimum value is required.
2712 * Refer to device datasheet.
2713 * @note On this STM32 series, setting of this feature is conditioned to
2714 * ADC state:
2715 * All ADC instances of the ADC common group must be disabled.
2716 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2717 * ADC instance or by using helper macro helper macro
2718 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2719 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2720 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2721 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2722 * @param ADCxy_COMMON ADC common instance
2723 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2724 * @param PathInternal This parameter can be a combination of the following values:
2725 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2726 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2727 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2728 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2729 * @retval None
2730 */
2731__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2732{
2733 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2734}
2735
2736/**
2737 * @brief Get parameter common to several ADC: measurement path to internal
2738 * channels (VrefInt, temperature sensor, ...).
2739 * @note One or several values can be selected.
2740 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2741 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2742 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2743 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2744 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2745 * @param ADCxy_COMMON ADC common instance
2746 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2747 * @retval Returned value can be a combination of the following values:
2748 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2749 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2750 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2751 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2752 */
2753__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2754{
2755 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2756}
2757
2758/**
2759 * @brief Set parameter common to several ADC: measurement path to
2760 * internal channels (VrefInt, temperature sensor, ...).
2761 * Add paths to the current configuration.
2762 * @note One or several values can be selected.
2763 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2764 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2765 * @note Stabilization time of measurement path to internal channel:
2766 * After enabling internal paths, before starting ADC conversion,
2767 * a delay is required for internal voltage reference and
2768 * temperature sensor stabilization time.
2769 * Refer to device datasheet.
2770 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2771 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2772 * @note ADC internal channel sampling time constraint:
2773 * For ADC conversion of internal channels,
2774 * a sampling time minimum value is required.
2775 * Refer to device datasheet.
2776 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2777 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2778 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2779 * @param ADCxy_COMMON ADC common instance
2780 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2781 * @param PathInternal This parameter can be a combination of the following values:
2782 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2783 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2784 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2785 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2786 * @retval None
2787 */
2788__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2789{
2790 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2791}
2792
2793/**
2794 * @brief Set parameter common to several ADC: measurement path to
2795 * internal channels (VrefInt, temperature sensor, ...).
2796 * Remove paths to the current configuration.
2797 * @note One or several values can be selected.
2798 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2799 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2800 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2801 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2802 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2803 * @param ADCxy_COMMON ADC common instance
2804 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2805 * @param PathInternal This parameter can be a combination of the following values:
2806 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2807 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2808 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2809 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2810 * @retval None
2811 */
2812__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2813{
2814 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2815}
2816
2817/**
2818 * @}
2819 */
2820
2821/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2822 * @{
2823 */
2824
2825/**
2826 * @brief Set ADC calibration factor in the mode single-ended
2827 * or differential (for devices with differential mode available).
2828 * @note This function is intended to set calibration parameters
2829 * without having to perform a new calibration using
2830 * @ref LL_ADC_StartCalibration().
2831 * @note For devices with differential mode available:
2832 * Calibration of offset is specific to each of
2833 * single-ended and differential modes
2834 * (calibration factor must be specified for each of these
2835 * differential modes, if used afterwards and if the application
2836 * requires their calibration).
2837 * Calibration of linearity is common to both
2838 * single-ended and differential modes
2839 * (calibration factor can be specified only once).
2840 * @note In case of setting calibration factors of both modes single ended
2841 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2842 * both calibration factors must be concatenated.
2843 * To perform this processing, use helper macro
2844 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2845 * @note On this STM32 series, setting of this feature is conditioned to
2846 * ADC state:
2847 * ADC must be enabled, without calibration on going, without conversion
2848 * on going on group regular.
2849 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor\n
2850 * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
2851 * @param ADCx ADC instance
2852 * @param SingleDiff This parameter can be one of the following values:
2853 * @arg @ref LL_ADC_SINGLE_ENDED
2854 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2855 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2856 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2857 * @retval None
2858 */
2859__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2860{
2861#if defined(ADC_VER_V5_V90)
2862 MODIFY_REG(ADCx->CALFACT_RES13,
2863 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2864 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2865#else
2866 MODIFY_REG(ADCx->CALFACT,
2867 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2868 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2869#endif /* ADC_VER_V5_V90 */
2870}
2871
2872/**
2873 * @brief Get ADC calibration factor in the mode single-ended
2874 * or differential (for devices with differential mode available).
2875 * @note Calibration factors are set by hardware after performing
2876 * a calibration run using function @ref LL_ADC_StartCalibration().
2877 * @note For devices with differential mode available:
2878 * Calibration of offset is specific to each of
2879 * single-ended and differential modes
2880 * Calibration of linearity is common to both
2881 * single-ended and differential modes
2882 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor\n
2883 * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
2884 * @param ADCx ADC instance
2885 * @param SingleDiff This parameter can be one of the following values:
2886 * @arg @ref LL_ADC_SINGLE_ENDED
2887 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2888 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2889 */
2890__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
2891{
2892 /* Retrieve bits with position in register depending on parameter */
2893 /* "SingleDiff". */
2894 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2895 /* containing other bits reserved for other purpose. */
2896#if defined(ADC_VER_V5_V90)
2897 return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2898#else
2899 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2900#endif /* ADC_VER_V5_V90 */
2901}
2902
2903/**
2904 * @brief Set ADC Linear calibration factor in the mode single-ended.
2905 * @note This function is intended to set linear calibration parameters
2906 * without having to perform a new calibration using
2907 * @ref LL_ADC_StartCalibration().
2908 * @note On this STM32 series, setting of this feature is conditioned to
2909 * ADC state:
2910 * ADC must be enabled, without calibration on going, without conversion
2911 * on going on group regular.
2912 * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n
2913 * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
2914 * @param ADCx ADC instance
2915 * @param LinearityWord This parameter can be one of the following values:
2916 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
2917 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
2918 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
2919 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
2920 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
2921 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
2922 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
2923 * @retval None
2924 */
2925__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
2926{
2927#if defined(ADC_VER_V5_V90)
2928 if (ADCx != ADC3)
2929 {
2930 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2931 MODIFY_REG(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2932 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2933 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
2934 {
2935 timeout_cpu_cycles--;
2936 }
2937 }
2938#else
2939 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2940 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2941 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2942 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
2943 {
2944 timeout_cpu_cycles--;
2945 }
2946#endif /* ADC_VER_V5_V90 */
2947}
2948
2949/**
2950 * @brief Get ADC Linear calibration factor in the mode single-ended.
2951 * @note Calibration factors are set by hardware after performing
2952 * a calibration run using function @ref LL_ADC_StartCalibration().
2953 * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n
2954 * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
2955 * @param ADCx ADC instance
2956 * @param LinearityWord This parameter can be one of the following values:
2957 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
2958 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
2959 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
2960 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
2961 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
2962 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
2963 * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
2964 */
2965__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
2966{
2967 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2968 CLEAR_BIT(ADCx->CR, LinearityWord);
2969 while ((READ_BIT(ADCx->CR, LinearityWord) != 0UL) && (timeout_cpu_cycles > 0UL))
2970 {
2971 timeout_cpu_cycles--;
2972 }
2973#if defined(ADC_VER_V5_V90)
2974 return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT));
2975#else
2976 return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
2977#endif /* ADC_VER_V5_V90 */
2978}
2979/**
2980 * @brief Set ADC resolution.
2981 * Refer to reference manual for alignments formats
2982 * dependencies to ADC resolutions.
2983 * @note On this STM32 series, setting of this feature is conditioned to
2984 * ADC state:
2985 * ADC must be disabled or enabled without conversion on going
2986 * on either groups regular or injected.
2987 * @rmtoll CFGR RES LL_ADC_SetResolution
2988 * @param ADCx ADC instance
2989 * @param Resolution This parameter can be one of the following values:
2990 * @arg @ref LL_ADC_RESOLUTION_16B
2991 * @arg @ref LL_ADC_RESOLUTION_14B
2992 * @arg @ref LL_ADC_RESOLUTION_12B
2993 * @arg @ref LL_ADC_RESOLUTION_10B
2994 * @arg @ref LL_ADC_RESOLUTION_8B
2995 * @retval None
2996 */
2997__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2998{
2999#if defined(ADC_VER_V5_3)
3000
3001 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3002
3003#elif defined(ADC_VER_V5_V90)
3004 if (ADCx == ADC3)
3005 {
3006 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, ((__LL_ADC12_RESOLUTION_TO_ADC3(Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL));
3007 }
3008 else
3009 {
3010 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3011 {
3012 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3013 }
3014 else /* Rev.V */
3015 {
3016 if (LL_ADC_RESOLUTION_8B == Resolution)
3017 {
3018 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
3019 }
3020 else
3021 {
3022 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3023 }
3024 }
3025 }
3026#else /* ADC_VER_V5_V90 */
3027 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3028 {
3029 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3030 }
3031 else /* Rev.V */
3032 {
3033 if (LL_ADC_RESOLUTION_8B == Resolution)
3034 {
3035 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
3036 }
3037 else
3038 {
3039 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3040 }
3041 }
3042
3043#endif /* ADC_VER_V5_X*/
3044}
3045
3046/**
3047 * @brief Get ADC resolution.
3048 * Refer to reference manual for alignments formats
3049 * dependencies to ADC resolutions.
3050 * @rmtoll CFGR RES LL_ADC_GetResolution
3051 * @param ADCx ADC instance
3052 * @retval Returned value can be one of the following values:
3053 * @arg @ref LL_ADC_RESOLUTION_16B (1)
3054 * @arg @ref LL_ADC_RESOLUTION_14B
3055 * @arg @ref LL_ADC_RESOLUTION_12B
3056 * @arg @ref LL_ADC_RESOLUTION_10B
3057 * @arg @ref LL_ADC_RESOLUTION_8B
3058 * @arg @ref LL_ADC_RESOLUTION_6B (2)
3059 * (1): Specific to ADC instance: ADC1, ADC2
3060 * (2): Specific to ADC instance: ADC3
3061 */
3062__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3063{
3064#if defined (ADC_VER_V5_3)
3065
3066 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3067
3068#elif defined(ADC_VER_V5_V90)
3069 if (ADCx == ADC3)
3070 {
3071 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_RES));
3072 }
3073 else
3074 {
3075 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3076 {
3077 return (LL_ADC_RESOLUTION_8B);
3078 }
3079 else
3080 {
3081 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3082 }
3083 }
3084
3085#else /* ADC_VER_V5_V90 */
3086 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3087 {
3088 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3089 }
3090 else /* Rev.V */
3091 {
3092 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3093 {
3094 return (LL_ADC_RESOLUTION_8B);
3095 }
3096 else
3097 {
3098 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3099 }
3100 }
3101
3102#endif /* ADC_VER_V5_X */
3103}
3104
3105/**
3106 * @brief Set ADC low power mode.
3107 * @note Description of ADC low power modes:
3108 * - ADC low power mode "auto wait": Dynamic low power mode,
3109 * ADC conversions occurrences are limited to the minimum necessary
3110 * in order to reduce power consumption.
3111 * New ADC conversion starts only when the previous
3112 * unitary conversion data (for ADC group regular)
3113 * or previous sequence conversions data (for ADC group injected)
3114 * has been retrieved by user software.
3115 * In the meantime, ADC remains idle: does not performs any
3116 * other conversion.
3117 * This mode allows to automatically adapt the ADC conversions
3118 * triggers to the speed of the software that reads the data.
3119 * Moreover, this avoids risk of overrun for low frequency
3120 * applications.
3121 * How to use this low power mode:
3122 * - It is not recommended to use with interruption or DMA
3123 * since these modes have to clear immediately the EOC flag
3124 * (by CPU to free the IRQ pending event or by DMA).
3125 * Auto wait will work but fort a very short time, discarding
3126 * its intended benefit (except specific case of high load of CPU
3127 * or DMA transfers which can justify usage of auto wait).
3128 * - Do use with polling: 1. Start conversion,
3129 * 2. Later on, when conversion data is needed: poll for end of
3130 * conversion to ensure that conversion is completed and
3131 * retrieve ADC conversion data. This will trig another
3132 * ADC conversion start.
3133 * - ADC low power mode "auto power-off" (feature available on
3134 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3135 * the ADC automatically powers-off after a conversion and
3136 * automatically wakes up when a new conversion is triggered
3137 * (with startup time between trigger and start of sampling).
3138 * This feature can be combined with low power mode "auto wait".
3139 * @note With ADC low power mode "auto wait", the ADC conversion data read
3140 * is corresponding to previous ADC conversion start, independently
3141 * of delay during which ADC was idle.
3142 * Therefore, the ADC conversion data may be outdated: does not
3143 * correspond to the current voltage level on the selected
3144 * ADC channel.
3145 * @note On this STM32 series, setting of this feature is conditioned to
3146 * ADC state:
3147 * ADC must be disabled or enabled without conversion on going
3148 * on either groups regular or injected.
3149 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3150 * @param ADCx ADC instance
3151 * @param LowPowerMode This parameter can be one of the following values:
3152 * @arg @ref LL_ADC_LP_MODE_NONE
3153 * @arg @ref LL_ADC_LP_AUTOWAIT
3154 * @retval None
3155 */
3156__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3157{
3158 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3159}
3160
3161/**
3162 * @brief Get ADC low power mode:
3163 * @note Description of ADC low power modes:
3164 * - ADC low power mode "auto wait": Dynamic low power mode,
3165 * ADC conversions occurrences are limited to the minimum necessary
3166 * in order to reduce power consumption.
3167 * New ADC conversion starts only when the previous
3168 * unitary conversion data (for ADC group regular)
3169 * or previous sequence conversions data (for ADC group injected)
3170 * has been retrieved by user software.
3171 * In the meantime, ADC remains idle: does not performs any
3172 * other conversion.
3173 * This mode allows to automatically adapt the ADC conversions
3174 * triggers to the speed of the software that reads the data.
3175 * Moreover, this avoids risk of overrun for low frequency
3176 * applications.
3177 * How to use this low power mode:
3178 * - It is not recommended to use with interruption or DMA
3179 * since these modes have to clear immediately the EOC flag
3180 * (by CPU to free the IRQ pending event or by DMA).
3181 * Auto wait will work but fort a very short time, discarding
3182 * its intended benefit (except specific case of high load of CPU
3183 * or DMA transfers which can justify usage of auto wait).
3184 * - Do use with polling: 1. Start conversion,
3185 * 2. Later on, when conversion data is needed: poll for end of
3186 * conversion to ensure that conversion is completed and
3187 * retrieve ADC conversion data. This will trig another
3188 * ADC conversion start.
3189 * - ADC low power mode "auto power-off" (feature available on
3190 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3191 * the ADC automatically powers-off after a conversion and
3192 * automatically wakes up when a new conversion is triggered
3193 * (with startup time between trigger and start of sampling).
3194 * This feature can be combined with low power mode "auto wait".
3195 * @note With ADC low power mode "auto wait", the ADC conversion data read
3196 * is corresponding to previous ADC conversion start, independently
3197 * of delay during which ADC was idle.
3198 * Therefore, the ADC conversion data may be outdated: does not
3199 * correspond to the current voltage level on the selected
3200 * ADC channel.
3201 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3202 * @param ADCx ADC instance
3203 * @retval Returned value can be one of the following values:
3204 * @arg @ref LL_ADC_LP_MODE_NONE
3205 * @arg @ref LL_ADC_LP_AUTOWAIT
3206 */
3207__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3208{
3209 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3210}
3211
3212/**
3213 * @brief Set ADC selected Channel.
3214 * @note This function set the pre-selection of channel configuration.
3215 * @note Caution: Channel selections is dependent to ADC instance and IP version:
3216 * For STM32H72x/3x This is applicable only for ADC1/ADC2
3217 * For Rest of STM32H7xxx This is applicable only all the ADCs instances.
3218 *
3219 * @param ADCx ADC instance
3220 * @param Channel This parameter can be one of the following values:
3221 * @arg @ref LL_ADC_CHANNEL_0
3222 * @arg @ref LL_ADC_CHANNEL_1
3223 * @arg @ref LL_ADC_CHANNEL_2
3224 * @arg @ref LL_ADC_CHANNEL_3
3225 * @arg @ref LL_ADC_CHANNEL_4
3226 * @arg @ref LL_ADC_CHANNEL_5
3227 * @arg @ref LL_ADC_CHANNEL_6
3228 * @arg @ref LL_ADC_CHANNEL_7
3229 * @arg @ref LL_ADC_CHANNEL_8
3230 * @arg @ref LL_ADC_CHANNEL_9
3231 * @arg @ref LL_ADC_CHANNEL_10
3232 * @arg @ref LL_ADC_CHANNEL_11
3233 * @arg @ref LL_ADC_CHANNEL_12
3234 * @arg @ref LL_ADC_CHANNEL_13
3235 * @arg @ref LL_ADC_CHANNEL_14
3236 * @arg @ref LL_ADC_CHANNEL_15
3237 * @arg @ref LL_ADC_CHANNEL_16
3238 * @arg @ref LL_ADC_CHANNEL_17
3239 * @arg @ref LL_ADC_CHANNEL_18
3240 * @arg @ref LL_ADC_CHANNEL_19
3241 * @retval None
3242 */
3243__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
3244{
3245#if defined(ADC_VER_V5_V90)
3246 if (ADCx != ADC3)
3247 {
3248 /* ADC channels preselection */
3249 ADCx->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3250 }
3251#else
3252 /* ADC channels preselection */
3253 ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3254#endif /* ADC_VER_V5_V90 */
3255}
3256
3257/**
3258 * @brief Gets ADC pre-selected Channel.
3259 * @note This function gets the pre-selected ADC channel.
3260 * @note Caution: Channel selections is dependent to ADC instance and IP version:
3261 * For STM32H72x/3x This is applicable only for ADC1/ADC2
3262 * For Rest of STM32H7xxx This is applicable on all the ADCs instances.
3263 *
3264 * @param ADCx ADC instance
3265 * @param Channel This parameter can be one of the following values:
3266 * @arg @ref LL_ADC_CHANNEL_0
3267 * @arg @ref LL_ADC_CHANNEL_1
3268 * @arg @ref LL_ADC_CHANNEL_2
3269 * @arg @ref LL_ADC_CHANNEL_3
3270 * @arg @ref LL_ADC_CHANNEL_4
3271 * @arg @ref LL_ADC_CHANNEL_5
3272 * @arg @ref LL_ADC_CHANNEL_6
3273 * @arg @ref LL_ADC_CHANNEL_7
3274 * @arg @ref LL_ADC_CHANNEL_8
3275 * @arg @ref LL_ADC_CHANNEL_9
3276 * @arg @ref LL_ADC_CHANNEL_10
3277 * @arg @ref LL_ADC_CHANNEL_11
3278 * @arg @ref LL_ADC_CHANNEL_12
3279 * @arg @ref LL_ADC_CHANNEL_13
3280 * @arg @ref LL_ADC_CHANNEL_14
3281 * @arg @ref LL_ADC_CHANNEL_15
3282 * @arg @ref LL_ADC_CHANNEL_16
3283 * @arg @ref LL_ADC_CHANNEL_17
3284 * @arg @ref LL_ADC_CHANNEL_18
3285 * @arg @ref LL_ADC_CHANNEL_19
3286 * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected)
3287 */
3288__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx, uint32_t Channel)
3289{
3290#if defined(ADC_VER_V5_V90)
3291 if (ADCx != ADC3)
3292 {
3293 /* Gets preselected ADC channel */
3294 return (uint32_t)(READ_BIT(ADCx->PCSEL_RES0, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
3295 }
3296 else
3297 {
3298 return 0UL;
3299 }
3300#else
3301 /* Gets preselected ADC channel */
3302 return (uint32_t)(READ_BIT(ADCx->PCSEL, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
3303#endif /* ADC_VER_V5_V90 */
3304}
3305
3306/**
3307 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3308 * @note This function set the 2 items of offset configuration:
3309 * - ADC channel to which the offset programmed will be applied
3310 * (independently of channel mapped on ADC group regular
3311 * or group injected)
3312 * - Offset level (offset to be subtracted from the raw
3313 * converted data).
3314 * @note Caution: Offset format is dependent to ADC resolution:
3315 * offset has to be left-aligned on bit 15 (handling maximum ADC resolution 16 bit),
3316 * the LSB (right bits) are set to 0.
3317 * @note This function enables the offset, by default. It can be forced
3318 * to disable state using function LL_ADC_SetOffsetState().
3319 * @note If a channel is mapped on several offsets numbers, only the offset
3320 * with the lowest value is considered for the subtraction.
3321 * @note On this STM32 series, setting of this feature is conditioned to
3322 * ADC state:
3323 * ADC must be disabled or enabled without conversion on going
3324 * on either groups regular or injected.
3325 * @note On STM32H7, some fast channels are available: fast analog inputs
3326 * coming from GPIO pads (ADC_IN0..5).
3327 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3328 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3329 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3330 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3331 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3332 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3333 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3334 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3335 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3336 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3337 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3338 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3339 * @param ADCx ADC instance
3340 * @param Offsety This parameter can be one of the following values:
3341 * @arg @ref LL_ADC_OFFSET_1
3342 * @arg @ref LL_ADC_OFFSET_2
3343 * @arg @ref LL_ADC_OFFSET_3
3344 * @arg @ref LL_ADC_OFFSET_4
3345 * @param Channel This parameter can be one of the following values:
3346 * @arg @ref LL_ADC_CHANNEL_0 (3)
3347 * @arg @ref LL_ADC_CHANNEL_1 (3)
3348 * @arg @ref LL_ADC_CHANNEL_2 (3)
3349 * @arg @ref LL_ADC_CHANNEL_3 (3)
3350 * @arg @ref LL_ADC_CHANNEL_4 (3)
3351 * @arg @ref LL_ADC_CHANNEL_5 (3)
3352 * @arg @ref LL_ADC_CHANNEL_6
3353 * @arg @ref LL_ADC_CHANNEL_7
3354 * @arg @ref LL_ADC_CHANNEL_8
3355 * @arg @ref LL_ADC_CHANNEL_9
3356 * @arg @ref LL_ADC_CHANNEL_10
3357 * @arg @ref LL_ADC_CHANNEL_11
3358 * @arg @ref LL_ADC_CHANNEL_12
3359 * @arg @ref LL_ADC_CHANNEL_13
3360 * @arg @ref LL_ADC_CHANNEL_14
3361 * @arg @ref LL_ADC_CHANNEL_15
3362 * @arg @ref LL_ADC_CHANNEL_16
3363 * @arg @ref LL_ADC_CHANNEL_17
3364 * @arg @ref LL_ADC_CHANNEL_18
3365 * @arg @ref LL_ADC_CHANNEL_19
3366 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3367 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3368 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3369 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
3370 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
3371 *
3372 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
3373 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
3374 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3375 * Other channels are slow channels (conversion rate: refer to reference manual).
3376 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
3377 * @retval None
3378 */
3379__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3380{
3381 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3382#if defined(ADC_VER_V5_V90)
3383 if (ADCx == ADC3)
3384 {
3385 MODIFY_REG(*preg,
3386 ADC3_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | (ADC_OFR1_OFFSET1 & 0xFFFUL),
3387 ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3388 }
3389 else
3390#endif /* ADC_VER_V5_V90 */
3391 {
3392 MODIFY_REG(*preg,
3393 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3394 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3395 }
3396}
3397
3398/**
3399 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3400 * Channel to which the offset programmed will be applied
3401 * (independently of channel mapped on ADC group regular
3402 * or group injected)
3403 * @note Usage of the returned channel number:
3404 * - To reinject this channel into another function LL_ADC_xxx:
3405 * the returned channel number is only partly formatted on definition
3406 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3407 * with parts of literals LL_ADC_CHANNEL_x or using
3408 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3409 * Then the selected literal LL_ADC_CHANNEL_x can be used
3410 * as parameter for another function.
3411 * - To get the channel number in decimal format:
3412 * process the returned value with the helper macro
3413 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3414 * @note On STM32H7, some fast channels are available: fast analog inputs
3415 * coming from GPIO pads (ADC_IN0..5).
3416 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3417 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3418 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3419 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3420 * @param ADCx ADC instance
3421 * @param Offsety This parameter can be one of the following values:
3422 * @arg @ref LL_ADC_OFFSET_1
3423 * @arg @ref LL_ADC_OFFSET_2
3424 * @arg @ref LL_ADC_OFFSET_3
3425 * @arg @ref LL_ADC_OFFSET_4
3426 * @retval Returned value can be one of the following values:
3427 * @arg @ref LL_ADC_CHANNEL_0 (3)
3428 * @arg @ref LL_ADC_CHANNEL_1 (3)
3429 * @arg @ref LL_ADC_CHANNEL_2 (3)
3430 * @arg @ref LL_ADC_CHANNEL_3 (3)
3431 * @arg @ref LL_ADC_CHANNEL_4 (3)
3432 * @arg @ref LL_ADC_CHANNEL_5 (3)
3433 * @arg @ref LL_ADC_CHANNEL_6
3434 * @arg @ref LL_ADC_CHANNEL_7
3435 * @arg @ref LL_ADC_CHANNEL_8
3436 * @arg @ref LL_ADC_CHANNEL_9
3437 * @arg @ref LL_ADC_CHANNEL_10
3438 * @arg @ref LL_ADC_CHANNEL_11
3439 * @arg @ref LL_ADC_CHANNEL_12
3440 * @arg @ref LL_ADC_CHANNEL_13
3441 * @arg @ref LL_ADC_CHANNEL_14
3442 * @arg @ref LL_ADC_CHANNEL_15
3443 * @arg @ref LL_ADC_CHANNEL_16
3444 * @arg @ref LL_ADC_CHANNEL_17
3445 * @arg @ref LL_ADC_CHANNEL_18
3446 * @arg @ref LL_ADC_CHANNEL_19
3447 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3448 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3449 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3450 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
3451 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
3452 *
3453 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
3454 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
3455 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3456 * Other channels are slow channels (conversion rate: refer to reference manual).\n
3457 * (1, 2) For ADC channel read back from ADC register,
3458 * comparison with internal channel parameter to be done
3459 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3460 */
3461__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3462{
3463 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3464
3465 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3466}
3467
3468/**
3469 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3470 * Offset level (offset to be subtracted from the raw
3471 * converted data).
3472 * @note Caution: Offset format is dependent to ADC resolution:
3473 * offset has to be left-aligned on bit 15 (handling maximum ADC resolution 16 bit),
3474 * the LSB (right bits) are set to 0.
3475 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3476 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3477 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3478 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3479 * @param ADCx ADC instance
3480 * @param Offsety This parameter can be one of the following values:
3481 * @arg @ref LL_ADC_OFFSET_1
3482 * @arg @ref LL_ADC_OFFSET_2
3483 * @arg @ref LL_ADC_OFFSET_3
3484 * @arg @ref LL_ADC_OFFSET_4
3485 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
3486 */
3487__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3488{
3489 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3490
3491 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3492}
3493
3494
3495/**
3496 * @brief Set data right shift for the ADC selected offset number 1, 2, 3 or 4:
3497 * signed offset saturation if enabled or disabled.
3498 * @rmtoll CFGR2 RSHIFT LL_ADC_SetDataRightShift\n
3499 * @param ADCx ADC instance
3500 * @param Offsety This parameter can be one of the following values:
3501 * @arg @ref LL_ADC_OFFSET_1
3502 * @arg @ref LL_ADC_OFFSET_2
3503 * @arg @ref LL_ADC_OFFSET_3
3504 * @arg @ref LL_ADC_OFFSET_4
3505 * @param RigthShift This parameter can be one of the following values:
3506 * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
3507 * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
3508 * @retval Returned None
3509 */
3510__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
3511{
3512 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
3513}
3514
3515/**
3516 * @brief Get data right shift for the ADC selected offset number 1, 2, 3 or 4:
3517 * signed offset saturation if enabled or disabled.
3518 * @rmtoll CFGR2 RSHIFT LL_ADC_GetDataRightShift\n
3519 * @param ADCx ADC instance
3520 * @param Offsety This parameter can be one of the following values:
3521 * @arg @ref LL_ADC_OFFSET_1
3522 * @arg @ref LL_ADC_OFFSET_2
3523 * @arg @ref LL_ADC_OFFSET_3
3524 * @arg @ref LL_ADC_OFFSET_4
3525 * @retval Returned value can be one of the following values:
3526 * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
3527 * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
3528 */
3529__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(const ADC_TypeDef *ADCx, uint32_t Offsety)
3530{
3531 return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
3532}
3533
3534/**
3535 * @brief Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3536 * signed offset saturation if enabled or disabled.
3537 * @rmtoll OFR1 SSATE LL_ADC_SetOffsetSignedSaturation\n
3538 * OFR2 SSATE LL_ADC_SetOffsetSignedSaturation\n
3539 * OFR3 SSATE LL_ADC_SetOffsetSignedSaturation\n
3540 * OFR4 SSATE LL_ADC_SetOffsetSignedSaturation
3541 * @param ADCx ADC instance
3542 * @param Offsety This parameter can be one of the following values:
3543 * @arg @ref LL_ADC_OFFSET_1
3544 * @arg @ref LL_ADC_OFFSET_2
3545 * @arg @ref LL_ADC_OFFSET_3
3546 * @arg @ref LL_ADC_OFFSET_4
3547 * @param OffsetSignedSaturation This parameter can be one of the following values:
3548 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3549 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3550 * @retval Returned None
3551 */
3552__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
3553{
3554#if defined(ADC_VER_V5_V90)
3555 if (ADCx == ADC3)
3556 {
3557 /* Function not available on this instance */
3558 }
3559 else
3560#endif /* ADC_VER_V5_V90 */
3561 {
3562 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3563 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
3564 }
3565}
3566
3567/**
3568 * @brief Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3569 * signed offset saturation if enabled or disabled.
3570 * @rmtoll OFR1 SSATE LL_ADC_GetOffsetSignedSaturation\n
3571 * OFR2 SSATE LL_ADC_GetOffsetSignedSaturation\n
3572 * OFR3 SSATE LL_ADC_GetOffsetSignedSaturation\n
3573 * OFR4 SSATE LL_ADC_GetOffsetSignedSaturation
3574 * @param ADCx ADC instance
3575 * @param Offsety This parameter can be one of the following values:
3576 * @arg @ref LL_ADC_OFFSET_1
3577 * @arg @ref LL_ADC_OFFSET_2
3578 * @arg @ref LL_ADC_OFFSET_3
3579 * @arg @ref LL_ADC_OFFSET_4
3580 * @retval Returned value can be one of the following values:
3581 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3582 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3583 */
3584__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3585{
3586#if defined(ADC_VER_V5_V90)
3587 if (ADCx == ADC3)
3588 {
3589 /* Function not available on this instance */
3590 return 0UL;
3591 }
3592 else
3593#endif /* ADC_VER_V5_V90 */
3594 {
3595 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3596 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3597 }
3598}
3599
3600#if defined(ADC_VER_V5_V90)
3601/**
3602 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3603 * choose offset saturation mode.
3604 * @note On this STM32 series, setting of this feature is conditioned to
3605 * ADC state:
3606 * ADC must be disabled or enabled without conversion on going
3607 * on either groups regular or injected.
3608 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
3609 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
3610 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
3611 * OFR4 SATEN LL_ADC_SetOffsetSaturation
3612 * @param ADCx ADC instance
3613 * @param Offsety This parameter can be one of the following values:
3614 * @arg @ref LL_ADC_OFFSET_1
3615 * @arg @ref LL_ADC_OFFSET_2
3616 * @arg @ref LL_ADC_OFFSET_3
3617 * @arg @ref LL_ADC_OFFSET_4
3618 * @param OffsetSaturation This parameter can be one of the following values:
3619 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3620 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3621 * @retval None
3622 */
3623__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3624{
3625 if (ADCx == ADC3)
3626 {
3627 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3628
3629 MODIFY_REG(*preg,
3630 ADC3_OFR1_SATEN,
3631 OffsetSaturation);
3632 }
3633}
3634
3635/**
3636 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3637 * offset saturation if enabled or disabled.
3638 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
3639 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
3640 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
3641 * OFR4 SATEN LL_ADC_GetOffsetSaturation
3642 * @param ADCx ADC instance
3643 * @param Offsety This parameter can be one of the following values:
3644 * @arg @ref LL_ADC_OFFSET_1
3645 * @arg @ref LL_ADC_OFFSET_2
3646 * @arg @ref LL_ADC_OFFSET_3
3647 * @arg @ref LL_ADC_OFFSET_4
3648 * @retval Returned value can be one of the following values:
3649 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3650 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3651 */
3652__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3653{
3654 if (ADCx == ADC3)
3655 {
3656 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3657
3658 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_SATEN);
3659 }else
3660 {
3661 return 0UL;
3662 }
3663}
3664
3665/**
3666 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3667 * choose offset sign.
3668 * @note On this STM32 series, setting of this feature is conditioned to
3669 * ADC state:
3670 * ADC must be disabled or enabled without conversion on going
3671 * on either groups regular or injected.
3672 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3673 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3674 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3675 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3676 * @param ADCx ADC instance
3677 * @param Offsety This parameter can be one of the following values:
3678 * @arg @ref LL_ADC_OFFSET_1
3679 * @arg @ref LL_ADC_OFFSET_2
3680 * @arg @ref LL_ADC_OFFSET_3
3681 * @arg @ref LL_ADC_OFFSET_4
3682 * @param OffsetSign This parameter can be one of the following values:
3683 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3684 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3685 * @retval None
3686 */
3687__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3688{
3689 if (ADCx == ADC3)
3690 {
3691 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3692
3693 MODIFY_REG(*preg,
3694 ADC3_OFR1_OFFSETPOS,
3695 OffsetSign);
3696 }
3697}
3698
3699/**
3700 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3701 * offset sign if positive or negative.
3702 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3703 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3704 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3705 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3706 * @param ADCx ADC instance
3707 * @param Offsety This parameter can be one of the following values:
3708 * @arg @ref LL_ADC_OFFSET_1
3709 * @arg @ref LL_ADC_OFFSET_2
3710 * @arg @ref LL_ADC_OFFSET_3
3711 * @arg @ref LL_ADC_OFFSET_4
3712 * @retval Returned value can be one of the following values:
3713 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3714 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3715 */
3716__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
3717{
3718 if (ADCx == ADC3)
3719 {
3720 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3721
3722 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSETPOS);
3723 }
3724 else
3725 {
3726 return 0UL;
3727 }
3728}
3729
3730/**
3731 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3732 * force offset state disable or enable
3733 * without modifying offset channel or offset value.
3734 * @note This function should be needed only in case of offset to be
3735 * enabled-disabled dynamically, and should not be needed in other cases:
3736 * function LL_ADC_SetOffset() automatically enables the offset.
3737 * @note On this STM32 series, setting of this feature is conditioned to
3738 * ADC state:
3739 * ADC must be disabled or enabled without conversion on going
3740 * on either groups regular or injected.
3741 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3742 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3743 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3744 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3745 * @param ADCx ADC instance
3746 * @param Offsety This parameter can be one of the following values:
3747 * @arg @ref LL_ADC_OFFSET_1
3748 * @arg @ref LL_ADC_OFFSET_2
3749 * @arg @ref LL_ADC_OFFSET_3
3750 * @arg @ref LL_ADC_OFFSET_4
3751 * @param OffsetState This parameter can be one of the following values:
3752 * @arg @ref LL_ADC_OFFSET_DISABLE
3753 * @arg @ref LL_ADC_OFFSET_ENABLE
3754 * @retval None
3755 */
3756__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3757{
3758 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3759 if (ADCx == ADC3)
3760 {
3761 MODIFY_REG(*preg,
3762 ADC3_OFR1_OFFSET1_EN,
3763 OffsetState);
3764 }
3765 else
3766 {
3767 MODIFY_REG(*preg,
3768 ADC_OFR1_SSATE,
3769 OffsetState);
3770 }
3771}
3772
3773/**
3774 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3775 * offset state disabled or enabled.
3776 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3777 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3778 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3779 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3780 * @param ADCx ADC instance
3781 * @param Offsety This parameter can be one of the following values:
3782 * @arg @ref LL_ADC_OFFSET_1
3783 * @arg @ref LL_ADC_OFFSET_2
3784 * @arg @ref LL_ADC_OFFSET_3
3785 * @arg @ref LL_ADC_OFFSET_4
3786 * @retval Returned value can be one of the following values:
3787 * @arg @ref LL_ADC_OFFSET_DISABLE
3788 * @arg @ref LL_ADC_OFFSET_ENABLE
3789 */
3790__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
3791{
3792 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3793 if (ADCx == ADC3)
3794 {
3795 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSET1_EN);
3796 }
3797 else
3798 {
3799 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3800 }
3801}
3802
3803#endif /* ADC_VER_V5_V90 */
3804
3805/**
3806 * @}
3807 */
3808
3809/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3810 * @{
3811 */
3812
3813/**
3814 * @brief Set ADC group regular conversion trigger source:
3815 * internal (SW start) or from external peripheral (timer event,
3816 * external interrupt line).
3817 * @note On this STM32 series, setting trigger source to external trigger
3818 * also set trigger polarity to rising edge
3819 * (default setting for compatibility with some ADC on other
3820 * STM32 families having this setting set by HW default value).
3821 * In case of need to modify trigger edge, use
3822 * function @ref LL_ADC_REG_SetTriggerEdge().
3823 * @note Availability of parameters of trigger sources from timer
3824 * depends on timers availability on the selected device.
3825 * @note On this STM32 series, setting of this feature is conditioned to
3826 * ADC state:
3827 * ADC must be disabled or enabled without conversion on going
3828 * on group regular.
3829 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3830 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3831 * @param ADCx ADC instance
3832 * @param TriggerSource This parameter can be one of the following values:
3833 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3834 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3835 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3836 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3837 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3838 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3839 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3840 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3841 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3842 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3843 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3844 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3845 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3846 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3847 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3848 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3849 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3850 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3851 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3852 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
3853 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
3854 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
3855 * @retval None
3856 */
3857__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3858{
3859 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3860}
3861
3862/**
3863 * @brief Get ADC group regular conversion trigger source:
3864 * internal (SW start) or from external peripheral (timer event,
3865 * external interrupt line).
3866 * @note To determine whether group regular trigger source is
3867 * internal (SW start) or external, without detail
3868 * of which peripheral is selected as external trigger,
3869 * (equivalent to
3870 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3871 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3872 * @note Availability of parameters of trigger sources from timer
3873 * depends on timers availability on the selected device.
3874 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3875 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3876 * @param ADCx ADC instance
3877 * @retval Returned value can be one of the following values:
3878 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3879 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3880 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3881 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3882 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3883 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3884 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3885 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3886 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3887 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3888 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3889 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3890 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3891 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3892 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3893 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3894 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3895 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3896 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3897 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
3898 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
3899 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
3900 */
3901__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
3902{
3903 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3904
3905 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3906 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3907 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3908
3909 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3910 /* to match with triggers literals definition. */
3911 return ((TriggerSource
3912 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3913 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3914 );
3915}
3916
3917/**
3918 * @brief Get ADC group regular conversion trigger source internal (SW start)
3919 * or external.
3920 * @note In case of group regular trigger source set to external trigger,
3921 * to determine which peripheral is selected as external trigger,
3922 * use function @ref LL_ADC_REG_GetTriggerSource().
3923 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3924 * @param ADCx ADC instance
3925 * @retval Value "0" if trigger source external trigger
3926 * Value "1" if trigger source SW start.
3927 */
3928__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
3929{
3930 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3931}
3932
3933/**
3934 * @brief Set ADC group regular conversion trigger polarity.
3935 * @note Applicable only for trigger source set to external trigger.
3936 * @note On this STM32 series, setting of this feature is conditioned to
3937 * ADC state:
3938 * ADC must be disabled or enabled without conversion on going
3939 * on group regular.
3940 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3941 * @param ADCx ADC instance
3942 * @param ExternalTriggerEdge This parameter can be one of the following values:
3943 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3944 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3945 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3946 * @retval None
3947 */
3948__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3949{
3950 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3951}
3952
3953/**
3954 * @brief Get ADC group regular conversion trigger polarity.
3955 * @note Applicable only for trigger source set to external trigger.
3956 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3957 * @param ADCx ADC instance
3958 * @retval Returned value can be one of the following values:
3959 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3960 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3961 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3962 */
3963__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
3964{
3965 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3966}
3967
3968#if defined(ADC_VER_V5_V90)
3969/**
3970 * @brief Set ADC sampling mode.
3971 * @note This function set the ADC conversion sampling mode
3972 * @note This mode applies to regular group only.
3973 * @note Set sampling mode is applied to all conversion of regular group.
3974 * @note On this STM32 series, setting of this feature is conditioned to
3975 * ADC state:
3976 * ADC must be disabled or enabled without conversion on going
3977 * on group regular.
3978 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
3979 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
3980 * @param ADCx ADC instance
3981 * @param SamplingMode This parameter can be one of the following values:
3982 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3983 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3984 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3985 * @retval None
3986 */
3987__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
3988{
3989 if (ADCx != ADC3)
3990 {
3991 /* Function not available on this instance */
3992 }
3993 else
3994 {
3995 MODIFY_REG(ADCx->CFGR2, ADC3_CFGR2_BULB | ADC3_CFGR2_SMPTRIG, SamplingMode);
3996 }
3997}
3998#endif /* ADC_VER_V5_V90 */
3999
4000/**
4001 * @brief Set ADC group regular sequencer length and scan direction.
4002 * @note Description of ADC group regular sequencer features:
4003 * - For devices with sequencer fully configurable
4004 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4005 * sequencer length and each rank affectation to a channel
4006 * are configurable.
4007 * This function performs configuration of:
4008 * - Sequence length: Number of ranks in the scan sequence.
4009 * - Sequence direction: Unless specified in parameters, sequencer
4010 * scan direction is forward (from rank 1 to rank n).
4011 * Sequencer ranks are selected using
4012 * function "LL_ADC_REG_SetSequencerRanks()".
4013 * - For devices with sequencer not fully configurable
4014 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4015 * sequencer length and each rank affectation to a channel
4016 * are defined by channel number.
4017 * This function performs configuration of:
4018 * - Sequence length: Number of ranks in the scan sequence is
4019 * defined by number of channels set in the sequence,
4020 * rank of each channel is fixed by channel HW number.
4021 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4022 * - Sequence direction: Unless specified in parameters, sequencer
4023 * scan direction is forward (from lowest channel number to
4024 * highest channel number).
4025 * Sequencer ranks are selected using
4026 * function "LL_ADC_REG_SetSequencerChannels()".
4027 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4028 * ADC conversion on only 1 channel.
4029 * @note On this STM32 series, setting of this feature is conditioned to
4030 * ADC state:
4031 * ADC must be disabled or enabled without conversion on going
4032 * on group regular.
4033 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4034 * @param ADCx ADC instance
4035 * @param SequencerNbRanks This parameter can be one of the following values:
4036 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4037 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4038 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4039 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4040 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4041 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4042 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4043 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4044 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4045 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4046 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4047 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4048 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4049 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4050 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4051 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4052 * @retval None
4053 */
4054__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4055{
4056 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4057}
4058
4059/**
4060 * @brief Get ADC group regular sequencer length and scan direction.
4061 * @note Description of ADC group regular sequencer features:
4062 * - For devices with sequencer fully configurable
4063 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4064 * sequencer length and each rank affectation to a channel
4065 * are configurable.
4066 * This function retrieves:
4067 * - Sequence length: Number of ranks in the scan sequence.
4068 * - Sequence direction: Unless specified in parameters, sequencer
4069 * scan direction is forward (from rank 1 to rank n).
4070 * Sequencer ranks are selected using
4071 * function "LL_ADC_REG_SetSequencerRanks()".
4072 * - For devices with sequencer not fully configurable
4073 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4074 * sequencer length and each rank affectation to a channel
4075 * are defined by channel number.
4076 * This function retrieves:
4077 * - Sequence length: Number of ranks in the scan sequence is
4078 * defined by number of channels set in the sequence,
4079 * rank of each channel is fixed by channel HW number.
4080 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4081 * - Sequence direction: Unless specified in parameters, sequencer
4082 * scan direction is forward (from lowest channel number to
4083 * highest channel number).
4084 * Sequencer ranks are selected using
4085 * function "LL_ADC_REG_SetSequencerChannels()".
4086 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4087 * ADC conversion on only 1 channel.
4088 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4089 * @param ADCx ADC instance
4090 * @retval Returned value can be one of the following values:
4091 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4092 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4093 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4094 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4095 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4096 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4097 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4098 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4099 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4100 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4101 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4102 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4103 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4104 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4105 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4106 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4107 */
4108__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4109{
4110 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4111}
4112
4113/**
4114 * @brief Set ADC group regular sequencer discontinuous mode:
4115 * sequence subdivided and scan conversions interrupted every selected
4116 * number of ranks.
4117 * @note It is not possible to enable both ADC group regular
4118 * continuous mode and sequencer discontinuous mode.
4119 * @note It is not possible to enable both ADC auto-injected mode
4120 * and ADC group regular sequencer discontinuous mode.
4121 * @note On this STM32 series, setting of this feature is conditioned to
4122 * ADC state:
4123 * ADC must be disabled or enabled without conversion on going
4124 * on group regular.
4125 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
4126 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4127 * @param ADCx ADC instance
4128 * @param SeqDiscont This parameter can be one of the following values:
4129 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4130 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4131 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4132 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4133 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4134 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4135 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4136 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4137 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4138 * @retval None
4139 */
4140__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4141{
4142 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4143}
4144
4145/**
4146 * @brief Get ADC group regular sequencer discontinuous mode:
4147 * sequence subdivided and scan conversions interrupted every selected
4148 * number of ranks.
4149 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4150 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4151 * @param ADCx ADC instance
4152 * @retval Returned value can be one of the following values:
4153 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4154 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4155 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4156 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4157 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4158 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4159 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4160 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4161 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4162 */
4163__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4164{
4165 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4166}
4167
4168/**
4169 * @brief Set ADC group regular sequence: channel on the selected
4170 * scan sequence rank.
4171 * @note This function performs configuration of:
4172 * - Channels ordering into each rank of scan sequence:
4173 * whatever channel can be placed into whatever rank.
4174 * @note On this STM32 series, ADC group regular sequencer is
4175 * fully configurable: sequencer length and each rank
4176 * affectation to a channel are configurable.
4177 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4178 * @note Depending on devices and packages, some channels may not be available.
4179 * Refer to device datasheet for channels availability.
4180 * @note On this STM32 series, to measure internal channels (VrefInt,
4181 * TempSensor, ...), measurement paths to internal channels must be
4182 * enabled separately.
4183 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4184 * @note On this STM32 series, setting of this feature is conditioned to
4185 * ADC state:
4186 * ADC must be disabled or enabled without conversion on going
4187 * on group regular.
4188 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4189 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4190 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4191 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4192 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4193 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4194 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4195 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4196 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4197 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4198 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4199 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4200 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4201 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4202 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4203 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4204 * @param ADCx ADC instance
4205 * @param Rank This parameter can be one of the following values:
4206 * @arg @ref LL_ADC_REG_RANK_1
4207 * @arg @ref LL_ADC_REG_RANK_2
4208 * @arg @ref LL_ADC_REG_RANK_3
4209 * @arg @ref LL_ADC_REG_RANK_4
4210 * @arg @ref LL_ADC_REG_RANK_5
4211 * @arg @ref LL_ADC_REG_RANK_6
4212 * @arg @ref LL_ADC_REG_RANK_7
4213 * @arg @ref LL_ADC_REG_RANK_8
4214 * @arg @ref LL_ADC_REG_RANK_9
4215 * @arg @ref LL_ADC_REG_RANK_10
4216 * @arg @ref LL_ADC_REG_RANK_11
4217 * @arg @ref LL_ADC_REG_RANK_12
4218 * @arg @ref LL_ADC_REG_RANK_13
4219 * @arg @ref LL_ADC_REG_RANK_14
4220 * @arg @ref LL_ADC_REG_RANK_15
4221 * @arg @ref LL_ADC_REG_RANK_16
4222 * @param Channel This parameter can be one of the following values:
4223 * @arg @ref LL_ADC_CHANNEL_0 (3)
4224 * @arg @ref LL_ADC_CHANNEL_1 (3)
4225 * @arg @ref LL_ADC_CHANNEL_2 (3)
4226 * @arg @ref LL_ADC_CHANNEL_3 (3)
4227 * @arg @ref LL_ADC_CHANNEL_4 (3)
4228 * @arg @ref LL_ADC_CHANNEL_5 (3)
4229 * @arg @ref LL_ADC_CHANNEL_6
4230 * @arg @ref LL_ADC_CHANNEL_7
4231 * @arg @ref LL_ADC_CHANNEL_8
4232 * @arg @ref LL_ADC_CHANNEL_9
4233 * @arg @ref LL_ADC_CHANNEL_10
4234 * @arg @ref LL_ADC_CHANNEL_11
4235 * @arg @ref LL_ADC_CHANNEL_12
4236 * @arg @ref LL_ADC_CHANNEL_13
4237 * @arg @ref LL_ADC_CHANNEL_14
4238 * @arg @ref LL_ADC_CHANNEL_15
4239 * @arg @ref LL_ADC_CHANNEL_16
4240 * @arg @ref LL_ADC_CHANNEL_17
4241 * @arg @ref LL_ADC_CHANNEL_18
4242 * @arg @ref LL_ADC_CHANNEL_19
4243 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4244 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4245 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4246 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4247 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4248 *
4249 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4250 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4251 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4252 * Other channels are slow channels (conversion rate: refer to reference manual).
4253 * @retval None
4254 */
4255__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4256{
4257 /* Set bits with content of parameter "Channel" with bits position */
4258 /* in register and register position depending on parameter "Rank". */
4259 /* Parameters "Rank" and "Channel" are used with masks because containing */
4260 /* other bits reserved for other purpose. */
4261 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4262
4263 MODIFY_REG(*preg,
4264 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4265 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4266}
4267
4268/**
4269 * @brief Get ADC group regular sequence: channel on the selected
4270 * scan sequence rank.
4271 * @note On this STM32 series, ADC group regular sequencer is
4272 * fully configurable: sequencer length and each rank
4273 * affectation to a channel are configurable.
4274 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4275 * @note Depending on devices and packages, some channels may not be available.
4276 * Refer to device datasheet for channels availability.
4277 * @note Usage of the returned channel number:
4278 * - To reinject this channel into another function LL_ADC_xxx:
4279 * the returned channel number is only partly formatted on definition
4280 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4281 * with parts of literals LL_ADC_CHANNEL_x or using
4282 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4283 * Then the selected literal LL_ADC_CHANNEL_x can be used
4284 * as parameter for another function.
4285 * - To get the channel number in decimal format:
4286 * process the returned value with the helper macro
4287 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4288 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4289 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4290 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4291 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4292 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4293 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4294 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4295 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4296 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4297 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4298 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4299 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4300 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4301 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4302 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4303 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4304 * @param ADCx ADC instance
4305 * @param Rank This parameter can be one of the following values:
4306 * @arg @ref LL_ADC_REG_RANK_1
4307 * @arg @ref LL_ADC_REG_RANK_2
4308 * @arg @ref LL_ADC_REG_RANK_3
4309 * @arg @ref LL_ADC_REG_RANK_4
4310 * @arg @ref LL_ADC_REG_RANK_5
4311 * @arg @ref LL_ADC_REG_RANK_6
4312 * @arg @ref LL_ADC_REG_RANK_7
4313 * @arg @ref LL_ADC_REG_RANK_8
4314 * @arg @ref LL_ADC_REG_RANK_9
4315 * @arg @ref LL_ADC_REG_RANK_10
4316 * @arg @ref LL_ADC_REG_RANK_11
4317 * @arg @ref LL_ADC_REG_RANK_12
4318 * @arg @ref LL_ADC_REG_RANK_13
4319 * @arg @ref LL_ADC_REG_RANK_14
4320 * @arg @ref LL_ADC_REG_RANK_15
4321 * @arg @ref LL_ADC_REG_RANK_16
4322 * @retval Returned value can be one of the following values:
4323 * @arg @ref LL_ADC_CHANNEL_0 (3)
4324 * @arg @ref LL_ADC_CHANNEL_1 (3)
4325 * @arg @ref LL_ADC_CHANNEL_2 (3)
4326 * @arg @ref LL_ADC_CHANNEL_3 (3)
4327 * @arg @ref LL_ADC_CHANNEL_4 (3)
4328 * @arg @ref LL_ADC_CHANNEL_5 (3)
4329 * @arg @ref LL_ADC_CHANNEL_6
4330 * @arg @ref LL_ADC_CHANNEL_7
4331 * @arg @ref LL_ADC_CHANNEL_8
4332 * @arg @ref LL_ADC_CHANNEL_9
4333 * @arg @ref LL_ADC_CHANNEL_10
4334 * @arg @ref LL_ADC_CHANNEL_11
4335 * @arg @ref LL_ADC_CHANNEL_12
4336 * @arg @ref LL_ADC_CHANNEL_13
4337 * @arg @ref LL_ADC_CHANNEL_14
4338 * @arg @ref LL_ADC_CHANNEL_15
4339 * @arg @ref LL_ADC_CHANNEL_16
4340 * @arg @ref LL_ADC_CHANNEL_17
4341 * @arg @ref LL_ADC_CHANNEL_18
4342 * @arg @ref LL_ADC_CHANNEL_19
4343 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4344 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4345 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4346 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4347 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4348 *
4349 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4350 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4351 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4352 * Other channels are slow channels (conversion rate: refer to reference manual).\n
4353 * (1, 2) For ADC channel read back from ADC register,
4354 * comparison with internal channel parameter to be done
4355 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4356 */
4357__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4358{
4359 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4360
4361 return (uint32_t)((READ_BIT(*preg,
4362 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4363 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4364 );
4365}
4366
4367/**
4368 * @brief Set ADC continuous conversion mode on ADC group regular.
4369 * @note Description of ADC continuous conversion mode:
4370 * - single mode: one conversion per trigger
4371 * - continuous mode: after the first trigger, following
4372 * conversions launched successively automatically.
4373 * @note It is not possible to enable both ADC group regular
4374 * continuous mode and sequencer discontinuous mode.
4375 * @note On this STM32 series, setting of this feature is conditioned to
4376 * ADC state:
4377 * ADC must be disabled or enabled without conversion on going
4378 * on group regular.
4379 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4380 * @param ADCx ADC instance
4381 * @param Continuous This parameter can be one of the following values:
4382 * @arg @ref LL_ADC_REG_CONV_SINGLE
4383 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4384 * @retval None
4385 */
4386__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4387{
4388 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4389}
4390
4391/**
4392 * @brief Get ADC continuous conversion mode on ADC group regular.
4393 * @note Description of ADC continuous conversion mode:
4394 * - single mode: one conversion per trigger
4395 * - continuous mode: after the first trigger, following
4396 * conversions launched successively automatically.
4397 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4398 * @param ADCx ADC instance
4399 * @retval Returned value can be one of the following values:
4400 * @arg @ref LL_ADC_REG_CONV_SINGLE
4401 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4402 */
4403__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4404{
4405 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4406}
4407/**
4408 * @brief Set ADC data transfer mode
4409 * @note Conversion data can be either:
4410 * - Available in Data Register
4411 * - Transferred by DMA in one shot mode
4412 * - Transferred by DMA in circular mode
4413 * - Transferred to DFSDM data register
4414 * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
4415 * @param ADCx ADC instance
4416 * @param DataTransferMode Select Data Management configuration
4417 * @retval None
4418 */
4419__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
4420{
4421 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
4422}
4423
4424#if defined(ADC_VER_V5_V90)
4425/**
4426 * @brief Enable DMA requests for ADC3.
4427 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4428 * @param ADCx ADC instance
4429 * @retval None
4430 */
4431__STATIC_INLINE void LL_ADC_EnableDMAReq (ADC_TypeDef *ADCx)
4432{
4433 SET_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN);
4434}
4435
4436__STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx)
4437{
4438 CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN);
4439}
4440
4441__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (const ADC_TypeDef *ADCx)
4442{
4443 return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL);
4444}
4445/**
4446 * @brief Set ADC group regular conversion data transfer: no transfer or
4447 * transfer by DMA, and DMA requests mode.
4448 * @note If transfer by DMA selected, specifies the DMA requests
4449 * mode:
4450 * - Limited mode (One shot mode): DMA transfer requests are stopped
4451 * when number of DMA data transfers (number of
4452 * ADC conversions) is reached.
4453 * This ADC mode is intended to be used with DMA mode non-circular.
4454 * - Unlimited mode: DMA transfer requests are unlimited,
4455 * whatever number of DMA data transfers (number of
4456 * ADC conversions).
4457 * This ADC mode is intended to be used with DMA mode circular.
4458 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4459 * mode non-circular:
4460 * when DMA transfers size will be reached, DMA will stop transfers of
4461 * ADC conversions data ADC will raise an overrun error
4462 * (overrun flag and interruption if enabled).
4463 * @note For devices with several ADC instances: ADC multimode DMA
4464 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4465 * @note To configure DMA source address (peripheral address),
4466 * use function @ref LL_ADC_DMA_GetRegAddr().
4467 * @note On this STM32 series, setting of this feature is conditioned to
4468 * ADC state:
4469 * ADC must be disabled or enabled without conversion on going
4470 * on either groups regular or injected.
4471 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransferMode\n
4472 * CFGR DMACFG LL_ADC_REG_SetDMATransferMode
4473 * @param ADCx ADC instance
4474 * @param DMATransfer This parameter can be one of the following values:
4475 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_NONE
4476 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED
4477 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED
4478 * @retval None
4479 */
4480__STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4481{
4482 if (ADCx == ADC3)
4483 {
4484 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG, DMATransfer);
4485 }
4486}
4487
4488/**
4489 * @brief Get ADC group regular conversion data transfer: no transfer or
4490 * transfer by DMA, and DMA requests mode.
4491 * @note If transfer by DMA selected, specifies the DMA requests
4492 * mode:
4493 * - Limited mode (One shot mode): DMA transfer requests are stopped
4494 * when number of DMA data transfers (number of
4495 * ADC conversions) is reached.
4496 * This ADC mode is intended to be used with DMA mode non-circular.
4497 * - Unlimited mode: DMA transfer requests are unlimited,
4498 * whatever number of DMA data transfers (number of
4499 * ADC conversions).
4500 * This ADC mode is intended to be used with DMA mode circular.
4501 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4502 * mode non-circular:
4503 * when DMA transfers size will be reached, DMA will stop transfers of
4504 * ADC conversions data ADC will raise an overrun error
4505 * (overrun flag and interruption if enabled).
4506 * @note For devices with several ADC instances: ADC multimode DMA
4507 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4508 * @note To configure DMA source address (peripheral address),
4509 * use function @ref LL_ADC_DMA_GetRegAddr().
4510 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4511 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4512 * @param ADCx ADC instance
4513 * @retval Returned value can be one of the following values:
4514 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_NONE
4515 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED
4516 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED
4517 */
4518__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(const ADC_TypeDef *ADCx)
4519{
4520 if (ADCx == ADC3)
4521 {
4522 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG));
4523 }
4524 else
4525 {
4526 return 0UL;
4527 }
4528}
4529
4530#endif /* ADC_VER_V5_V90 */
4531
4532/**
4533 * @brief Get ADC data transfer mode
4534 * @note Conversion data can be either:
4535 * - Available in Data Register
4536 * - Transferred by DMA in one shot mode
4537 * - Transferred by DMA in circular mode
4538 * - Transferred to DFSDM data register
4539 * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
4540 * @param ADCx ADC instance
4541 * @retval Returned value can be one of the following values:
4542 * @arg @ref LL_ADC_REG_DR_TRANSFER
4543 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4544 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4545 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
4546 */
4547__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx)
4548{
4549 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
4550}
4551
4552
4553/**
4554 * @brief Set ADC group regular behavior in case of overrun:
4555 * data preserved or overwritten.
4556 * @note Compatibility with devices without feature overrun:
4557 * other devices without this feature have a behavior
4558 * equivalent to data overwritten.
4559 * The default setting of overrun is data preserved.
4560 * Therefore, for compatibility with all devices, parameter
4561 * overrun should be set to data overwritten.
4562 * @note On this STM32 series, setting of this feature is conditioned to
4563 * ADC state:
4564 * ADC must be disabled or enabled without conversion on going
4565 * on group regular.
4566 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4567 * @param ADCx ADC instance
4568 * @param Overrun This parameter can be one of the following values:
4569 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4570 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4571 * @retval None
4572 */
4573__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4574{
4575 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4576}
4577
4578/**
4579 * @brief Get ADC group regular behavior in case of overrun:
4580 * data preserved or overwritten.
4581 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4582 * @param ADCx ADC instance
4583 * @retval Returned value can be one of the following values:
4584 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4585 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4586 */
4587__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4588{
4589 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4590}
4591
4592/**
4593 * @}
4594 */
4595
4596/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4597 * @{
4598 */
4599
4600/**
4601 * @brief Set ADC group injected conversion trigger source:
4602 * internal (SW start) or from external peripheral (timer event,
4603 * external interrupt line).
4604 * @note On this STM32 series, setting trigger source to external trigger
4605 * also set trigger polarity to rising edge
4606 * (default setting for compatibility with some ADC on other
4607 * STM32 families having this setting set by HW default value).
4608 * In case of need to modify trigger edge, use
4609 * function @ref LL_ADC_INJ_SetTriggerEdge().
4610 * @note Availability of parameters of trigger sources from timer
4611 * depends on timers availability on the selected device.
4612 * @note On this STM32 series, setting of this feature is conditioned to
4613 * ADC state:
4614 * ADC must not be disabled. Can be enabled with or without conversion
4615 * on going on either groups regular or injected.
4616 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4617 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4618 * @param ADCx ADC instance
4619 * @param TriggerSource This parameter can be one of the following values:
4620 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4621 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4622 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4623 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4624 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4625 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4626 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4627 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4628 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4629 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4630 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4631 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4632 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4633 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4634 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4635 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4636 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4637 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4638 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4639 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
4640 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
4641 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
4642 * @retval None
4643 */
4644__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4645{
4646 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4647}
4648
4649/**
4650 * @brief Get ADC group injected conversion trigger source:
4651 * internal (SW start) or from external peripheral (timer event,
4652 * external interrupt line).
4653 * @note To determine whether group injected trigger source is
4654 * internal (SW start) or external, without detail
4655 * of which peripheral is selected as external trigger,
4656 * (equivalent to
4657 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4658 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4659 * @note Availability of parameters of trigger sources from timer
4660 * depends on timers availability on the selected device.
4661 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4662 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4663 * @param ADCx ADC instance
4664 * @retval Returned value can be one of the following values:
4665 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4666 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4667 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4668 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4669 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4670 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4671 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4672 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4674 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4676 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4679 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4680 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4681 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4682 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4683 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4684 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
4685 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
4686 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
4687 */
4688__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4689{
4690 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4691
4692 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4693 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4694 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4695
4696 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4697 /* to match with triggers literals definition. */
4698 return ((TriggerSource
4699 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4700 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4701 );
4702}
4703
4704/**
4705 * @brief Get ADC group injected conversion trigger source internal (SW start)
4706 or external
4707 * @note In case of group injected trigger source set to external trigger,
4708 * to determine which peripheral is selected as external trigger,
4709 * use function @ref LL_ADC_INJ_GetTriggerSource.
4710 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4711 * @param ADCx ADC instance
4712 * @retval Value "0" if trigger source external trigger
4713 * Value "1" if trigger source SW start.
4714 */
4715__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4716{
4717 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4718}
4719
4720/**
4721 * @brief Set ADC group injected conversion trigger polarity.
4722 * Applicable only for trigger source set to external trigger.
4723 * @note On this STM32 series, setting of this feature is conditioned to
4724 * ADC state:
4725 * ADC must not be disabled. Can be enabled with or without conversion
4726 * on going on either groups regular or injected.
4727 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4728 * @param ADCx ADC instance
4729 * @param ExternalTriggerEdge This parameter can be one of the following values:
4730 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4731 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4732 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4733 * @retval None
4734 */
4735__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4736{
4737 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4738}
4739
4740/**
4741 * @brief Get ADC group injected conversion trigger polarity.
4742 * Applicable only for trigger source set to external trigger.
4743 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4744 * @param ADCx ADC instance
4745 * @retval Returned value can be one of the following values:
4746 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4747 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4748 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4749 */
4750__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4751{
4752 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4753}
4754
4755/**
4756 * @brief Set ADC group injected sequencer length and scan direction.
4757 * @note This function performs configuration of:
4758 * - Sequence length: Number of ranks in the scan sequence.
4759 * - Sequence direction: Unless specified in parameters, sequencer
4760 * scan direction is forward (from rank 1 to rank n).
4761 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4762 * ADC conversion on only 1 channel.
4763 * @note On this STM32 series, setting of this feature is conditioned to
4764 * ADC state:
4765 * ADC must not be disabled. Can be enabled with or without conversion
4766 * on going on either groups regular or injected.
4767 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4768 * @param ADCx ADC instance
4769 * @param SequencerNbRanks This parameter can be one of the following values:
4770 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4771 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4772 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4773 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4774 * @retval None
4775 */
4776__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4777{
4778 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4779}
4780
4781/**
4782 * @brief Get ADC group injected sequencer length and scan direction.
4783 * @note This function retrieves:
4784 * - Sequence length: Number of ranks in the scan sequence.
4785 * - Sequence direction: Unless specified in parameters, sequencer
4786 * scan direction is forward (from rank 1 to rank n).
4787 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4788 * ADC conversion on only 1 channel.
4789 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4790 * @param ADCx ADC instance
4791 * @retval Returned value can be one of the following values:
4792 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4793 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4794 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4795 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4796 */
4797__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4798{
4799 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4800}
4801
4802/**
4803 * @brief Set ADC group injected sequencer discontinuous mode:
4804 * sequence subdivided and scan conversions interrupted every selected
4805 * number of ranks.
4806 * @note It is not possible to enable both ADC group injected
4807 * auto-injected mode and sequencer discontinuous mode.
4808 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4809 * @param ADCx ADC instance
4810 * @param SeqDiscont This parameter can be one of the following values:
4811 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4812 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4813 * @retval None
4814 */
4815__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4816{
4817 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4818}
4819
4820/**
4821 * @brief Get ADC group injected sequencer discontinuous mode:
4822 * sequence subdivided and scan conversions interrupted every selected
4823 * number of ranks.
4824 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4825 * @param ADCx ADC instance
4826 * @retval Returned value can be one of the following values:
4827 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4828 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4829 */
4830__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4831{
4832 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4833}
4834
4835/**
4836 * @brief Set ADC group injected sequence: channel on the selected
4837 * sequence rank.
4838 * @note Depending on devices and packages, some channels may not be available.
4839 * Refer to device datasheet for channels availability.
4840 * @note On this STM32 series, to measure internal channels (VrefInt,
4841 * TempSensor, ...), measurement paths to internal channels must be
4842 * enabled separately.
4843 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4844 * @note On STM32H7, some fast channels are available: fast analog inputs
4845 * coming from GPIO pads (ADC_IN0..5).
4846 * @note On this STM32 series, setting of this feature is conditioned to
4847 * ADC state:
4848 * ADC must not be disabled. Can be enabled with or without conversion
4849 * on going on either groups regular or injected.
4850 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4851 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4852 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4853 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4854 * @param ADCx ADC instance
4855 * @param Rank This parameter can be one of the following values:
4856 * @arg @ref LL_ADC_INJ_RANK_1
4857 * @arg @ref LL_ADC_INJ_RANK_2
4858 * @arg @ref LL_ADC_INJ_RANK_3
4859 * @arg @ref LL_ADC_INJ_RANK_4
4860 * @param Channel This parameter can be one of the following values:
4861 * @arg @ref LL_ADC_CHANNEL_0 (3)
4862 * @arg @ref LL_ADC_CHANNEL_1 (3)
4863 * @arg @ref LL_ADC_CHANNEL_2 (3)
4864 * @arg @ref LL_ADC_CHANNEL_3 (3)
4865 * @arg @ref LL_ADC_CHANNEL_4 (3)
4866 * @arg @ref LL_ADC_CHANNEL_5 (3)
4867 * @arg @ref LL_ADC_CHANNEL_6
4868 * @arg @ref LL_ADC_CHANNEL_7
4869 * @arg @ref LL_ADC_CHANNEL_8
4870 * @arg @ref LL_ADC_CHANNEL_9
4871 * @arg @ref LL_ADC_CHANNEL_10
4872 * @arg @ref LL_ADC_CHANNEL_11
4873 * @arg @ref LL_ADC_CHANNEL_12
4874 * @arg @ref LL_ADC_CHANNEL_13
4875 * @arg @ref LL_ADC_CHANNEL_14
4876 * @arg @ref LL_ADC_CHANNEL_15
4877 * @arg @ref LL_ADC_CHANNEL_16
4878 * @arg @ref LL_ADC_CHANNEL_17
4879 * @arg @ref LL_ADC_CHANNEL_18
4880 * @arg @ref LL_ADC_CHANNEL_19
4881 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4882 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4883 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4884 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4885 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4886 *
4887 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4888 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4889 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4890 * Other channels are slow channels (conversion rate: refer to reference manual).
4891 * @retval None
4892 */
4893__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4894{
4895 /* Set bits with content of parameter "Channel" with bits position */
4896 /* in register depending on parameter "Rank". */
4897 /* Parameters "Rank" and "Channel" are used with masks because containing */
4898 /* other bits reserved for other purpose. */
4899 MODIFY_REG(ADCx->JSQR,
4900 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4901 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4902}
4903
4904/**
4905 * @brief Get ADC group injected sequence: channel on the selected
4906 * sequence rank.
4907 * @note Depending on devices and packages, some channels may not be available.
4908 * Refer to device datasheet for channels availability.
4909 * @note Usage of the returned channel number:
4910 * - To reinject this channel into another function LL_ADC_xxx:
4911 * the returned channel number is only partly formatted on definition
4912 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4913 * with parts of literals LL_ADC_CHANNEL_x or using
4914 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4915 * Then the selected literal LL_ADC_CHANNEL_x can be used
4916 * as parameter for another function.
4917 * - To get the channel number in decimal format:
4918 * process the returned value with the helper macro
4919 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4920 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4921 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4922 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4923 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4924 * @param ADCx ADC instance
4925 * @param Rank This parameter can be one of the following values:
4926 * @arg @ref LL_ADC_INJ_RANK_1
4927 * @arg @ref LL_ADC_INJ_RANK_2
4928 * @arg @ref LL_ADC_INJ_RANK_3
4929 * @arg @ref LL_ADC_INJ_RANK_4
4930 * @retval Returned value can be one of the following values:
4931 * @arg @ref LL_ADC_CHANNEL_0 (3)
4932 * @arg @ref LL_ADC_CHANNEL_1 (3)
4933 * @arg @ref LL_ADC_CHANNEL_2 (3)
4934 * @arg @ref LL_ADC_CHANNEL_3 (3)
4935 * @arg @ref LL_ADC_CHANNEL_4 (3)
4936 * @arg @ref LL_ADC_CHANNEL_5 (3)
4937 * @arg @ref LL_ADC_CHANNEL_6
4938 * @arg @ref LL_ADC_CHANNEL_7
4939 * @arg @ref LL_ADC_CHANNEL_8
4940 * @arg @ref LL_ADC_CHANNEL_9
4941 * @arg @ref LL_ADC_CHANNEL_10
4942 * @arg @ref LL_ADC_CHANNEL_11
4943 * @arg @ref LL_ADC_CHANNEL_12
4944 * @arg @ref LL_ADC_CHANNEL_13
4945 * @arg @ref LL_ADC_CHANNEL_14
4946 * @arg @ref LL_ADC_CHANNEL_15
4947 * @arg @ref LL_ADC_CHANNEL_16
4948 * @arg @ref LL_ADC_CHANNEL_17
4949 * @arg @ref LL_ADC_CHANNEL_18
4950 * @arg @ref LL_ADC_CHANNEL_19
4951 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4952 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4953 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4954 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4955 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4956 *
4957 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4958 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4959 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4960 * Other channels are slow channels (conversion rate: refer to reference manual).\n
4961 * (1, 2) For ADC channel read back from ADC register,
4962 * comparison with internal channel parameter to be done
4963 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4964 */
4965__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4966{
4967 return (uint32_t)((READ_BIT(ADCx->JSQR,
4968 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4969 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4970 );
4971}
4972
4973/**
4974 * @brief Set ADC group injected conversion trigger:
4975 * independent or from ADC group regular.
4976 * @note This mode can be used to extend number of data registers
4977 * updated after one ADC conversion trigger and with data
4978 * permanently kept (not erased by successive conversions of scan of
4979 * ADC sequencer ranks), up to 5 data registers:
4980 * 1 data register on ADC group regular, 4 data registers
4981 * on ADC group injected.
4982 * @note If ADC group injected injected trigger source is set to an
4983 * external trigger, this feature must be must be set to
4984 * independent trigger.
4985 * ADC group injected automatic trigger is compliant only with
4986 * group injected trigger source set to SW start, without any
4987 * further action on ADC group injected conversion start or stop:
4988 * in this case, ADC group injected is controlled only
4989 * from ADC group regular.
4990 * @note It is not possible to enable both ADC group injected
4991 * auto-injected mode and sequencer discontinuous mode.
4992 * @note On this STM32 series, setting of this feature is conditioned to
4993 * ADC state:
4994 * ADC must be disabled or enabled without conversion on going
4995 * on either groups regular or injected.
4996 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4997 * @param ADCx ADC instance
4998 * @param TrigAuto This parameter can be one of the following values:
4999 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5000 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5001 * @retval None
5002 */
5003__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5004{
5005 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5006}
5007
5008/**
5009 * @brief Get ADC group injected conversion trigger:
5010 * independent or from ADC group regular.
5011 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
5012 * @param ADCx ADC instance
5013 * @retval Returned value can be one of the following values:
5014 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5015 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5016 */
5017__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
5018{
5019 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5020}
5021
5022/**
5023 * @brief Set ADC group injected contexts queue mode.
5024 * @note A context is a setting of group injected sequencer:
5025 * - group injected trigger
5026 * - sequencer length
5027 * - sequencer ranks
5028 * If contexts queue is disabled:
5029 * - only 1 sequence can be configured
5030 * and is active perpetually.
5031 * If contexts queue is enabled:
5032 * - up to 2 contexts can be queued
5033 * and are checked in and out as a FIFO stack (first-in, first-out).
5034 * - If a new context is set when queues is full, error is triggered
5035 * by interruption "Injected Queue Overflow".
5036 * - Two behaviors are possible when all contexts have been processed:
5037 * the contexts queue can maintain the last context active perpetually
5038 * or can be empty and injected group triggers are disabled.
5039 * - Triggers can be only external (not internal SW start)
5040 * - Caution: The sequence must be fully configured in one time
5041 * (one write of register JSQR makes a check-in of a new context
5042 * into the queue).
5043 * Therefore functions to set separately injected trigger and
5044 * sequencer channels cannot be used, register JSQR must be set
5045 * using function @ref LL_ADC_INJ_ConfigQueueContext().
5046 * @note This parameter can be modified only when no conversion is on going
5047 * on either groups regular or injected.
5048 * @note A modification of the context mode (bit JQDIS) causes the contexts
5049 * queue to be flushed and the register JSQR is cleared.
5050 * @note On this STM32 series, setting of this feature is conditioned to
5051 * ADC state:
5052 * ADC must be disabled or enabled without conversion on going
5053 * on either groups regular or injected.
5054 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
5055 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
5056 * @param ADCx ADC instance
5057 * @param QueueMode This parameter can be one of the following values:
5058 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5059 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5060 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5061 * @retval None
5062 */
5063__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5064{
5065 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5066}
5067
5068/**
5069 * @brief Get ADC group injected context queue mode.
5070 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
5071 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
5072 * @param ADCx ADC instance
5073 * @retval Returned value can be one of the following values:
5074 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5075 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5076 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5077 */
5078__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
5079{
5080 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5081}
5082
5083/**
5084 * @brief Set one context on ADC group injected that will be checked in
5085 * contexts queue.
5086 * @note A context is a setting of group injected sequencer:
5087 * - group injected trigger
5088 * - sequencer length
5089 * - sequencer ranks
5090 * This function is intended to be used when contexts queue is enabled,
5091 * because the sequence must be fully configured in one time
5092 * (functions to set separately injected trigger and sequencer channels
5093 * cannot be used):
5094 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
5095 * @note In the contexts queue, only the active context can be read.
5096 * The parameters of this function can be read using functions:
5097 * @arg @ref LL_ADC_INJ_GetTriggerSource()
5098 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
5099 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
5100 * @note On this STM32 series, to measure internal channels (VrefInt,
5101 * TempSensor, ...), measurement paths to internal channels must be
5102 * enabled separately.
5103 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5104 * @note On STM32H7, some fast channels are available: fast analog inputs
5105 * coming from GPIO pads (ADC_IN0..5).
5106 * @note On this STM32 series, setting of this feature is conditioned to
5107 * ADC state:
5108 * ADC must not be disabled. Can be enabled with or without conversion
5109 * on going on either groups regular or injected.
5110 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
5111 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
5112 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
5113 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
5114 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
5115 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
5116 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
5117 * @param ADCx ADC instance
5118 * @param TriggerSource This parameter can be one of the following values:
5119 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5120 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5121 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5122 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5123 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5124 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5125 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5126 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5127 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5128 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5129 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5130 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5131 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5132 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5133 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5134 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5135 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5136 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
5137 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
5138 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
5139 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
5140 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
5141 * @param ExternalTriggerEdge This parameter can be one of the following values:
5142 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5143 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5144 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5145 *
5146 * Note: This parameter is discarded in case of SW start:
5147 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5148 * @param SequencerNbRanks This parameter can be one of the following values:
5149 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5150 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5151 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5152 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5153 * @param Rank1_Channel This parameter can be one of the following values:
5154 * @arg @ref LL_ADC_CHANNEL_0 (3)
5155 * @arg @ref LL_ADC_CHANNEL_1 (3)
5156 * @arg @ref LL_ADC_CHANNEL_2 (3)
5157 * @arg @ref LL_ADC_CHANNEL_3 (3)
5158 * @arg @ref LL_ADC_CHANNEL_4 (3)
5159 * @arg @ref LL_ADC_CHANNEL_5 (3)
5160 * @arg @ref LL_ADC_CHANNEL_6
5161 * @arg @ref LL_ADC_CHANNEL_7
5162 * @arg @ref LL_ADC_CHANNEL_8
5163 * @arg @ref LL_ADC_CHANNEL_9
5164 * @arg @ref LL_ADC_CHANNEL_10
5165 * @arg @ref LL_ADC_CHANNEL_11
5166 * @arg @ref LL_ADC_CHANNEL_12
5167 * @arg @ref LL_ADC_CHANNEL_13
5168 * @arg @ref LL_ADC_CHANNEL_14
5169 * @arg @ref LL_ADC_CHANNEL_15
5170 * @arg @ref LL_ADC_CHANNEL_16
5171 * @arg @ref LL_ADC_CHANNEL_17
5172 * @arg @ref LL_ADC_CHANNEL_18
5173 * @arg @ref LL_ADC_CHANNEL_19
5174 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5175 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5176 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5177 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5178 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5179 *
5180 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5181 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5182 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5183 * Other channels are slow channels (conversion rate: refer to reference manual).
5184 * @param Rank2_Channel This parameter can be one of the following values:
5185 * @arg @ref LL_ADC_CHANNEL_0 (3)
5186 * @arg @ref LL_ADC_CHANNEL_1 (3)
5187 * @arg @ref LL_ADC_CHANNEL_2 (3)
5188 * @arg @ref LL_ADC_CHANNEL_3 (3)
5189 * @arg @ref LL_ADC_CHANNEL_4 (3)
5190 * @arg @ref LL_ADC_CHANNEL_5 (3)
5191 * @arg @ref LL_ADC_CHANNEL_6
5192 * @arg @ref LL_ADC_CHANNEL_7
5193 * @arg @ref LL_ADC_CHANNEL_8
5194 * @arg @ref LL_ADC_CHANNEL_9
5195 * @arg @ref LL_ADC_CHANNEL_10
5196 * @arg @ref LL_ADC_CHANNEL_11
5197 * @arg @ref LL_ADC_CHANNEL_12
5198 * @arg @ref LL_ADC_CHANNEL_13
5199 * @arg @ref LL_ADC_CHANNEL_14
5200 * @arg @ref LL_ADC_CHANNEL_15
5201 * @arg @ref LL_ADC_CHANNEL_16
5202 * @arg @ref LL_ADC_CHANNEL_17
5203 * @arg @ref LL_ADC_CHANNEL_18
5204 * @arg @ref LL_ADC_CHANNEL_19
5205 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5206 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5207 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5208 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5209 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5210 *
5211 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5212 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5213 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5214 * Other channels are slow channels (conversion rate: refer to reference manual).
5215 * @param Rank3_Channel This parameter can be one of the following values:
5216 * @arg @ref LL_ADC_CHANNEL_0 (3)
5217 * @arg @ref LL_ADC_CHANNEL_1 (3)
5218 * @arg @ref LL_ADC_CHANNEL_2 (3)
5219 * @arg @ref LL_ADC_CHANNEL_3 (3)
5220 * @arg @ref LL_ADC_CHANNEL_4 (3)
5221 * @arg @ref LL_ADC_CHANNEL_5 (3)
5222 * @arg @ref LL_ADC_CHANNEL_6
5223 * @arg @ref LL_ADC_CHANNEL_7
5224 * @arg @ref LL_ADC_CHANNEL_8
5225 * @arg @ref LL_ADC_CHANNEL_9
5226 * @arg @ref LL_ADC_CHANNEL_10
5227 * @arg @ref LL_ADC_CHANNEL_11
5228 * @arg @ref LL_ADC_CHANNEL_12
5229 * @arg @ref LL_ADC_CHANNEL_13
5230 * @arg @ref LL_ADC_CHANNEL_14
5231 * @arg @ref LL_ADC_CHANNEL_15
5232 * @arg @ref LL_ADC_CHANNEL_16
5233 * @arg @ref LL_ADC_CHANNEL_17
5234 * @arg @ref LL_ADC_CHANNEL_18
5235 * @arg @ref LL_ADC_CHANNEL_19
5236 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5237 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5238 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5239 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5240 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5241 *
5242 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5243 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5244 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5245 * Other channels are slow channels (conversion rate: refer to reference manual).
5246 * @param Rank4_Channel This parameter can be one of the following values:
5247 * @arg @ref LL_ADC_CHANNEL_0 (3)
5248 * @arg @ref LL_ADC_CHANNEL_1 (3)
5249 * @arg @ref LL_ADC_CHANNEL_2 (3)
5250 * @arg @ref LL_ADC_CHANNEL_3 (3)
5251 * @arg @ref LL_ADC_CHANNEL_4 (3)
5252 * @arg @ref LL_ADC_CHANNEL_5 (3)
5253 * @arg @ref LL_ADC_CHANNEL_6
5254 * @arg @ref LL_ADC_CHANNEL_7
5255 * @arg @ref LL_ADC_CHANNEL_8
5256 * @arg @ref LL_ADC_CHANNEL_9
5257 * @arg @ref LL_ADC_CHANNEL_10
5258 * @arg @ref LL_ADC_CHANNEL_11
5259 * @arg @ref LL_ADC_CHANNEL_12
5260 * @arg @ref LL_ADC_CHANNEL_13
5261 * @arg @ref LL_ADC_CHANNEL_14
5262 * @arg @ref LL_ADC_CHANNEL_15
5263 * @arg @ref LL_ADC_CHANNEL_16
5264 * @arg @ref LL_ADC_CHANNEL_17
5265 * @arg @ref LL_ADC_CHANNEL_18
5266 * @arg @ref LL_ADC_CHANNEL_19
5267 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5268 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5269 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5270 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5271 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5272 *
5273 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5274 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5275 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5276 * Other channels are slow channels (conversion rate: refer to reference manual).
5277 * @retval None
5278 */
5279__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5280 uint32_t TriggerSource,
5281 uint32_t ExternalTriggerEdge,
5282 uint32_t SequencerNbRanks,
5283 uint32_t Rank1_Channel,
5284 uint32_t Rank2_Channel,
5285 uint32_t Rank3_Channel,
5286 uint32_t Rank4_Channel)
5287{
5288 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5289 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5290 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5291 /* because containing other bits reserved for other purpose. */
5292 /* If parameter "TriggerSource" is set to SW start, then parameter */
5293 /* "ExternalTriggerEdge" is discarded. */
5294 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5295 MODIFY_REG(ADCx->JSQR,
5296 ADC_JSQR_JEXTSEL |
5297 ADC_JSQR_JEXTEN |
5298 ADC_JSQR_JSQ4 |
5299 ADC_JSQR_JSQ3 |
5300 ADC_JSQR_JSQ2 |
5301 ADC_JSQR_JSQ1 |
5302 ADC_JSQR_JL,
5303 (TriggerSource & ADC_JSQR_JEXTSEL) |
5304 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5305 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5306 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5307 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5308 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5309 SequencerNbRanks
5310 );
5311}
5312
5313/**
5314 * @}
5315 */
5316
5317/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5318 * @{
5319 */
5320
5321/**
5322 * @brief Set sampling time of the selected ADC channel
5323 * Unit: ADC clock cycles.
5324 * @note On this device, sampling time is on channel scope: independently
5325 * of channel mapped on ADC group regular or injected.
5326 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5327 * converted:
5328 * sampling time constraints must be respected (sampling time can be
5329 * adjusted in function of ADC clock frequency and sampling time
5330 * setting).
5331 * Refer to device datasheet for timings values (parameters TS_vrefint,
5332 * TS_temp, ...).
5333 * @note Conversion time is the addition of sampling time and processing time.
5334 * On this STM32 series, ADC processing time is:
5335 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5336 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5337 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5338 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5339 * @note In case of ADC conversion of internal channel (VrefInt,
5340 * temperature sensor, ...), a sampling time minimum value
5341 * is required.
5342 * Refer to device datasheet.
5343 * @note On this STM32 series, setting of this feature is conditioned to
5344 * ADC state:
5345 * ADC must be disabled or enabled without conversion on going
5346 * on either groups regular or injected.
5347 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5348 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5349 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5350 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5351 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5352 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5353 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5354 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5355 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5356 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5357 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5358 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5359 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5360 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5361 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5362 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5363 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5364 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5365 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5366 * @param ADCx ADC instance
5367 * @param Channel This parameter can be one of the following values:
5368 * @arg @ref LL_ADC_CHANNEL_0 (3)
5369 * @arg @ref LL_ADC_CHANNEL_1 (3)
5370 * @arg @ref LL_ADC_CHANNEL_2 (3)
5371 * @arg @ref LL_ADC_CHANNEL_3 (3)
5372 * @arg @ref LL_ADC_CHANNEL_4 (3)
5373 * @arg @ref LL_ADC_CHANNEL_5 (3)
5374 * @arg @ref LL_ADC_CHANNEL_6
5375 * @arg @ref LL_ADC_CHANNEL_7
5376 * @arg @ref LL_ADC_CHANNEL_8
5377 * @arg @ref LL_ADC_CHANNEL_9
5378 * @arg @ref LL_ADC_CHANNEL_10
5379 * @arg @ref LL_ADC_CHANNEL_11
5380 * @arg @ref LL_ADC_CHANNEL_12
5381 * @arg @ref LL_ADC_CHANNEL_13
5382 * @arg @ref LL_ADC_CHANNEL_14
5383 * @arg @ref LL_ADC_CHANNEL_15
5384 * @arg @ref LL_ADC_CHANNEL_16
5385 * @arg @ref LL_ADC_CHANNEL_17
5386 * @arg @ref LL_ADC_CHANNEL_18
5387 * @arg @ref LL_ADC_CHANNEL_19
5388 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5389 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5390 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5391 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5392 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5393 *
5394 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5395 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5396 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5397 * Other channels are slow channels (conversion rate: refer to reference manual).
5398 * @param SamplingTime This parameter can be one of the following values:
5399 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
5400 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5401 * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
5402 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
5403 * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
5404 * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
5405 * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
5406 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
5407 * @retval None
5408 */
5409__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5410{
5411 /* Set bits with content of parameter "SamplingTime" with bits position */
5412 /* in register and register position depending on parameter "Channel". */
5413 /* Parameter "Channel" is used with masks because containing */
5414 /* other bits reserved for other purpose. */
5415 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5416
5417 MODIFY_REG(*preg,
5418 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5419 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5420}
5421
5422/**
5423 * @brief Get sampling time of the selected ADC channel
5424 * Unit: ADC clock cycles.
5425 * @note On this device, sampling time is on channel scope: independently
5426 * of channel mapped on ADC group regular or injected.
5427 * @note Conversion time is the addition of sampling time and processing time.
5428 * On this STM32 series, ADC processing time is:
5429 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5430 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5431 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5432 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5433 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5434 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5435 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5436 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5437 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5438 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5439 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5440 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5441 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5442 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5443 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5444 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5445 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5446 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5447 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5448 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5449 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5450 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5451 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5452 * @param ADCx ADC instance
5453 * @param Channel This parameter can be one of the following values:
5454 * @arg @ref LL_ADC_CHANNEL_0 (3)
5455 * @arg @ref LL_ADC_CHANNEL_1 (3)
5456 * @arg @ref LL_ADC_CHANNEL_2 (3)
5457 * @arg @ref LL_ADC_CHANNEL_3 (3)
5458 * @arg @ref LL_ADC_CHANNEL_4 (3)
5459 * @arg @ref LL_ADC_CHANNEL_5 (3)
5460 * @arg @ref LL_ADC_CHANNEL_6
5461 * @arg @ref LL_ADC_CHANNEL_7
5462 * @arg @ref LL_ADC_CHANNEL_8
5463 * @arg @ref LL_ADC_CHANNEL_9
5464 * @arg @ref LL_ADC_CHANNEL_10
5465 * @arg @ref LL_ADC_CHANNEL_11
5466 * @arg @ref LL_ADC_CHANNEL_12
5467 * @arg @ref LL_ADC_CHANNEL_13
5468 * @arg @ref LL_ADC_CHANNEL_14
5469 * @arg @ref LL_ADC_CHANNEL_15
5470 * @arg @ref LL_ADC_CHANNEL_16
5471 * @arg @ref LL_ADC_CHANNEL_17
5472 * @arg @ref LL_ADC_CHANNEL_18
5473 * @arg @ref LL_ADC_CHANNEL_19
5474 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5475 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5476 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5477 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5478 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5479 *
5480 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5481 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5482 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5483 * Other channels are slow channels (conversion rate: refer to reference manual).
5484 * @retval Returned value can be one of the following values:
5485 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
5486 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5487 * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
5488 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
5489 * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
5490 * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
5491 * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
5492 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
5493 */
5494__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5495{
5496 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5497
5498 return (uint32_t)(READ_BIT(*preg,
5499 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5500 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5501 );
5502}
5503
5504/**
5505 * @brief Set mode single-ended or differential input of the selected
5506 * ADC channel.
5507 * @note Channel ending is on channel scope: independently of channel mapped
5508 * on ADC group regular or injected.
5509 * In differential mode: Differential measurement is carried out
5510 * between the selected channel 'i' (positive input) and
5511 * channel 'i+1' (negative input). Only channel 'i' has to be
5512 * configured, channel 'i+1' is configured automatically.
5513 * @note Refer to Reference Manual to ensure the selected channel is
5514 * available in differential mode.
5515 * For example, internal channels (VrefInt, TempSensor, ...) are
5516 * not available in differential mode.
5517 * @note When configuring a channel 'i' in differential mode,
5518 * the channel 'i+1' is not usable separately.
5519 * @note On STM32H7, some channels are internally fixed to single-ended inputs
5520 * configuration:
5521 * - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
5522 * - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
5523 * - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
5524 * @note For ADC channels configured in differential mode, both inputs
5525 * should be biased at (Vref+)/2 +/-200mV.
5526 * (Vref+ is the analog voltage reference)
5527 * @note On this STM32 series, setting of this feature is conditioned to
5528 * ADC state:
5529 * ADC must be ADC disabled.
5530 * @note One or several values can be selected.
5531 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5532 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5533 * @param ADCx ADC instance
5534 * @param Channel This parameter can be one of the following values:
5535 * @arg @ref LL_ADC_CHANNEL_1
5536 * @arg @ref LL_ADC_CHANNEL_2
5537 * @arg @ref LL_ADC_CHANNEL_3
5538 * @arg @ref LL_ADC_CHANNEL_4
5539 * @arg @ref LL_ADC_CHANNEL_5
5540 * @arg @ref LL_ADC_CHANNEL_10
5541 * @arg @ref LL_ADC_CHANNEL_11
5542 * @arg @ref LL_ADC_CHANNEL_12
5543 * @arg @ref LL_ADC_CHANNEL_13
5544 * @arg @ref LL_ADC_CHANNEL_14
5545 * @arg @ref LL_ADC_CHANNEL_15
5546 * @arg @ref LL_ADC_CHANNEL_16
5547 * @arg @ref LL_ADC_CHANNEL_17
5548 * @arg @ref LL_ADC_CHANNEL_18
5549 * @arg @ref LL_ADC_CHANNEL_19
5550 * @param SingleDiff This parameter can be a combination of the following values:
5551 * @arg @ref LL_ADC_SINGLE_ENDED
5552 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5553 * @retval None
5554 */
5555__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5556{
5557#if defined(ADC_VER_V5_V90)
5558 /* Bits of channels in single or differential mode are set only for */
5559 /* differential mode (for single mode, mask of bits allowed to be set is */
5560 /* shifted out of range of bits of channels in single or differential mode. */
5561 if (ADCx == ADC3)
5562 {
5563 MODIFY_REG(ADCx->LTR2_DIFSEL,
5564 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5565 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5566 }
5567 else
5568 {
5569 MODIFY_REG(ADCx->DIFSEL_RES12,
5570 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5571 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5572 }
5573#else /* ADC_VER_V5_V90 */
5574 /* Bits of channels in single or differential mode are set only for */
5575 /* differential mode (for single mode, mask of bits allowed to be set is */
5576 /* shifted out of range of bits of channels in single or differential mode. */
5577 MODIFY_REG(ADCx->DIFSEL,
5578 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5579 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5580#endif /* ADC_VER_V5_V90 */
5581}
5582
5583/**
5584 * @brief Get mode single-ended or differential input of the selected
5585 * ADC channel.
5586 * @note When configuring a channel 'i' in differential mode,
5587 * the channel 'i+1' is not usable separately.
5588 * Therefore, to ensure a channel is configured in single-ended mode,
5589 * the configuration of channel itself and the channel 'i-1' must be
5590 * read back (to ensure that the selected channel channel has not been
5591 * configured in differential mode by the previous channel).
5592 * @note Refer to Reference Manual to ensure the selected channel is
5593 * available in differential mode.
5594 * For example, internal channels (VrefInt, TempSensor, ...) are
5595 * not available in differential mode.
5596 * @note When configuring a channel 'i' in differential mode,
5597 * the channel 'i+1' is not usable separately.
5598 * @note On STM32H7, some channels are internally fixed to single-ended inputs
5599 * configuration:
5600 * - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
5601 * - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
5602 * - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
5603 * @note One or several values can be selected. In this case, the value
5604 * returned is null if all channels are in single ended-mode.
5605 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5606 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5607 * @param ADCx ADC instance
5608 * @param Channel This parameter can be a combination of the following values:
5609 * @arg @ref LL_ADC_CHANNEL_1
5610 * @arg @ref LL_ADC_CHANNEL_2
5611 * @arg @ref LL_ADC_CHANNEL_3
5612 * @arg @ref LL_ADC_CHANNEL_4
5613 * @arg @ref LL_ADC_CHANNEL_5
5614 * @arg @ref LL_ADC_CHANNEL_10
5615 * @arg @ref LL_ADC_CHANNEL_11
5616 * @arg @ref LL_ADC_CHANNEL_12
5617 * @arg @ref LL_ADC_CHANNEL_13
5618 * @arg @ref LL_ADC_CHANNEL_14
5619 * @arg @ref LL_ADC_CHANNEL_15
5620 * @arg @ref LL_ADC_CHANNEL_16
5621 * @arg @ref LL_ADC_CHANNEL_17
5622 * @arg @ref LL_ADC_CHANNEL_18
5623 * @arg @ref LL_ADC_CHANNEL_19
5624 * @retval 0: channel in single-ended mode, else: channel in differential mode
5625 */
5626__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5627{
5628#if defined(ADC_VER_V5_V90)
5629 return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5630#else
5631 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5632#endif /* ADC_VER_V5_V90 */
5633}
5634
5635/**
5636 * @}
5637 */
5638
5639/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5640 * @{
5641 */
5642
5643/**
5644 * @brief Set ADC analog watchdog monitored channels:
5645 * a single channel, multiple channels or all channels,
5646 * on ADC groups regular and-or injected.
5647 * @note Once monitored channels are selected, analog watchdog
5648 * is enabled.
5649 * @note In case of need to define a single channel to monitor
5650 * with analog watchdog from sequencer channel definition,
5651 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5652 * @note On this STM32 series, there are 2 kinds of analog watchdog
5653 * instance:
5654 * - AWD standard (instance AWD1):
5655 * - channels monitored: can monitor 1 channel or all channels.
5656 * - groups monitored: ADC groups regular and-or injected.
5657 * - resolution: resolution is not limited (corresponds to
5658 * ADC resolution configured).
5659 * - AWD flexible (instances AWD2, AWD3):
5660 * - channels monitored: flexible on channels monitored, selection is
5661 * channel wise, from from 1 to all channels.
5662 * Specificity of this analog watchdog: Multiple channels can
5663 * be selected. For example:
5664 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5665 * - groups monitored: not selection possible (monitoring on both
5666 * groups regular and injected).
5667 * Channels selected are monitored on groups regular and injected:
5668 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5669 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5670 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5671 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5672 * the 2 LSB are ignored.
5673 * @note On this STM32 series, setting of this feature is conditioned to
5674 * ADC state:
5675 * ADC must be disabled or enabled without conversion on going
5676 * on either groups regular or injected.
5677 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5678 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5679 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5680 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5681 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5682 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5683 * @param ADCx ADC instance
5684 * @param AWDy This parameter can be one of the following values:
5685 * @arg @ref LL_ADC_AWD1
5686 * @arg @ref LL_ADC_AWD2
5687 * @arg @ref LL_ADC_AWD3
5688 * @param AWDChannelGroup This parameter can be one of the following values:
5689 * @arg @ref LL_ADC_AWD_DISABLE
5690 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5691 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5692 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5693 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5694 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5695 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5696 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5697 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5698 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5699 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5700 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5701 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5702 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5703 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5704 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5705 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5706 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5707 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5708 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5709 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5710 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5711 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5712 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5713 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5714 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5715 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5716 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5717 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5718 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5719 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5720 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5721 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5722 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5723 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5724 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5725 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5726 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5727 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5728 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5729 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5730 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5731 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5732 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5733 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5734 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5735 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5736 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5737 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5738 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5739 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5740 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5741 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5742 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5743 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5744 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5745 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5746 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5747 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5748 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5749 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5750 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5751 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5752 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5753 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5754 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5755 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5756 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
5757 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5758 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5759 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
5760 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5761 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5762 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
5763 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
5764 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
5765 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
5766 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
5767 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
5768 *
5769 * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
5770 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5771 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
5772 * @retval None
5773 */
5774__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5775{
5776 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5777 /* in register and register position depending on parameter "AWDy". */
5778 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5779 /* containing other bits reserved for other purpose. */
5780 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5781 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5782
5783 MODIFY_REG(*preg,
5784 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5785 AWDChannelGroup & AWDy);
5786}
5787
5788/**
5789 * @brief Get ADC analog watchdog monitored channel.
5790 * @note Usage of the returned channel number:
5791 * - To reinject this channel into another function LL_ADC_xxx:
5792 * the returned channel number is only partly formatted on definition
5793 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5794 * with parts of literals LL_ADC_CHANNEL_x or using
5795 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5796 * Then the selected literal LL_ADC_CHANNEL_x can be used
5797 * as parameter for another function.
5798 * - To get the channel number in decimal format:
5799 * process the returned value with the helper macro
5800 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5801 * Applicable only when the analog watchdog is set to monitor
5802 * one channel.
5803 * @note On this STM32 series, there are 2 kinds of analog watchdog
5804 * instance:
5805 * - AWD standard (instance AWD1):
5806 * - channels monitored: can monitor 1 channel or all channels.
5807 * - groups monitored: ADC groups regular and-or injected.
5808 * - resolution: resolution is not limited (corresponds to
5809 * ADC resolution configured).
5810 * - AWD flexible (instances AWD2, AWD3):
5811 * - channels monitored: flexible on channels monitored, selection is
5812 * channel wise, from from 1 to all channels.
5813 * Specificity of this analog watchdog: Multiple channels can
5814 * be selected. For example:
5815 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5816 * - groups monitored: not selection possible (monitoring on both
5817 * groups regular and injected).
5818 * Channels selected are monitored on groups regular and injected:
5819 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5820 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5821 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5822 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5823 * the 2 LSB are ignored.
5824 * @note On this STM32 series, setting of this feature is conditioned to
5825 * ADC state:
5826 * ADC must be disabled or enabled without conversion on going
5827 * on either groups regular or injected.
5828 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5829 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5830 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5831 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5832 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5833 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5834 * @param ADCx ADC instance
5835 * @param AWDy This parameter can be one of the following values:
5836 * @arg @ref LL_ADC_AWD1
5837 * @arg @ref LL_ADC_AWD2 (1)
5838 * @arg @ref LL_ADC_AWD3 (1)
5839 *
5840 * (1) On this AWD number, monitored channel can be retrieved
5841 * if only 1 channel is programmed (or none or all channels).
5842 * This function cannot retrieve monitored channel if
5843 * multiple channels are programmed simultaneously
5844 * by bitfield.
5845 * @retval Returned value can be one of the following values:
5846 * @arg @ref LL_ADC_AWD_DISABLE
5847 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5848 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5849 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5850 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5851 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5852 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5853 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5854 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5855 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5856 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5857 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5858 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5859 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5860 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5861 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5862 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5863 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5864 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5865 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5866 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5867 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5868 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5869 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5870 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5871 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5872 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5873 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5874 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5875 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5876 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5877 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5878 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5879 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5880 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5881 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5882 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5883 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5884 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5885 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5886 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5887 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5888 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5889 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5890 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5891 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5892 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5893 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5894 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5895 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5896 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5897 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5898 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5899 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5900 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5901 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5902 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5903 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5904 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5905 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5906 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5907 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5908 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5909 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5910 *
5911 * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.
5912 */
5913__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
5914{
5915 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5916 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5917
5918 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5919
5920 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5921 /* (parameter value LL_ADC_AWD_DISABLE). */
5922 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5923 /* or a single channel. */
5924 if (AnalogWDMonitChannels != 0UL)
5925 {
5926 if (AWDy == LL_ADC_AWD1)
5927 {
5928 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5929 {
5930 /* AWD monitoring a group of channels */
5931 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5932 | (ADC_AWD_CR23_CHANNEL_MASK)
5933 )
5934 & (~(ADC_CFGR_AWD1CH))
5935 );
5936 }
5937 else
5938 {
5939 /* AWD monitoring a single channel */
5940 AnalogWDMonitChannels = (AnalogWDMonitChannels
5941 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5942 );
5943 }
5944 }
5945 else
5946 {
5947 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5948 {
5949 /* AWD monitoring a group of channels */
5950 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5951 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5952 );
5953 }
5954 else
5955 {
5956 /* AWD monitoring a single channel */
5957 /* AWD monitoring a group of channels */
5958 AnalogWDMonitChannels = (AnalogWDMonitChannels
5959 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5960 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5961 );
5962 }
5963 }
5964 }
5965
5966 return AnalogWDMonitChannels;
5967}
5968
5969/**
5970 * @brief Set ADC analog watchdog threshold value of threshold
5971 * high or low.
5972 * @note In case of ADC resolution different of 12 bits,
5973 * analog watchdog thresholds data require a specific shift.
5974 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5975 * @note On this STM32 series, there are 2 kinds of analog watchdog
5976 * instance:
5977 * - AWD standard (instance AWD1):
5978 * - channels monitored: can monitor 1 channel or all channels.
5979 * - groups monitored: ADC groups regular and-or injected.
5980 * - resolution: resolution is not limited (corresponds to
5981 * ADC resolution configured).
5982 * - AWD flexible (instances AWD2, AWD3):
5983 * - channels monitored: flexible on channels monitored, selection is
5984 * channel wise, from from 1 to all channels.
5985 * Specificity of this analog watchdog: Multiple channels can
5986 * be selected. For example:
5987 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5988 * - groups monitored: not selection possible (monitoring on both
5989 * groups regular and injected).
5990 * Channels selected are monitored on groups regular and injected:
5991 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5992 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5993 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5994 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5995 * the 2 LSB are ignored.
5996 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5997 * impacted: the comparison of analog watchdog thresholds is done
5998 * on oversampling intermediate computation (after ratio, before shift
5999 * application): intermediate register bitfield [32:7]
6000 * (26 most significant bits).
6001 * @note On this STM32 series, setting of this feature is conditioned to
6002 * ADC state:
6003 * ADC must be disabled or enabled without conversion on going
6004 * on either ADC groups regular or injected.
6005 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
6006 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
6007 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
6008 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
6009 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
6010 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
6011 * @param ADCx ADC instance
6012 * @param AWDy This parameter can be one of the following values:
6013 * @arg @ref LL_ADC_AWD1
6014 * @arg @ref LL_ADC_AWD2
6015 * @arg @ref LL_ADC_AWD3
6016 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6017 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6018 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6019 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
6020 * @retval None
6021 */
6022__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
6023{
6024#if defined(ADC_VER_V5_V90)
6025 if (ADCx == ADC3)
6026 {
6027 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6028 /* position in register and register position depending on parameters */
6029 /* "AWDThresholdsHighLow" and "AWDy". */
6030 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6031 /* containing other bits reserved for other purpose. */
6032 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6033
6034 MODIFY_REG(*preg,
6035 (ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)),
6036 AWDThresholdValue << (((AWDThresholdsHighLow * ADC3_TR1_HT1) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6037 }
6038 else
6039 {
6040 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6041 /* position in register and register position depending on parameters */
6042 /* "AWDThresholdsHighLow" and "AWDy". */
6043 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6044 /* containing other bits reserved for other purpose. */
6045 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6046 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6047 + (AWDThresholdsHighLow));
6048
6049 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
6050 }
6051#else
6052 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6053 /* position in register and register position depending on parameters */
6054 /* "AWDThresholdsHighLow" and "AWDy". */
6055 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6056 /* containing other bits reserved for other purpose. */
6057 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6058 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6059 + (AWDThresholdsHighLow));
6060
6061 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
6062#endif /* ADC_VER_V5_V90 */
6063}
6064
6065/**
6066 * @brief Get ADC analog watchdog threshold value of threshold high,
6067 * threshold low or raw data with ADC thresholds high and low
6068 * concatenated.
6069 * @note In case of ADC resolution different of 12 bits,
6070 * analog watchdog thresholds data require a specific shift.
6071 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
6072 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
6073 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
6074 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
6075 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
6076 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
6077 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
6078 * @param ADCx ADC instance
6079 * @param AWDy This parameter can be one of the following values:
6080 * @arg @ref LL_ADC_AWD1
6081 * @arg @ref LL_ADC_AWD2
6082 * @arg @ref LL_ADC_AWD3
6083 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6084 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6085 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6086 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
6087*/
6088__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6089{
6090#if defined(ADC_VER_V5_V90)
6091 if (ADCx == ADC3)
6092 {
6093 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
6094 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6095
6096 return (uint32_t)(READ_BIT(*preg,
6097 (ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)))
6098 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
6099 & ~(AWDThresholdsHighLow & ADC3_TR1_LT1)));
6100 }
6101 else
6102 {
6103 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6104 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6105 + (AWDThresholdsHighLow));
6106
6107 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
6108 }
6109#else
6110 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6111 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6112 + (AWDThresholdsHighLow));
6113
6114 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
6115#endif /* ADC_VER_V5_V90 */
6116}
6117
6118#if defined(ADC_VER_V5_V90)
6119
6120/**
6121 * @brief Set ADC analog watchdog thresholds value of both thresholds
6122 * high and low. Applicable for devices STM32H72xx and STM32H73xx.
6123 * @note If value of only one threshold high or low must be set,
6124 * use function @ref LL_ADC_SetAnalogWDThresholds().
6125 * @note In case of ADC resolution different of 12 bits,
6126 * analog watchdog thresholds data require a specific shift.
6127 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6128 * @note On this STM32 series, there are 2 kinds of analog watchdog
6129 * instance:
6130 * - AWD standard (instance AWD1):
6131 * - channels monitored: can monitor 1 channel or all channels.
6132 * - groups monitored: ADC groups regular and-or injected.
6133 * - resolution: resolution is not limited (corresponds to
6134 * ADC resolution configured).
6135 * - AWD flexible (instances AWD2, AWD3):
6136 * - channels monitored: flexible on channels monitored, selection is
6137 * channel wise, from from 1 to all channels.
6138 * Specificity of this analog watchdog: Multiple channels can
6139 * be selected. For example:
6140 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6141 * - groups monitored: not selection possible (monitoring on both
6142 * groups regular and injected).
6143 * Channels selected are monitored on groups regular and injected:
6144 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6145 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6146 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6147 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6148 * the 2 LSB are ignored.
6149 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6150 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6151 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6152 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6153 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6154 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6155 * @param ADCx ADC instance
6156 * @param AWDy This parameter can be one of the following values:
6157 * @arg @ref LL_ADC_AWD1
6158 * @arg @ref LL_ADC_AWD2
6159 * @arg @ref LL_ADC_AWD3
6160 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6161 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6162 * @retval None
6163 */
6164__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
6165{
6166 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6167 /* position in register and register position depending on parameter */
6168 /* "AWDy". */
6169 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6170 /* containing other bits reserved for other purpose. */
6171 if (ADCx == ADC3)
6172 {
6173 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
6174 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6175
6176 MODIFY_REG(*preg,
6177 ADC3_TR1_HT1 | ADC3_TR1_LT1,
6178 (AWDThresholdHighValue << ADC3_TR1_HT1_Pos) | AWDThresholdLowValue);
6179 }
6180 else
6181 {
6182 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6183 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6184 + (LL_ADC_AWD_THRESHOLD_LOW));
6185 __IO uint32_t *preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6186 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6187 + (LL_ADC_AWD_THRESHOLD_HIGH));
6188
6189 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
6190 MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
6191 }
6192}
6193
6194
6195/**
6196 * @brief Set ADC analog watchdog filtering configuration
6197 * @note On this STM32 series, setting of this feature is conditioned to
6198 * ADC state:
6199 * ADC must be disabled or enabled without conversion on going
6200 * on either groups regular or injected.
6201 * Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
6202 * @note On this STM32 series, this feature is only available on first
6203 * analog watchdog (AWD1)
6204 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
6205 * @param ADCx ADC instance
6206 * @param AWDy This parameter can be one of the following values:
6207 * @arg @ref LL_ADC_AWD1
6208 * @param FilteringConfig This parameter can be one of the following values:
6209 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6210 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6211 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6212 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6213 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6214 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6215 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6216 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6217 * @retval None
6218 */
6219__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6220{
6221 if (ADCx == ADC3)
6222 {
6223 /* Prevent unused argument(s) compilation warning */
6224 (void)(AWDy);
6225 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT, FilteringConfig);
6226 }
6227}
6228
6229/**
6230 * @brief Get ADC analog watchdog filtering configuration
6231 * @note On this STM32 series, this feature is only available on first
6232 * analog watchdog (AWD1)
6233 * Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
6234 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
6235 * @param ADCx ADC instance
6236 * @param AWDy This parameter can be one of the following values:
6237 * @arg @ref LL_ADC_AWD1
6238 * @retval Returned value can be:
6239 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6240 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6241 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6242 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6243 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6244 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6245 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6246 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6247 */
6248__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
6249{
6250 if (ADCx == ADC3)
6251 {
6252 /* Prevent unused argument(s) compilation warning */
6253 (void)(AWDy);
6254 return (uint32_t)(READ_BIT(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT));
6255 }
6256 else
6257 {
6258 /* Function not available on this instance, return 0 */
6259 return 0UL;
6260 }
6261}
6262#endif /* ADC_VER_V5_V90 */
6263/**
6264 * @}
6265 */
6266
6267/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6268 * @{
6269 */
6270
6271/**
6272 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6273 * (availability of ADC group injected depends on STM32 families).
6274 * @note If both groups regular and injected are selected,
6275 * specify behavior of ADC group injected interrupting
6276 * group regular: when ADC group injected is triggered,
6277 * the oversampling on ADC group regular is either
6278 * temporary stopped and continued, or resumed from start
6279 * (oversampler buffer reset).
6280 * @note On this STM32 series, setting of this feature is conditioned to
6281 * ADC state:
6282 * ADC must be disabled or enabled without conversion on going
6283 * on either groups regular or injected.
6284 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6285 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6286 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6287 * @param ADCx ADC instance
6288 * @param OvsScope This parameter can be one of the following values:
6289 * @arg @ref LL_ADC_OVS_DISABLE
6290 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6291 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6292 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6293 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6294 * @retval None
6295 */
6296__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6297{
6298 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6299}
6300
6301/**
6302 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6303 * (availability of ADC group injected depends on STM32 families).
6304 * @note If both groups regular and injected are selected,
6305 * specify behavior of ADC group injected interrupting
6306 * group regular: when ADC group injected is triggered,
6307 * the oversampling on ADC group regular is either
6308 * temporary stopped and continued, or resumed from start
6309 * (oversampler buffer reset).
6310 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6311 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6312 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6313 * @param ADCx ADC instance
6314 * @retval Returned value can be one of the following values:
6315 * @arg @ref LL_ADC_OVS_DISABLE
6316 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6317 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6318 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6319 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6320 */
6321__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
6322{
6323 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6324}
6325
6326/**
6327 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6328 * on the selected ADC group.
6329 * @note Number of oversampled conversions are done either in:
6330 * - continuous mode (all conversions of oversampling ratio
6331 * are done from 1 trigger)
6332 * - discontinuous mode (each conversion of oversampling ratio
6333 * needs a trigger)
6334 * @note On this STM32 series, setting of this feature is conditioned to
6335 * ADC state:
6336 * ADC must be disabled or enabled without conversion on going
6337 * on group regular.
6338 * @note On this STM32 series, oversampling discontinuous mode
6339 * (triggered mode) can be used only when oversampling is
6340 * set on group regular only and in resumed mode.
6341 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6342 * @param ADCx ADC instance
6343 * @param OverSamplingDiscont This parameter can be one of the following values:
6344 * @arg @ref LL_ADC_OVS_REG_CONT
6345 * @arg @ref LL_ADC_OVS_REG_DISCONT
6346 * @retval None
6347 */
6348__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6349{
6350 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6351}
6352
6353/**
6354 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6355 * on the selected ADC group.
6356 * @note Number of oversampled conversions are done either in:
6357 * - continuous mode (all conversions of oversampling ratio
6358 * are done from 1 trigger)
6359 * - discontinuous mode (each conversion of oversampling ratio
6360 * needs a trigger)
6361 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6362 * @param ADCx ADC instance
6363 * @retval Returned value can be one of the following values:
6364 * @arg @ref LL_ADC_OVS_REG_CONT
6365 * @arg @ref LL_ADC_OVS_REG_DISCONT
6366 */
6367__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
6368{
6369 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6370}
6371
6372/**
6373 * @brief Set ADC oversampling
6374 * (impacting both ADC groups regular and injected)
6375 * @note This function set the 2 items of oversampling configuration:
6376 * - ratio
6377 * - shift
6378 * @note On this STM32 series, setting of this feature is conditioned to
6379 * ADC state:
6380 * ADC must be disabled or enabled without conversion on going
6381 * on either groups regular or injected.
6382 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6383 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6384 * @param ADCx ADC instance
6385 * @param Ratio This parameter can be in the range from 1 to 1024.
6386 * In the case of ADC3 can be one of the following values:
6387 * @arg @ref LL_ADC_OVS_RATIO_2
6388 * @arg @ref LL_ADC_OVS_RATIO_4
6389 * @arg @ref LL_ADC_OVS_RATIO_8
6390 * @arg @ref LL_ADC_OVS_RATIO_16
6391 * @arg @ref LL_ADC_OVS_RATIO_32
6392 * @arg @ref LL_ADC_OVS_RATIO_64
6393 * @arg @ref LL_ADC_OVS_RATIO_128
6394 * @arg @ref LL_ADC_OVS_RATIO_256
6395 * @param Shift This parameter can be one of the following values:
6396 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6397 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6398 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6399 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6400 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6401 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6402 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6403 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6404 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6405 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
6406 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
6407 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
6408 * @retval None
6409 */
6410__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6411{
6412#if defined(ADC_VER_V5_V90)
6413 if(ADCx==ADC3)
6414 {
6415 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC3_CFGR2_OVSR), (Shift | Ratio));
6416 }
6417 else
6418 {
6419 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6420 }
6421#else
6422
6423 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6424
6425#endif /* ADC_VER_V5_V90 */
6426}
6427
6428/**
6429 * @brief Get ADC oversampling ratio
6430 * (impacting both ADC groups regular and injected)
6431 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6432 * @param ADCx ADC instance
6433 * @retval Ratio This parameter can be in the from 1 to 1024.
6434 * In the case of ADC3 can be one of the following values:
6435 * @arg @ref LL_ADC_OVS_RATIO_2
6436 * @arg @ref LL_ADC_OVS_RATIO_4
6437 * @arg @ref LL_ADC_OVS_RATIO_8
6438 * @arg @ref LL_ADC_OVS_RATIO_16
6439 * @arg @ref LL_ADC_OVS_RATIO_32
6440 * @arg @ref LL_ADC_OVS_RATIO_64
6441 * @arg @ref LL_ADC_OVS_RATIO_128
6442 * @arg @ref LL_ADC_OVS_RATIO_256
6443*/
6444__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
6445{
6446#if defined(ADC_VER_V5_V90)
6447 if(ADCx==ADC3)
6448 {
6449 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC3_CFGR2_OVSR));
6450 }
6451 else
6452 {
6453 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6454 }
6455#else
6456
6457 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6458
6459#endif /* ADC_VER_V5_V90 */
6460}
6461
6462/**
6463 * @brief Get ADC oversampling shift
6464 * (impacting both ADC groups regular and injected)
6465 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6466 * @param ADCx ADC instance
6467 * @retval Shift This parameter can be one of the following values:
6468 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6469 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6470 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6471 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6472 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6473 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6474 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6475 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6476 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6477 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
6478 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
6479 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
6480*/
6481__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
6482{
6483 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6484}
6485
6486/**
6487 * @}
6488 */
6489
6490/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6491 * @{
6492 */
6493/**
6494 * @brief Set ADC boost mode.
6495 * @note On this STM32 series, setting of this feature is conditioned to
6496 * ADC state:
6497 * ADC boost must be configured, without calibration on going, without conversion
6498 * on going on group regular.
6499 * @rmtoll CR BOOST LL_ADC_SetBoostMode
6500 * @param ADCx ADC instance
6501 * @param BoostMode This parameter can be one of the following values:
6502 * @arg @ref LL_ADC_BOOST_MODE_6MHZ25
6503 * @arg @ref LL_ADC_BOOST_MODE_12MHZ5
6504 * @arg @ref LL_ADC_BOOST_MODE_20MHZ
6505 * @arg @ref LL_ADC_BOOST_MODE_25MHZ
6506 * @arg @ref LL_ADC_BOOST_MODE_50MHZ
6507 * @retval None
6508 */
6509__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
6510{
6511#if defined(ADC_VER_V5_V90)
6512 if (ADCx != ADC3)
6513 {
6514 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6515 }
6516#else /* ADC_VER_V5_V90 */
6517 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6518 {
6519 MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
6520 }
6521 else /* Cut 2.x */
6522 {
6523 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6524 }
6525#endif /* ADC_VER_V5_V90 */
6526}
6527
6528
6529/**
6530 * @brief Get ADC boost mode.
6531 * @note On this STM32 series, setting of this feature is conditioned to
6532 * ADC state:
6533 * ADC boost must be configured, without calibration on going, without conversion
6534 * on going on group regular.
6535 * @rmtoll CR BOOST LL_ADC_GetBoostMode
6536 * @param ADCx ADC instance
6537 * @retval 0: Boost disabled 1: Boost enabled
6538 */
6539__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(const ADC_TypeDef *ADCx)
6540{
6541 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6542 {
6543 return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
6544 }
6545 else /* Cut 2.x */
6546 {
6547 return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);
6548 }
6549}
6550
6551/**
6552 * @brief Set ADC multimode configuration to operate in independent mode
6553 * or multimode (for devices with several ADC instances).
6554 * @note If multimode configuration: the selected ADC instance is
6555 * either master or slave depending on hardware.
6556 * Refer to reference manual.
6557 * @note On this STM32 series, setting of this feature is conditioned to
6558 * ADC state:
6559 * All ADC instances of the ADC common group must be disabled.
6560 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6561 * ADC instance or by using helper macro
6562 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6563 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6564 * @param ADCxy_COMMON ADC common instance
6565 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6566 * @param Multimode This parameter can be one of the following values:
6567 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6568 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6569 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6570 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6571 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6572 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6573 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6574 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6575 * @retval None
6576 */
6577__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6578{
6579 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6580}
6581
6582/**
6583 * @brief Get ADC multimode configuration to operate in independent mode
6584 * or multimode (for devices with several ADC instances).
6585 * @note If multimode configuration: the selected ADC instance is
6586 * either master or slave depending on hardware.
6587 * Refer to reference manual.
6588 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6589 * @param ADCxy_COMMON ADC common instance
6590 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6591 * @retval Returned value can be one of the following values:
6592 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6593 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6594 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6595 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6596 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6597 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6598 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6599 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6600 */
6601__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
6602{
6603 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6604}
6605
6606/**
6607 * @brief Set ADC multimode conversion data transfer: no transfer
6608 * or transfer by DMA.
6609 * @note If ADC multimode transfer by DMA is not selected:
6610 * each ADC uses its own DMA channel, with its individual
6611 * DMA transfer settings.
6612 * If ADC multimode transfer by DMA is selected:
6613 * One DMA channel is used for both ADC (DMA of ADC master)
6614 * Specifies the DMA requests mode:
6615 * - Limited mode (One shot mode): DMA transfer requests are stopped
6616 * when number of DMA data transfers (number of
6617 * ADC conversions) is reached.
6618 * This ADC mode is intended to be used with DMA mode non-circular.
6619 * - Unlimited mode: DMA transfer requests are unlimited,
6620 * whatever number of DMA data transfers (number of
6621 * ADC conversions).
6622 * This ADC mode is intended to be used with DMA mode circular.
6623 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6624 * mode non-circular:
6625 * when DMA transfers size will be reached, DMA will stop transfers of
6626 * ADC conversions data ADC will raise an overrun error
6627 * (overrun flag and interruption if enabled).
6628 * @note How to retrieve multimode conversion data:
6629 * Whatever multimode transfer by DMA setting: using function
6630 * @ref LL_ADC_REG_ReadMultiConversionData32().
6631 * If ADC multimode transfer by DMA is selected: conversion data
6632 * is a raw data with ADC master and slave concatenated.
6633 * A macro is available to get the conversion data of
6634 * ADC master or ADC slave: see helper macro
6635 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6636 * @note On this STM32 series, setting of this feature is conditioned to
6637 * ADC state:
6638 * All ADC instances of the ADC common group must be disabled
6639 * or enabled without conversion on going on group regular.
6640 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
6641 * @param ADCxy_COMMON ADC common instance
6642 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6643 * @param MultiDMATransfer This parameter can be one of the following values:
6644 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6645 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
6646 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
6647 * @retval None
6648 */
6649__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6650{
6651 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
6652}
6653
6654/**
6655 * @brief Get ADC multimode conversion data transfer: no transfer
6656 * or transfer by DMA.
6657 * @note If ADC multimode transfer by DMA is not selected:
6658 * each ADC uses its own DMA channel, with its individual
6659 * DMA transfer settings.
6660 * If ADC multimode transfer by DMA is selected:
6661 * One DMA channel is used for both ADC (DMA of ADC master)
6662 * Specifies the DMA requests mode:
6663 * - Limited mode (One shot mode): DMA transfer requests are stopped
6664 * when number of DMA data transfers (number of
6665 * ADC conversions) is reached.
6666 * This ADC mode is intended to be used with DMA mode non-circular.
6667 * - Unlimited mode: DMA transfer requests are unlimited,
6668 * whatever number of DMA data transfers (number of
6669 * ADC conversions).
6670 * This ADC mode is intended to be used with DMA mode circular.
6671 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6672 * mode non-circular:
6673 * when DMA transfers size will be reached, DMA will stop transfers of
6674 * ADC conversions data ADC will raise an overrun error
6675 * (overrun flag and interruption if enabled).
6676 * @note How to retrieve multimode conversion data:
6677 * Whatever multimode transfer by DMA setting: using function
6678 * @ref LL_ADC_REG_ReadMultiConversionData32().
6679 * If ADC multimode transfer by DMA is selected: conversion data
6680 * is a raw data with ADC master and slave concatenated.
6681 * A macro is available to get the conversion data of
6682 * ADC master or ADC slave: see helper macro
6683 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6684 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
6685 * @param ADCxy_COMMON ADC common instance
6686 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6687 * @retval Returned value can be one of the following values:
6688 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6689 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
6690 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
6691 */
6692__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
6693{
6694 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
6695}
6696
6697/**
6698 * @brief Set ADC multimode delay between 2 sampling phases.
6699 * @note The sampling delay range depends on ADC resolution:
6700 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6701 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6702 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6703 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6704 * @note On this STM32 series, setting of this feature is conditioned to
6705 * ADC state:
6706 * All ADC instances of the ADC common group must be disabled.
6707 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6708 * ADC instance or by using helper macro helper macro
6709 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6710 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6711 * @param ADCxy_COMMON ADC common instance
6712 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6713 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
6715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
6716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
6717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
6718 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
6719 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
6720 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
6721 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
6722 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
6723 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
6724 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
6725 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
6726 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
6727 *
6728 * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
6729 * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
6730 * (3) Parameter available only if ADC resolution is 10 or 8 bits.
6731 * (4) Parameter available only if ADC resolution is 16 or 14 bits.
6732 * (5) Parameter available only if ADC resolution is 16 bits.
6733 * (6) Parameter available only if ADC resolution is 12 bits.
6734 * (7) Parameter available only if ADC resolution is 16 or 14 bits.
6735 * @retval None
6736 */
6737__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6738{
6739 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6740}
6741
6742/**
6743 * @brief Get ADC multimode delay between 2 sampling phases.
6744 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6745 * @param ADCxy_COMMON ADC common instance
6746 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6747 * @retval Returned value can be one of the following values:
6748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
6749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
6750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
6751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
6752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
6753 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
6754 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
6755 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
6756 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
6757 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
6758 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
6759 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
6760 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
6761 *
6762 * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
6763 * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
6764 * (3) Parameter available only if ADC resolution is 10 or 8 bits.
6765 * (4) Parameter available only if ADC resolution is 16 or 14 bits.
6766 * (5) Parameter available only if ADC resolution is 16 bits.
6767 * (6) Parameter available only if ADC resolution is 12 bits.
6768 * (7) Parameter available only if ADC resolution is 16 or 14 bits.
6769 */
6770__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
6771{
6772 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6773}
6774
6775/**
6776 * @}
6777 */
6778/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6779 * @{
6780 */
6781
6782/**
6783 * @brief Put ADC instance in deep power down state.
6784 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6785 * state, the internal analog calibration is lost. After exiting from
6786 * deep power down, calibration must be relaunched or calibration factor
6787 * (preliminarily saved) must be set back into calibration register.
6788 * @note On this STM32 series, setting of this feature is conditioned to
6789 * ADC state:
6790 * ADC must be ADC disabled.
6791 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6792 * @param ADCx ADC instance
6793 * @retval None
6794 */
6795__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6796{
6797 /* Note: Write register with some additional bits forced to state reset */
6798 /* instead of modifying only the selected bit for this function, */
6799 /* to not interfere with bits with HW property "rs". */
6800 MODIFY_REG(ADCx->CR,
6801 ADC_CR_BITS_PROPERTY_RS,
6802 ADC_CR_DEEPPWD);
6803}
6804
6805/**
6806 * @brief Disable ADC deep power down mode.
6807 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6808 * state, the internal analog calibration is lost. After exiting from
6809 * deep power down, calibration must be relaunched or calibration factor
6810 * (preliminarily saved) must be set back into calibration register.
6811 * @note On this STM32 series, setting of this feature is conditioned to
6812 * ADC state:
6813 * ADC must be ADC disabled.
6814 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6815 * @param ADCx ADC instance
6816 * @retval None
6817 */
6818__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6819{
6820 /* Note: Write register with some additional bits forced to state reset */
6821 /* instead of modifying only the selected bit for this function, */
6822 /* to not interfere with bits with HW property "rs". */
6823 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6824}
6825
6826/**
6827 * @brief Get the selected ADC instance deep power down state.
6828 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6829 * @param ADCx ADC instance
6830 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6831 */
6832__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6833{
6834 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6835}
6836
6837/**
6838 * @brief Enable ADC instance internal voltage regulator.
6839 * @note On this STM32 series, after ADC internal voltage regulator enable,
6840 * a delay for ADC internal voltage regulator stabilization
6841 * is required before performing a ADC calibration or ADC enable.
6842 * Refer to device datasheet, parameter tADCVREG_STUP.
6843 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6844 * @note On this STM32 series, setting of this feature is conditioned to
6845 * ADC state:
6846 * ADC must be ADC disabled.
6847 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6848 * @param ADCx ADC instance
6849 * @retval None
6850 */
6851__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6852{
6853 /* Note: Write register with some additional bits forced to state reset */
6854 /* instead of modifying only the selected bit for this function, */
6855 /* to not interfere with bits with HW property "rs". */
6856 MODIFY_REG(ADCx->CR,
6857 ADC_CR_BITS_PROPERTY_RS,
6858 ADC_CR_ADVREGEN);
6859}
6860
6861/**
6862 * @brief Disable ADC internal voltage regulator.
6863 * @note On this STM32 series, setting of this feature is conditioned to
6864 * ADC state:
6865 * ADC must be ADC disabled.
6866 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6867 * @param ADCx ADC instance
6868 * @retval None
6869 */
6870__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6871{
6872 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6873}
6874
6875/**
6876 * @brief Get the selected ADC instance internal voltage regulator state.
6877 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6878 * @param ADCx ADC instance
6879 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6880 */
6881__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
6882{
6883 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6884}
6885
6886/**
6887 * @brief Enable the selected ADC instance.
6888 * @note On this STM32 series, after ADC enable, a delay for
6889 * ADC internal analog stabilization is required before performing a
6890 * ADC conversion start.
6891 * Refer to device datasheet, parameter tSTAB.
6892 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6893 * is enabled and when conversion clock is active.
6894 * (not only core clock: this ADC has a dual clock domain)
6895 * @note On this STM32 series, setting of this feature is conditioned to
6896 * ADC state:
6897 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6898 * @rmtoll CR ADEN LL_ADC_Enable
6899 * @param ADCx ADC instance
6900 * @retval None
6901 */
6902__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6903{
6904 /* Note: Write register with some additional bits forced to state reset */
6905 /* instead of modifying only the selected bit for this function, */
6906 /* to not interfere with bits with HW property "rs". */
6907 MODIFY_REG(ADCx->CR,
6908 ADC_CR_BITS_PROPERTY_RS,
6909 ADC_CR_ADEN);
6910}
6911
6912/**
6913 * @brief Disable the selected ADC instance.
6914 * @note On this STM32 series, setting of this feature is conditioned to
6915 * ADC state:
6916 * ADC must be not disabled. Must be enabled without conversion on going
6917 * on either groups regular or injected.
6918 * @rmtoll CR ADDIS LL_ADC_Disable
6919 * @param ADCx ADC instance
6920 * @retval None
6921 */
6922__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6923{
6924 /* Note: Write register with some additional bits forced to state reset */
6925 /* instead of modifying only the selected bit for this function, */
6926 /* to not interfere with bits with HW property "rs". */
6927 MODIFY_REG(ADCx->CR,
6928 ADC_CR_BITS_PROPERTY_RS,
6929 ADC_CR_ADDIS);
6930}
6931
6932/**
6933 * @brief Get the selected ADC instance enable state.
6934 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6935 * is enabled and when conversion clock is active.
6936 * (not only core clock: this ADC has a dual clock domain)
6937 * @rmtoll CR ADEN LL_ADC_IsEnabled
6938 * @param ADCx ADC instance
6939 * @retval 0: ADC is disabled, 1: ADC is enabled.
6940 */
6941__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6942{
6943 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6944}
6945
6946/**
6947 * @brief Get the selected ADC instance disable state.
6948 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6949 * @param ADCx ADC instance
6950 * @retval 0: no ADC disable command on going.
6951 */
6952__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6953{
6954 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6955}
6956
6957/**
6958 * @brief Start ADC calibration in the mode single-ended
6959 * or differential (for devices with differential mode available).
6960 * @note On this STM32 series, a minimum number of ADC clock cycles
6961 * are required between ADC end of calibration and ADC enable.
6962 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6963 * @note Calibration duration:
6964 * - Calibration of offset: 520 ADC clock cycles
6965 * - Calibration of linearity: 131072 ADC clock cycles
6966 * @note For devices with differential mode available:
6967 * Calibration of offset is specific to each of
6968 * single-ended and differential modes
6969 * (calibration run must be performed for each of these
6970 * differential modes, if used afterwards and if the application
6971 * requires their calibration).
6972 * Calibration of linearity is common to both
6973 * single-ended and differential modes
6974 * (calibration run can be performed only once).
6975 * @note On this STM32 series, setting of this feature is conditioned to
6976 * ADC state:
6977 * ADC must be ADC disabled.
6978 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6979 * CR ADCALDIF LL_ADC_StartCalibration\n
6980 * CR ADCALLIN LL_ADC_StartCalibration
6981 * @param ADCx ADC instance
6982 * @param CalibrationMode This parameter can be one of the following values:
6983 * @arg @ref LL_ADC_CALIB_OFFSET
6984 * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
6985 * @param SingleDiff This parameter can be one of the following values:
6986 * @arg @ref LL_ADC_SINGLE_ENDED
6987 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6988 * @retval None
6989 */
6990__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
6991{
6992 /* Note: Write register with some additional bits forced to state reset */
6993 /* instead of modifying only the selected bit for this function, */
6994 /* to not interfere with bits with HW property "rs". */
6995 MODIFY_REG(ADCx->CR,
6996 ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6997 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6998}
6999
7000/**
7001 * @brief Get ADC calibration state.
7002 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
7003 * @param ADCx ADC instance
7004 * @retval 0: calibration complete, 1: calibration in progress.
7005 */
7006__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
7007{
7008 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
7009}
7010
7011/**
7012 * @}
7013 */
7014
7015/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
7016 * @{
7017 */
7018
7019/**
7020 * @brief Start ADC group regular conversion.
7021 * @note On this STM32 series, this function is relevant for both
7022 * internal trigger (SW start) and external trigger:
7023 * - If ADC trigger has been set to software start, ADC conversion
7024 * starts immediately.
7025 * - If ADC trigger has been set to external trigger, ADC conversion
7026 * will start at next trigger event (on the selected trigger edge)
7027 * following the ADC start conversion command.
7028 * @note On this STM32 series, setting of this feature is conditioned to
7029 * ADC state:
7030 * ADC must be enabled without conversion on going on group regular,
7031 * without conversion stop command on going on group regular,
7032 * without ADC disable command on going.
7033 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
7034 * @param ADCx ADC instance
7035 * @retval None
7036 */
7037__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
7038{
7039 /* Note: Write register with some additional bits forced to state reset */
7040 /* instead of modifying only the selected bit for this function, */
7041 /* to not interfere with bits with HW property "rs". */
7042 MODIFY_REG(ADCx->CR,
7043 ADC_CR_BITS_PROPERTY_RS,
7044 ADC_CR_ADSTART);
7045}
7046
7047/**
7048 * @brief Stop ADC group regular conversion.
7049 * @note On this STM32 series, setting of this feature is conditioned to
7050 * ADC state:
7051 * ADC must be enabled with conversion on going on group regular,
7052 * without ADC disable command on going.
7053 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
7054 * @param ADCx ADC instance
7055 * @retval None
7056 */
7057__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
7058{
7059 /* Note: Write register with some additional bits forced to state reset */
7060 /* instead of modifying only the selected bit for this function, */
7061 /* to not interfere with bits with HW property "rs". */
7062 MODIFY_REG(ADCx->CR,
7063 ADC_CR_BITS_PROPERTY_RS,
7064 ADC_CR_ADSTP);
7065}
7066
7067/**
7068 * @brief Get ADC group regular conversion state.
7069 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
7070 * @param ADCx ADC instance
7071 * @retval 0: no conversion is on going on ADC group regular.
7072 */
7073__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
7074{
7075 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
7076}
7077
7078/**
7079 * @brief Get ADC group regular command of conversion stop state
7080 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
7081 * @param ADCx ADC instance
7082 * @retval 0: no command of conversion stop is on going on ADC group regular.
7083 */
7084__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7085{
7086 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
7087}
7088
7089/**
7090 * @brief Get ADC group regular conversion data, range fit for
7091 * all ADC configurations: all ADC resolutions and
7092 * all oversampling increased data width (for devices
7093 * with feature oversampling).
7094 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
7095 * @param ADCx ADC instance
7096 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7097 */
7098__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
7099{
7100 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7101}
7102
7103/**
7104 * @brief Get ADC group regular conversion data, range fit for
7105 * ADC resolution 16 bits.
7106 * @note For devices with feature oversampling: Oversampling
7107 * can increase data width, function for extended range
7108 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7109 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
7110 * @param ADCx ADC instance
7111 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
7112 */
7113__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx)
7114{
7115 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7116}
7117
7118/**
7119 * @brief Get ADC group regular conversion data, range fit for
7120 * ADC resolution 14 bits.
7121 * @note For devices with feature oversampling: Oversampling
7122 * can increase data width, function for extended range
7123 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7124 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
7125 * @param ADCx ADC instance
7126 * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
7127 */
7128__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx)
7129{
7130 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7131}
7132
7133/**
7134 * @brief Get ADC group regular conversion data, range fit for
7135 * ADC resolution 12 bits.
7136 * @note For devices with feature oversampling: Oversampling
7137 * can increase data width, function for extended range
7138 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7139 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
7140 * @param ADCx ADC instance
7141 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7142 */
7143__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
7144{
7145 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7146}
7147
7148/**
7149 * @brief Get ADC group regular conversion data, range fit for
7150 * ADC resolution 10 bits.
7151 * @note For devices with feature oversampling: Oversampling
7152 * can increase data width, function for extended range
7153 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7154 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
7155 * @param ADCx ADC instance
7156 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7157 */
7158__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
7159{
7160 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7161}
7162
7163/**
7164 * @brief Get ADC group regular conversion data, range fit for
7165 * ADC resolution 8 bits.
7166 * @note For devices with feature oversampling: Oversampling
7167 * can increase data width, function for extended range
7168 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7169 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
7170 * @param ADCx ADC instance
7171 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7172 */
7173__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
7174{
7175 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7176}
7177/**
7178 * @brief Get ADC multimode conversion data of ADC master, ADC slave
7179 * or raw data with ADC master and slave concatenated.
7180 * @note If raw data with ADC master and slave concatenated is retrieved,
7181 * a macro is available to get the conversion data of
7182 * ADC master or ADC slave: see helper macro
7183 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7184 * (however this macro is mainly intended for multimode
7185 * transfer by DMA, because this function can do the same
7186 * by getting multimode conversion data of ADC master or ADC slave
7187 * separately).
7188 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
7189 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
7190 * @param ADCxy_COMMON ADC common instance
7191 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7192 * @param ConversionData This parameter can be one of the following values:
7193 * @arg @ref LL_ADC_MULTI_MASTER
7194 * @arg @ref LL_ADC_MULTI_SLAVE
7195 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
7196 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7197 */
7198__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
7199{
7200 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7201 ConversionData)
7202 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7203 );
7204}
7205
7206/**
7207 * @}
7208 */
7209
7210/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
7211 * @{
7212 */
7213
7214/**
7215 * @brief Start ADC group injected conversion.
7216 * @note On this STM32 series, this function is relevant for both
7217 * internal trigger (SW start) and external trigger:
7218 * - If ADC trigger has been set to software start, ADC conversion
7219 * starts immediately.
7220 * - If ADC trigger has been set to external trigger, ADC conversion
7221 * will start at next trigger event (on the selected trigger edge)
7222 * following the ADC start conversion command.
7223 * @note On this STM32 series, setting of this feature is conditioned to
7224 * ADC state:
7225 * ADC must be enabled without conversion on going on group injected,
7226 * without conversion stop command on going on group injected,
7227 * without ADC disable command on going.
7228 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
7229 * @param ADCx ADC instance
7230 * @retval None
7231 */
7232__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7233{
7234 /* Note: Write register with some additional bits forced to state reset */
7235 /* instead of modifying only the selected bit for this function, */
7236 /* to not interfere with bits with HW property "rs". */
7237 MODIFY_REG(ADCx->CR,
7238 ADC_CR_BITS_PROPERTY_RS,
7239 ADC_CR_JADSTART);
7240}
7241
7242/**
7243 * @brief Stop ADC group injected conversion.
7244 * @note On this STM32 series, setting of this feature is conditioned to
7245 * ADC state:
7246 * ADC must be enabled with conversion on going on group injected,
7247 * without ADC disable command on going.
7248 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
7249 * @param ADCx ADC instance
7250 * @retval None
7251 */
7252__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7253{
7254 /* Note: Write register with some additional bits forced to state reset */
7255 /* instead of modifying only the selected bit for this function, */
7256 /* to not interfere with bits with HW property "rs". */
7257 MODIFY_REG(ADCx->CR,
7258 ADC_CR_BITS_PROPERTY_RS,
7259 ADC_CR_JADSTP);
7260}
7261
7262/**
7263 * @brief Get ADC group injected conversion state.
7264 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7265 * @param ADCx ADC instance
7266 * @retval 0: no conversion is on going on ADC group injected.
7267 */
7268__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
7269{
7270 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7271}
7272
7273/**
7274 * @brief Get ADC group injected command of conversion stop state
7275 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7276 * @param ADCx ADC instance
7277 * @retval 0: no command of conversion stop is on going on ADC group injected.
7278 */
7279__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7280{
7281 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7282}
7283
7284/**
7285 * @brief Get ADC group injected conversion data, range fit for
7286 * all ADC configurations: all ADC resolutions and
7287 * all oversampling increased data width (for devices
7288 * with feature oversampling).
7289 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7290 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7291 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7292 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7293 * @param ADCx ADC instance
7294 * @param Rank This parameter can be one of the following values:
7295 * @arg @ref LL_ADC_INJ_RANK_1
7296 * @arg @ref LL_ADC_INJ_RANK_2
7297 * @arg @ref LL_ADC_INJ_RANK_3
7298 * @arg @ref LL_ADC_INJ_RANK_4
7299 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7300 */
7301__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
7302{
7303 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7304
7305 return (uint32_t)(READ_BIT(*preg,
7306 ADC_JDR1_JDATA)
7307 );
7308}
7309
7310/**
7311 * @brief Get ADC group injected conversion data, range fit for
7312 * ADC resolution 16 bits.
7313 * @note For devices with feature oversampling: Oversampling
7314 * can increase data width, function for extended range
7315 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7316 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n
7317 * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n
7318 * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n
7319 * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
7320 * @param ADCx ADC instance
7321 * @param Rank This parameter can be one of the following values:
7322 * @arg @ref LL_ADC_INJ_RANK_1
7323 * @arg @ref LL_ADC_INJ_RANK_2
7324 * @arg @ref LL_ADC_INJ_RANK_3
7325 * @arg @ref LL_ADC_INJ_RANK_4
7326 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
7327 */
7328__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank)
7329{
7330 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7331
7332 return (uint16_t)(READ_BIT(*preg,
7333 ADC_JDR1_JDATA)
7334 );
7335}
7336
7337/**
7338 * @brief Get ADC group injected conversion data, range fit for
7339 * ADC resolution 14 bits.
7340 * @note For devices with feature oversampling: Oversampling
7341 * can increase data width, function for extended range
7342 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7343 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n
7344 * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n
7345 * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n
7346 * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
7347 * @param ADCx ADC instance
7348 * @param Rank This parameter can be one of the following values:
7349 * @arg @ref LL_ADC_INJ_RANK_1
7350 * @arg @ref LL_ADC_INJ_RANK_2
7351 * @arg @ref LL_ADC_INJ_RANK_3
7352 * @arg @ref LL_ADC_INJ_RANK_4
7353 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
7354 */
7355__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank)
7356{
7357 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7358
7359 return (uint16_t)(READ_BIT(*preg,
7360 ADC_JDR1_JDATA)
7361 );
7362}
7363
7364/**
7365 * @brief Get ADC group injected conversion data, range fit for
7366 * ADC resolution 12 bits.
7367 * @note For devices with feature oversampling: Oversampling
7368 * can increase data width, function for extended range
7369 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7370 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7371 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7372 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7373 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7374 * @param ADCx ADC instance
7375 * @param Rank This parameter can be one of the following values:
7376 * @arg @ref LL_ADC_INJ_RANK_1
7377 * @arg @ref LL_ADC_INJ_RANK_2
7378 * @arg @ref LL_ADC_INJ_RANK_3
7379 * @arg @ref LL_ADC_INJ_RANK_4
7380 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7381 */
7382__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
7383{
7384 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7385
7386 return (uint16_t)(READ_BIT(*preg,
7387 ADC_JDR1_JDATA)
7388 );
7389}
7390
7391/**
7392 * @brief Get ADC group injected conversion data, range fit for
7393 * ADC resolution 10 bits.
7394 * @note For devices with feature oversampling: Oversampling
7395 * can increase data width, function for extended range
7396 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7397 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7398 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7399 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7400 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7401 * @param ADCx ADC instance
7402 * @param Rank This parameter can be one of the following values:
7403 * @arg @ref LL_ADC_INJ_RANK_1
7404 * @arg @ref LL_ADC_INJ_RANK_2
7405 * @arg @ref LL_ADC_INJ_RANK_3
7406 * @arg @ref LL_ADC_INJ_RANK_4
7407 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7408 */
7409__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
7410{
7411 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7412
7413 return (uint16_t)(READ_BIT(*preg,
7414 ADC_JDR1_JDATA)
7415 );
7416}
7417
7418/**
7419 * @brief Get ADC group injected conversion data, range fit for
7420 * ADC resolution 8 bits.
7421 * @note For devices with feature oversampling: Oversampling
7422 * can increase data width, function for extended range
7423 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7424 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7425 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7426 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7427 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7428 * @param ADCx ADC instance
7429 * @param Rank This parameter can be one of the following values:
7430 * @arg @ref LL_ADC_INJ_RANK_1
7431 * @arg @ref LL_ADC_INJ_RANK_2
7432 * @arg @ref LL_ADC_INJ_RANK_3
7433 * @arg @ref LL_ADC_INJ_RANK_4
7434 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7435 */
7436__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
7437{
7438 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7439
7440 return (uint8_t)(READ_BIT(*preg,
7441 ADC_JDR1_JDATA)
7442 );
7443}
7444
7445/**
7446 * @}
7447 */
7448
7449/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7450 * @{
7451 */
7452
7453/**
7454 * @brief Get flag ADC ready.
7455 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7456 * is enabled and when conversion clock is active.
7457 * (not only core clock: this ADC has a dual clock domain)
7458 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7459 * @param ADCx ADC instance
7460 * @retval State of bit (1 or 0).
7461 */
7462__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
7463{
7464 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7465}
7466
7467/**
7468 * @brief Get flag ADC group regular end of unitary conversion.
7469 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7470 * @param ADCx ADC instance
7471 * @retval State of bit (1 or 0).
7472 */
7473__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
7474{
7475 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7476}
7477
7478/**
7479 * @brief Get flag ADC group regular end of sequence conversions.
7480 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7481 * @param ADCx ADC instance
7482 * @retval State of bit (1 or 0).
7483 */
7484__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
7485{
7486 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7487}
7488
7489/**
7490 * @brief Get flag ADC group regular overrun.
7491 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7492 * @param ADCx ADC instance
7493 * @retval State of bit (1 or 0).
7494 */
7495__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
7496{
7497 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7498}
7499
7500/**
7501 * @brief Get flag ADC group regular end of sampling phase.
7502 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7503 * @param ADCx ADC instance
7504 * @retval State of bit (1 or 0).
7505 */
7506__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
7507{
7508 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7509}
7510
7511/**
7512 * @brief Get flag ADC group injected end of unitary conversion.
7513 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7514 * @param ADCx ADC instance
7515 * @retval State of bit (1 or 0).
7516 */
7517__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
7518{
7519 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7520}
7521
7522/**
7523 * @brief Get flag ADC group injected end of sequence conversions.
7524 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7525 * @param ADCx ADC instance
7526 * @retval State of bit (1 or 0).
7527 */
7528__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
7529{
7530 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7531}
7532
7533/**
7534 * @brief Get flag ADC group injected contexts queue overflow.
7535 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7536 * @param ADCx ADC instance
7537 * @retval State of bit (1 or 0).
7538 */
7539__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
7540{
7541 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7542}
7543
7544/**
7545 * @brief Get flag ADC LDO output voltage ready bit.
7546 * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY
7547 * @param ADCx ADC instance
7548 * @retval State of bit (1 or 0).
7549 */
7550__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx)
7551{
7552 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
7553}
7554
7555/**
7556 * @brief Get flag ADC analog watchdog 1 flag
7557 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7558 * @param ADCx ADC instance
7559 * @retval State of bit (1 or 0).
7560 */
7561__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
7562{
7563 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7564}
7565
7566/**
7567 * @brief Get flag ADC analog watchdog 2.
7568 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7569 * @param ADCx ADC instance
7570 * @retval State of bit (1 or 0).
7571 */
7572__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
7573{
7574 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7575}
7576
7577/**
7578 * @brief Get flag ADC analog watchdog 3.
7579 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7580 * @param ADCx ADC instance
7581 * @retval State of bit (1 or 0).
7582 */
7583__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
7584{
7585 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7586}
7587
7588/**
7589 * @brief Clear flag ADC ready.
7590 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7591 * is enabled and when conversion clock is active.
7592 * (not only core clock: this ADC has a dual clock domain)
7593 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7594 * @param ADCx ADC instance
7595 * @retval None
7596 */
7597__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7598{
7599 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7600}
7601
7602/**
7603 * @brief Clear flag ADC group regular end of unitary conversion.
7604 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7605 * @param ADCx ADC instance
7606 * @retval None
7607 */
7608__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7609{
7610 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7611}
7612
7613/**
7614 * @brief Clear flag ADC group regular end of sequence conversions.
7615 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7616 * @param ADCx ADC instance
7617 * @retval None
7618 */
7619__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7620{
7621 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7622}
7623
7624/**
7625 * @brief Clear flag ADC group regular overrun.
7626 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7627 * @param ADCx ADC instance
7628 * @retval None
7629 */
7630__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7631{
7632 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7633}
7634
7635/**
7636 * @brief Clear flag ADC group regular end of sampling phase.
7637 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7638 * @param ADCx ADC instance
7639 * @retval None
7640 */
7641__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7642{
7643 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7644}
7645
7646/**
7647 * @brief Clear flag ADC group injected end of unitary conversion.
7648 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7649 * @param ADCx ADC instance
7650 * @retval None
7651 */
7652__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7653{
7654 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7655}
7656
7657/**
7658 * @brief Clear flag ADC group injected end of sequence conversions.
7659 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7660 * @param ADCx ADC instance
7661 * @retval None
7662 */
7663__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7664{
7665 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7666}
7667
7668/**
7669 * @brief Clear flag ADC group injected contexts queue overflow.
7670 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7671 * @param ADCx ADC instance
7672 * @retval None
7673 */
7674__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7675{
7676 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7677}
7678
7679/**
7680 * @brief Clear flag ADC analog watchdog 1.
7681 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7682 * @param ADCx ADC instance
7683 * @retval None
7684 */
7685__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7686{
7687 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7688}
7689
7690/**
7691 * @brief Clear flag ADC analog watchdog 2.
7692 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7693 * @param ADCx ADC instance
7694 * @retval None
7695 */
7696__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7697{
7698 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7699}
7700
7701/**
7702 * @brief Clear flag ADC analog watchdog 3.
7703 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7704 * @param ADCx ADC instance
7705 * @retval None
7706 */
7707__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7708{
7709 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7710}
7711
7712/**
7713 * @brief Get flag multimode ADC ready of the ADC master.
7714 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7715 * @param ADCxy_COMMON ADC common instance
7716 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7717 * @retval State of bit (1 or 0).
7718 */
7719__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7720{
7721 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7722}
7723
7724/**
7725 * @brief Get flag multimode ADC ready of the ADC slave.
7726 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7727 * @param ADCxy_COMMON ADC common instance
7728 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7729 * @retval State of bit (1 or 0).
7730 */
7731__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7732{
7733 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7734}
7735
7736/**
7737 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7738 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7739 * @param ADCxy_COMMON ADC common instance
7740 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7741 * @retval State of bit (1 or 0).
7742 */
7743__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7744{
7745 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7746}
7747
7748/**
7749 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7750 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7751 * @param ADCxy_COMMON ADC common instance
7752 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7753 * @retval State of bit (1 or 0).
7754 */
7755__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7756{
7757 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7758}
7759
7760/**
7761 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7762 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7763 * @param ADCxy_COMMON ADC common instance
7764 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7765 * @retval State of bit (1 or 0).
7766 */
7767__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7768{
7769 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7770}
7771
7772/**
7773 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7774 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7775 * @param ADCxy_COMMON ADC common instance
7776 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7777 * @retval State of bit (1 or 0).
7778 */
7779__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7780{
7781 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7782}
7783
7784/**
7785 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7786 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7787 * @param ADCxy_COMMON ADC common instance
7788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7789 * @retval State of bit (1 or 0).
7790 */
7791__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7792{
7793 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7794}
7795
7796/**
7797 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7798 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7799 * @param ADCxy_COMMON ADC common instance
7800 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7801 * @retval State of bit (1 or 0).
7802 */
7803__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7804{
7805 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7806}
7807
7808/**
7809 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7810 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7811 * @param ADCxy_COMMON ADC common instance
7812 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7813 * @retval State of bit (1 or 0).
7814 */
7815__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7816{
7817 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7818}
7819
7820/**
7821 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7822 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7823 * @param ADCxy_COMMON ADC common instance
7824 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7825 * @retval State of bit (1 or 0).
7826 */
7827__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7828{
7829 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7830}
7831
7832/**
7833 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7834 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7835 * @param ADCxy_COMMON ADC common instance
7836 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7837 * @retval State of bit (1 or 0).
7838 */
7839__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7840{
7841 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7842}
7843
7844/**
7845 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7846 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7847 * @param ADCxy_COMMON ADC common instance
7848 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7849 * @retval State of bit (1 or 0).
7850 */
7851__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7852{
7853 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7854}
7855
7856/**
7857 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7858 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7859 * @param ADCxy_COMMON ADC common instance
7860 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7861 * @retval State of bit (1 or 0).
7862 */
7863__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7864{
7865 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7866}
7867
7868/**
7869 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7870 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7871 * @param ADCxy_COMMON ADC common instance
7872 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7873 * @retval State of bit (1 or 0).
7874 */
7875__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7876{
7877 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7878}
7879
7880/**
7881 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7882 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7883 * @param ADCxy_COMMON ADC common instance
7884 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7885 * @retval State of bit (1 or 0).
7886 */
7887__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7888{
7889 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7890}
7891
7892/**
7893 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7894 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7895 * @param ADCxy_COMMON ADC common instance
7896 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7897 * @retval State of bit (1 or 0).
7898 */
7899__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7900{
7901 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7902}
7903
7904/**
7905 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7906 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7907 * @param ADCxy_COMMON ADC common instance
7908 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7909 * @retval State of bit (1 or 0).
7910 */
7911__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7912{
7913 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7914}
7915
7916/**
7917 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7918 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7919 * @param ADCxy_COMMON ADC common instance
7920 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7921 * @retval State of bit (1 or 0).
7922 */
7923__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7924{
7925 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7926}
7927
7928/**
7929 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7930 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7931 * @param ADCxy_COMMON ADC common instance
7932 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7933 * @retval State of bit (1 or 0).
7934 */
7935__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7936{
7937 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7938}
7939
7940/**
7941 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7942 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7943 * @param ADCxy_COMMON ADC common instance
7944 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7945 * @retval State of bit (1 or 0).
7946 */
7947__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7948{
7949 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7950}
7951
7952/**
7953 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7954 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7955 * @param ADCxy_COMMON ADC common instance
7956 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7957 * @retval State of bit (1 or 0).
7958 */
7959__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7960{
7961 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7962}
7963
7964/**
7965 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7966 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7967 * @param ADCxy_COMMON ADC common instance
7968 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7969 * @retval State of bit (1 or 0).
7970 */
7971__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7972{
7973 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7974}
7975
7976/**
7977 * @}
7978 */
7979
7980/** @defgroup ADC_LL_EF_IT_Management ADC IT management
7981 * @{
7982 */
7983
7984/**
7985 * @brief Enable ADC ready.
7986 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7987 * @param ADCx ADC instance
7988 * @retval None
7989 */
7990__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7991{
7992 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7993}
7994
7995/**
7996 * @brief Enable interruption ADC group regular end of unitary conversion.
7997 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7998 * @param ADCx ADC instance
7999 * @retval None
8000 */
8001__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
8002{
8003 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
8004}
8005
8006/**
8007 * @brief Enable interruption ADC group regular end of sequence conversions.
8008 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
8009 * @param ADCx ADC instance
8010 * @retval None
8011 */
8012__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
8013{
8014 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
8015}
8016
8017/**
8018 * @brief Enable ADC group regular interruption overrun.
8019 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
8020 * @param ADCx ADC instance
8021 * @retval None
8022 */
8023__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
8024{
8025 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
8026}
8027
8028/**
8029 * @brief Enable interruption ADC group regular end of sampling.
8030 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
8031 * @param ADCx ADC instance
8032 * @retval None
8033 */
8034__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
8035{
8036 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8037}
8038
8039/**
8040 * @brief Enable interruption ADC group injected end of unitary conversion.
8041 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
8042 * @param ADCx ADC instance
8043 * @retval None
8044 */
8045__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
8046{
8047 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8048}
8049
8050/**
8051 * @brief Enable interruption ADC group injected end of sequence conversions.
8052 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
8053 * @param ADCx ADC instance
8054 * @retval None
8055 */
8056__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
8057{
8058 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8059}
8060
8061/**
8062 * @brief Enable interruption ADC group injected context queue overflow.
8063 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
8064 * @param ADCx ADC instance
8065 * @retval None
8066 */
8067__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
8068{
8069 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8070}
8071
8072/**
8073 * @brief Enable interruption ADC analog watchdog 1.
8074 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
8075 * @param ADCx ADC instance
8076 * @retval None
8077 */
8078__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
8079{
8080 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8081}
8082
8083/**
8084 * @brief Enable interruption ADC analog watchdog 2.
8085 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
8086 * @param ADCx ADC instance
8087 * @retval None
8088 */
8089__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8090{
8091 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8092}
8093
8094/**
8095 * @brief Enable interruption ADC analog watchdog 3.
8096 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
8097 * @param ADCx ADC instance
8098 * @retval None
8099 */
8100__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8101{
8102 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8103}
8104
8105/**
8106 * @brief Disable interruption ADC ready.
8107 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
8108 * @param ADCx ADC instance
8109 * @retval None
8110 */
8111__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8112{
8113 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8114}
8115
8116/**
8117 * @brief Disable interruption ADC group regular end of unitary conversion.
8118 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
8119 * @param ADCx ADC instance
8120 * @retval None
8121 */
8122__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8123{
8124 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8125}
8126
8127/**
8128 * @brief Disable interruption ADC group regular end of sequence conversions.
8129 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
8130 * @param ADCx ADC instance
8131 * @retval None
8132 */
8133__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8134{
8135 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8136}
8137
8138/**
8139 * @brief Disable interruption ADC group regular overrun.
8140 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
8141 * @param ADCx ADC instance
8142 * @retval None
8143 */
8144__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8145{
8146 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8147}
8148
8149/**
8150 * @brief Disable interruption ADC group regular end of sampling.
8151 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
8152 * @param ADCx ADC instance
8153 * @retval None
8154 */
8155__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8156{
8157 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8158}
8159
8160/**
8161 * @brief Disable interruption ADC group regular end of unitary conversion.
8162 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
8163 * @param ADCx ADC instance
8164 * @retval None
8165 */
8166__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8167{
8168 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8169}
8170
8171/**
8172 * @brief Disable interruption ADC group injected end of sequence conversions.
8173 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8174 * @param ADCx ADC instance
8175 * @retval None
8176 */
8177__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8178{
8179 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8180}
8181
8182/**
8183 * @brief Disable interruption ADC group injected context queue overflow.
8184 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
8185 * @param ADCx ADC instance
8186 * @retval None
8187 */
8188__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8189{
8190 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8191}
8192
8193/**
8194 * @brief Disable interruption ADC analog watchdog 1.
8195 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8196 * @param ADCx ADC instance
8197 * @retval None
8198 */
8199__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8200{
8201 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8202}
8203
8204/**
8205 * @brief Disable interruption ADC analog watchdog 2.
8206 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8207 * @param ADCx ADC instance
8208 * @retval None
8209 */
8210__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8211{
8212 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8213}
8214
8215/**
8216 * @brief Disable interruption ADC analog watchdog 3.
8217 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8218 * @param ADCx ADC instance
8219 * @retval None
8220 */
8221__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8222{
8223 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8224}
8225
8226/**
8227 * @brief Get state of interruption ADC ready
8228 * (0: interrupt disabled, 1: interrupt enabled).
8229 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8230 * @param ADCx ADC instance
8231 * @retval State of bit (1 or 0).
8232 */
8233__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
8234{
8235 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8236}
8237
8238/**
8239 * @brief Get state of interruption ADC group regular end of unitary conversion
8240 * (0: interrupt disabled, 1: interrupt enabled).
8241 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8242 * @param ADCx ADC instance
8243 * @retval State of bit (1 or 0).
8244 */
8245__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
8246{
8247 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8248}
8249
8250/**
8251 * @brief Get state of interruption ADC group regular end of sequence conversions
8252 * (0: interrupt disabled, 1: interrupt enabled).
8253 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8254 * @param ADCx ADC instance
8255 * @retval State of bit (1 or 0).
8256 */
8257__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
8258{
8259 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8260}
8261
8262/**
8263 * @brief Get state of interruption ADC group regular overrun
8264 * (0: interrupt disabled, 1: interrupt enabled).
8265 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8266 * @param ADCx ADC instance
8267 * @retval State of bit (1 or 0).
8268 */
8269__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
8270{
8271 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8272}
8273
8274/**
8275 * @brief Get state of interruption ADC group regular end of sampling
8276 * (0: interrupt disabled, 1: interrupt enabled).
8277 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8278 * @param ADCx ADC instance
8279 * @retval State of bit (1 or 0).
8280 */
8281__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
8282{
8283 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8284}
8285
8286/**
8287 * @brief Get state of interruption ADC group injected end of unitary conversion
8288 * (0: interrupt disabled, 1: interrupt enabled).
8289 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8290 * @param ADCx ADC instance
8291 * @retval State of bit (1 or 0).
8292 */
8293__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
8294{
8295 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8296}
8297
8298/**
8299 * @brief Get state of interruption ADC group injected end of sequence conversions
8300 * (0: interrupt disabled, 1: interrupt enabled).
8301 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8302 * @param ADCx ADC instance
8303 * @retval State of bit (1 or 0).
8304 */
8305__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
8306{
8307 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8308}
8309
8310/**
8311 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
8312 * (0: interrupt disabled, 1: interrupt enabled).
8313 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
8314 * @param ADCx ADC instance
8315 * @retval State of bit (1 or 0).
8316 */
8317__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
8318{
8319 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8320}
8321
8322/**
8323 * @brief Get state of interruption ADC analog watchdog 1
8324 * (0: interrupt disabled, 1: interrupt enabled).
8325 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8326 * @param ADCx ADC instance
8327 * @retval State of bit (1 or 0).
8328 */
8329__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
8330{
8331 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8332}
8333
8334/**
8335 * @brief Get state of interruption Get ADC analog watchdog 2
8336 * (0: interrupt disabled, 1: interrupt enabled).
8337 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
8338 * @param ADCx ADC instance
8339 * @retval State of bit (1 or 0).
8340 */
8341__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
8342{
8343 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8344}
8345
8346/**
8347 * @brief Get state of interruption Get ADC analog watchdog 3
8348 * (0: interrupt disabled, 1: interrupt enabled).
8349 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
8350 * @param ADCx ADC instance
8351 * @retval State of bit (1 or 0).
8352 */
8353__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
8354{
8355 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8356}
8357
8358/**
8359 * @}
8360 */
8361
8362#if defined(USE_FULL_LL_DRIVER)
8363/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
8364 * @{
8365 */
8366
8367/* Initialization of some features of ADC common parameters and multimode */
8368ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
8369ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8370void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8371
8372/* De-initialization of ADC instance, ADC group regular and ADC group injected */
8373/* (availability of ADC group injected depends on STM32 families) */
8374ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8375
8376/* Initialization of some features of ADC instance */
8377ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
8378void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
8379
8380/* Initialization of some features of ADC instance and ADC group regular */
8381ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8382void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8383
8384/* Initialization of some features of ADC instance and ADC group injected */
8385ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8386void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8387
8388/**
8389 * @}
8390 */
8391#endif /* USE_FULL_LL_DRIVER */
8392
8393/**
8394 * @}
8395 */
8396
8397/**
8398 * @}
8399 */
8400
8401#endif /* ADC1 || ADC2 || ADC3 */
8402
8403/**
8404 * @}
8405 */
8406
8407#ifdef __cplusplus
8408}
8409#endif
8410
8411#endif /* STM32H7xx_LL_ADC_H */
8412
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
__IO
#define __IO
Defines 'read / write' permissions.
Definition core_armv81mml.h:290
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
POSITION_VAL
#define POSITION_VAL(VAL)
Definition stm32h7xx.h:221
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
ErrorStatus
ErrorStatus
Definition stm32h7xx.h:194
ADC_SMPR1_SMP0
#define ADC_SMPR1_SMP0
ADC Channel 0 Sampling time selection.
Definition stm32h723xx.h:3032
ADC3_CFGR_DMAEN
#define ADC3_CFGR_DMAEN
ADC DMA transfer enable.
Definition stm32h723xx.h:2941
ADC_CCR_CKMODE
#define ADC_CCR_CKMODE
ADC clock mode.
Definition stm32h723xx.h:4086
ADC_CALFACT_CALFACT_S
#define ADC_CALFACT_CALFACT_S
ADC calibration factors in single-ended mode.
Definition stm32h723xx.h:3928
ADC_CCR_PRESC
#define ADC_CCR_PRESC
ADC prescaler.
Definition stm32h723xx.h:4092
ADC_CFGR_JAUTO
#define ADC_CFGR_JAUTO
ADC Automatic injected group conversion.
Definition stm32h723xx.h:2924
ADC_OFR1_OFFSET1_CH
#define ADC_OFR1_OFFSET1_CH
ADC Channel selection for the data offset 1.
Definition stm32h723xx.h:3491
ADC_CFGR_DISCEN
#define ADC_CFGR_DISCEN
ADC Discontinuous mode for regular channels.
Definition stm32h723xx.h:2898
ADC_CALFACT2_LINCALFACT
#define ADC_CALFACT2_LINCALFACT
ADC Linearity calibration factors.
Definition stm32h723xx.h:3958
ADC_CR_ADSTART
#define ADC_CR_ADSTART
ADC Start of Regular conversion.
Definition stm32h723xx.h:2808
ADC_CR_ADEN
#define ADC_CR_ADEN
ADC Enable control.
Definition stm32h723xx.h:2802
ADC_CR_JADSTART
#define ADC_CR_JADSTART
ADC Start of injected conversion.
Definition stm32h723xx.h:2811
ADC_CR_ADCALLIN
#define ADC_CR_ADCALLIN
ADC Linearity calibration.
Definition stm32h723xx.h:2825
ADC3_OFR1_OFFSETPOS
#define ADC3_OFR1_OFFSETPOS
ADC offset number 1 positive.
Definition stm32h723xx.h:3508
ADC_JSQR_JSQ4
#define ADC_JSQR_JSQ4
ADC 4th conversion in injected sequence.
Definition stm32h723xx.h:3451
ADC_CFGR2_TROVS
#define ADC_CFGR2_TROVS
ADC Triggered regular Oversampling.
Definition stm32h723xx.h:2973
ADC_JSQR_JSQ2
#define ADC_JSQR_JSQ2
ADC 2nd conversion in injected sequence.
Definition stm32h723xx.h:3433
ADC3_CFGR2_BULB
#define ADC3_CFGR2_BULB
ADC Bulb sampling mode.
Definition stm32h723xx.h:3025
ADC3_CFGR2_OVSR
#define ADC3_CFGR2_OVSR
ADC oversampling ratio.
Definition stm32h723xx.h:3015
ADC3_TR1_AWDFILT
#define ADC3_TR1_AWDFILT
ADC analog watchdog filtering parameter.
Definition stm32h723xx.h:3213
ADC_CFGR_DISCNUM
#define ADC_CFGR_DISCNUM
ADC Discontinuous mode channel count.
Definition stm32h723xx.h:2902
ADC_DIFSEL_DIFSEL
#define ADC_DIFSEL_DIFSEL
ADC differential modes for channels 1 to 18.
Definition stm32h723xx.h:3903
ADC_CFGR_DMNGT
#define ADC_CFGR_DMNGT
ADC Data Management configuration.
Definition stm32h723xx.h:2860
ADC3_TR1_LT1
#define ADC3_TR1_LT1
ADC analog watchdog 1 threshold low.
Definition stm32h723xx.h:3209
ADC_CR_ADSTP
#define ADC_CR_ADSTP
ADC Stop of Regular conversion.
Definition stm32h723xx.h:2814
ADC_CFGR_RES_0
#define ADC_CFGR_RES_0
0x00000004
Definition stm32h723xx.h:2867
ADC_CR_ADVREGEN
#define ADC_CR_ADVREGEN
ADC Voltage regulator Enable.
Definition stm32h723xx.h:2846
ADC_CFGR2_OVSR_Pos
#define ADC_CFGR2_OVSR_Pos
Definition stm32h723xx.h:2991
ADC3_CFGR_DMACFG
#define ADC3_CFGR_DMACFG
ADC DMA transfer configuration.
Definition stm32h723xx.h:2944
ADC_CR_ADCALDIF
#define ADC_CR_ADCALDIF
ADC Differential Mode for calibration.
Definition stm32h723xx.h:2852
ADC_CFGR2_OVSS
#define ADC_CFGR2_OVSS
ADC Regular Oversampling shift.
Definition stm32h723xx.h:2965
ADC_CFGR_AWD1CH_Pos
#define ADC_CFGR_AWD1CH_Pos
Definition stm32h723xx.h:2926
ADC_CR_DEEPPWD
#define ADC_CR_DEEPPWD
ADC Deep power down Enable.
Definition stm32h723xx.h:2849
ADC3_TR1_HT1_Pos
#define ADC3_TR1_HT1_Pos
Definition stm32h723xx.h:3218
ADC_CFGR2_ROVSE
#define ADC_CFGR2_ROVSE
ADC Regular group oversampler enable.
Definition stm32h723xx.h:2958
ADC_CFGR2_JOVSE
#define ADC_CFGR2_JOVSE
ADC Injected group oversampler enable.
Definition stm32h723xx.h:2961
ADC_OFR1_SSATE
#define ADC_OFR1_SSATE
ADC Signed saturation Enable.
Definition stm32h723xx.h:3500
ADC_CFGR2_OVSR
#define ADC_CFGR2_OVSR
ADC oversampling Ratio.
Definition stm32h723xx.h:2993
ADC_CFGR_AUTDLY
#define ADC_CFGR_AUTDLY
ADC Delayed conversion mode.
Definition stm32h723xx.h:2894
ADC_CFGR2_RSHIFT4
#define ADC_CFGR2_RSHIFT4
ADC Right-shift data after Offset 4 correction.
Definition stm32h723xx.h:2989
ADC_OFR1_OFFSET1
#define ADC_OFR1_OFFSET1
ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0].
Definition stm32h723xx.h:3461
ADC_CFGR_JAWD1EN
#define ADC_CFGR_JAWD1EN
ADC Analog watchdog 1 enable on injected Channels.
Definition stm32h723xx.h:2921
ADC_CFGR_JQDIS
#define ADC_CFGR_JQDIS
ADC Injected queue disable.
Definition stm32h723xx.h:2937
ADC_CFGR2_RSHIFT3
#define ADC_CFGR2_RSHIFT3
ADC Right-shift data after Offset 3 correction.
Definition stm32h723xx.h:2986
ADC_CFGR2_RSHIFT1
#define ADC_CFGR2_RSHIFT1
ADC Right-shift data after Offset 1 correction.
Definition stm32h723xx.h:2980
ADC_JSQR_JEXTSEL
#define ADC_JSQR_JEXTSEL
ADC external trigger selection for injected group.
Definition stm32h723xx.h:3409
ADC3_OFR1_OFFSET1_EN
#define ADC3_OFR1_OFFSET1_EN
ADC offset number 1 enable.
Definition stm32h723xx.h:3515
ADC_CFGR_CONT
#define ADC_CFGR_CONT
ADC Single/continuous conversion mode for regular conversion.
Definition stm32h723xx.h:2891
ADC3_CFGR2_SMPTRIG
#define ADC3_CFGR2_SMPTRIG
ADC Sample Time Control Trigger mode.
Definition stm32h723xx.h:3028
ADC_CR_ADCAL
#define ADC_CR_ADCAL
ADC Calibration.
Definition stm32h723xx.h:2855
ADC_CFGR_RES_1
#define ADC_CFGR_RES_1
0x00000008
Definition stm32h723xx.h:2868
ADC_ISR_EOC
#define ADC_ISR_EOC
ADC End of Regular Conversion flag.
Definition stm32h723xx.h:2735
ADC_CFGR_AWD1CH
#define ADC_CFGR_AWD1CH
ADC Analog watchdog 1 Channel selection.
Definition stm32h723xx.h:2928
ADC3_TR1_HT1
#define ADC3_TR1_HT1
ADC analog watchdog 1 threshold high.
Definition stm32h723xx.h:3220
ADC_CCR_DELAY
#define ADC_CCR_DELAY
Delay between 2 sampling phases.
Definition stm32h723xx.h:4071
ADC_CCR_DAMDF
#define ADC_CCR_DAMDF
Dual ADC mode Data format.
Definition stm32h723xx.h:4080
ADC_JSQR_JL
#define ADC_JSQR_JL
ADC injected channel sequence length.
Definition stm32h723xx.h:3403
ADC_CFGR_AWD1EN
#define ADC_CFGR_AWD1EN
ADC Analog watchdog 1 enable on regular Channels.
Definition stm32h723xx.h:2918
ADC3_OFR1_SATEN
#define ADC3_OFR1_SATEN
ADC offset number 1 saturation enable.
Definition stm32h723xx.h:3511
ADC_CCR_VBATEN
#define ADC_CCR_VBATEN
VBAT enable.
Definition stm32h723xx.h:4106
ADC_CFGR_EXTSEL
#define ADC_CFGR_EXTSEL
ADC External trigger selection for regular group.
Definition stm32h723xx.h:2873
ADC_DR_RDATA
#define ADC_DR_RDATA
ADC regular Data converted.
Definition stm32h723xx.h:3398
ADC_CFGR2_ROVSM
#define ADC_CFGR2_ROVSM
ADC Regular oversampling mode.
Definition stm32h723xx.h:2976
ADC_LTR_LT
#define ADC_LTR_LT
ADC Analog watchdog 1, 2 and 3 lower threshold.
Definition stm32h723xx.h:3199
ADC_CR_JADSTP
#define ADC_CR_JADSTP
ADC Stop of injected conversion.
Definition stm32h723xx.h:2817
ADC_JDR1_JDATA
#define ADC_JDR1_JDATA
ADC Injected DATA.
Definition stm32h723xx.h:3697
ADC_JSQR_JEXTEN
#define ADC_JSQR_JEXTEN
ADC external trigger enable and polarity selection for injected channels.
Definition stm32h723xx.h:3418
ADC_CFGR2_RSHIFT2
#define ADC_CFGR2_RSHIFT2
ADC Right-shift data after Offset 2 correction.
Definition stm32h723xx.h:2983
ADC_HTR_HT
#define ADC_HTR_HT
ADC Analog watchdog 1,2 and 3 higher threshold.
Definition stm32h723xx.h:3204
ADC_JSQR_JSQ1
#define ADC_JSQR_JSQ1
ADC 1st conversion in injected sequence.
Definition stm32h723xx.h:3424
ADC_CR_ADDIS
#define ADC_CR_ADDIS
ADC Disable command.
Definition stm32h723xx.h:2805
ADC_CFGR_AWD1SGL
#define ADC_CFGR_AWD1SGL
Enable the watchdog 1 on a single channel or on all channels.
Definition stm32h723xx.h:2915
ADC_CFGR_JQM
#define ADC_CFGR_JQM
ADC JSQR Queue mode.
Definition stm32h723xx.h:2912
ADC_CCR_DUAL
#define ADC_CCR_DUAL
Dual ADC mode selection.
Definition stm32h723xx.h:4062
ADC_JSQR_JSQ3
#define ADC_JSQR_JSQ3
ADC 3rd conversion in injected sequence.
Definition stm32h723xx.h:3442
ADC_CR_BOOST
#define ADC_CR_BOOST
ADC Boost Mode configuration.
Definition stm32h723xx.h:2820
ADC_SQR1_L
#define ADC_SQR1_L
ADC regular channel sequence length.
Definition stm32h723xx.h:3243
ADC_CR_BOOST_0
#define ADC_CR_BOOST_0
0x00000100
Definition stm32h723xx.h:2821
ADC3_CFGR_RES
#define ADC3_CFGR_RES
ADC data resolution.
Definition stm32h723xx.h:2948
ADC_CFGR_JDISCEN
#define ADC_CFGR_JDISCEN
ADC Discontinuous mode on injected channels.
Definition stm32h723xx.h:2909
ADC_CFGR_RES
#define ADC_CFGR_RES
ADC Data resolution.
Definition stm32h723xx.h:2866
ADC_CCR_TSEN
#define ADC_CCR_TSEN
Temperature sensor enable.
Definition stm32h723xx.h:4103
ADC_CCR_VREFEN
#define ADC_CCR_VREFEN
VREFINT enable.
Definition stm32h723xx.h:4100
ADC_CFGR_OVRMOD
#define ADC_CFGR_OVRMOD
ADC overrun mode.
Definition stm32h723xx.h:2888
ADC_CFGR_EXTEN
#define ADC_CFGR_EXTEN
ADC External trigger enable and polarity selection for regular channels.
Definition stm32h723xx.h:2882
ADC_AWD2CR_AWD2CH_0
#define ADC_AWD2CR_AWD2CH_0
0x00000001
Definition stm32h723xx.h:3846
DBGMCU
#define DBGMCU
Definition stm32h723xx.h:2655
ADC3
#define ADC3
Definition stm32h723xx.h:2528
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
ADC_Common_TypeDef
Definition stm32h723xx.h:289
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C.
Definition stm32h723xx.h:293
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
ADC Common status register, Address offset: ADC1/3 base address + 0x300.
Definition stm32h723xx.h:290
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
ADC common control register, Address offset: ADC1/3 base address + 0x308.
Definition stm32h723xx.h:292
ADC_TypeDef
Analog to Digital Converter.
Definition stm32h723xx.h:242
ADC_TypeDef::SQR1
__IO uint32_t SQR1
ADC regular sequence register 1, Address offset: 0x30.
Definition stm32h723xx.h:255
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
ADC Configuration register 2, Address offset: 0x10.
Definition stm32h723xx.h:247
ADC_TypeDef::CFGR
__IO uint32_t CFGR
ADC Configuration register, Address offset: 0x0C.
Definition stm32h723xx.h:246
ADC_TypeDef::JSQR
__IO uint32_t JSQR
ADC injected sequence register, Address offset: 0x4C.
Definition stm32h723xx.h:262
ADC_TypeDef::CR
__IO uint32_t CR
ADC control register, Address offset: 0x08.
Definition stm32h723xx.h:245
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
ADC sample time register 1, Address offset: 0x14.
Definition stm32h723xx.h:248
ADC_TypeDef::IER
__IO uint32_t IER
ADC Interrupt Enable Register, Address offset: 0x04.
Definition stm32h723xx.h:244
ADC_TypeDef::DR
__IO uint32_t DR
ADC regular data register, Address offset: 0x40.
Definition stm32h723xx.h:259
ADC_TypeDef::DIFSEL_RES12
__IO uint32_t DIFSEL_RES12
ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0.
Definition stm32h723xx.h:282
ADC_TypeDef::OFR1
__IO uint32_t OFR1
ADC offset register 1, Address offset: 0x60.
Definition stm32h723xx.h:264
ADC_TypeDef::JDR1
__IO uint32_t JDR1
ADC injected data register 1, Address offset: 0x80.
Definition stm32h723xx.h:269
ADC_TypeDef::LTR2_DIFSEL
__IO uint32_t LTR2_DIFSEL
ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0.
Definition stm32h723xx.h:278
ADC_TypeDef::PCSEL_RES0
__IO uint32_t PCSEL_RES0
Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C.
Definition stm32h723xx.h:250
ADC_TypeDef::CALFACT_RES13
__IO uint32_t CALFACT_RES13
ADC Calibration Factors specific ADC1/2, Address offset: 0xC4.
Definition stm32h723xx.h:283
ADC_TypeDef::ISR
__IO uint32_t ISR
ADC Interrupt and Status Register, Address offset: 0x00.
Definition stm32h723xx.h:243
ADC_TypeDef::CALFACT2_RES14
__IO uint32_t CALFACT2_RES14
ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8.
Definition stm32h723xx.h:284
ADC_TypeDef::LTR1_TR1
__IO uint32_t LTR1_TR1
ADC watchdog Lower threshold register 1, Address offset: 0x20.
Definition stm32h723xx.h:251