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stm32h7xx_ll_dmamux.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_DMAMUX_H
21#define STM32H7xx_LL_DMAMUX_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined (DMAMUX1) || defined (DMAMUX2)
35
36/** @defgroup DMAMUX_LL DMAMUX
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private constants ---------------------------------------------------------*/
43/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
44 * @{
45 */
46/* Define used to get DMAMUX CCR register size */
47#define DMAMUX_CCR_SIZE 0x00000004U
48
49/* Define used to get DMAMUX RGCR register size */
50#define DMAMUX_RGCR_SIZE 0x00000004U
51
52/* Define used to get DMAMUX RequestGenerator offset */
53#define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
54/* Define used to get DMAMUX Channel Status offset */
55#define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
56/* Define used to get DMAMUX RequestGenerator status offset */
57#define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
58
59/**
60 * @}
61 */
62
63/* Private macros ------------------------------------------------------------*/
64/* Exported types ------------------------------------------------------------*/
65/* Exported constants --------------------------------------------------------*/
66/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
67 * @{
68 */
69/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
70 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
71 * @{
72 */
73#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
74#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
75#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
76#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
77#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
78#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
79#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
80#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
81#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
82#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
83#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
84#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
85#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
86#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
87#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
88#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
89#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
90#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
91#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
92#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
93#define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
94#define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
95#define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
96#define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
97/**
98 * @}
99 */
100
101/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
103 * @{
104 */
105#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
106#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
107#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
108#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
109#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
110#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
111#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
112#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
113#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
114#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
115#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
116#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
117#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
118#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
119#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
120#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
121#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
122#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
123#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
124#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
125#define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
126#define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
127#define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
128#define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
129/**
130 * @}
131 */
132
133/** @defgroup DMAMUX_LL_EC_IT IT Defines
134 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
135 * @{
136 */
137#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
138#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
139/**
140 * @}
141 */
142
143/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection
144 * @brief DMAMUX1 Request selection
145 * @{
146 */
147/* DMAMUX1 requests */
148#define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */
149#define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
150#define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
151#define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
152#define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
153#define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
154#define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
155#define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
156#define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
157#define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */
158#define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */
159#define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
160#define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
161#define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
162#define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
163#define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
164#define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
165#define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
166#define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
167#define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
168#define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
169#define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
170#define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
171#define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
172#define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
173#define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
174#define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
175#define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
176#define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
177#define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
178#define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
179#define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
180#define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
181#define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
182#define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
183#define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
184#define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
185#define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
186#define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
187#define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
188#define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
189#define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */
190#define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */
191#define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
192#define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
193#define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
194#define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
195#define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
196#define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
197#define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
198#define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
199#define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
200#define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
201#define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
202#define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
203#define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
204#define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
205#define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
206#define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
207#define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
208#define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
209#define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
210#define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
211#define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
212#define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
213#define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
214#define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */
215#define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */
216#define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
217#define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
218#define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
219#define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
220#define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
221#define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
222#if defined (PSSI)
223#define LL_DMAMUX1_REQ_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */
224#define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
225#else
226#define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */
227#endif /* PSSI */
228#define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
229#define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
230#define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */
231#define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
232#define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
233#define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
234#define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
235#define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
236#define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
237#define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
238#define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
239#define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
240#define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
241#if defined(SAI2)
242#define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
243#define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
244#endif /* SAI2 */
245#define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
246#define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
247#define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */
248#define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */
249#if defined (HRTIM1)
250#define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
251#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */
252#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */
253#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */
254#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */
255#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6 */
256#endif /* HRTIM1 */
257#define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */
258#define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */
259#define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM1 Filter2 request */
260#define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM1 Filter3 request */
261#define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
262#define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
263#define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
264#define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
265#define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
266#define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
267#define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
268#define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
269#if defined (SAI3)
270#define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
271#define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
272#endif /* SAI3 */
273#if defined (ADC3)
274#define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */
275#endif /* ADC3 */
276#if defined (UART9)
277#define LL_DMAMUX1_REQ_UART9_RX 116U /*!< DMAMUX1 UART9 RX request */
278#define LL_DMAMUX1_REQ_UART9_TX 117U /*!< DMAMUX1 UART9 TX request */
279#endif /* UART9 */
280#if defined (USART10)
281#define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */
282#define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */
283#endif /* USART10 */
284#if defined(FMAC)
285#define LL_DMAMUX1_REQ_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */
286#define LL_DMAMUX1_REQ_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */
287#endif /* FMAC */
288#if defined(CORDIC)
289#define LL_DMAMUX1_REQ_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */
290#define LL_DMAMUX1_REQ_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */
291#endif /* CORDIC */
292#if defined(I2C5)
293#define LL_DMAMUX1_REQ_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */
294#define LL_DMAMUX1_REQ_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */
295#endif /* I2C5 */
296#if defined(TIM23)
297#define LL_DMAMUX1_REQ_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */
298#define LL_DMAMUX1_REQ_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */
299#define LL_DMAMUX1_REQ_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */
300#define LL_DMAMUX1_REQ_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */
301#define LL_DMAMUX1_REQ_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */
302#define LL_DMAMUX1_REQ_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */
303#endif /* TIM23 */
304#if defined(TIM24)
305#define LL_DMAMUX1_REQ_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */
306#define LL_DMAMUX1_REQ_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */
307#define LL_DMAMUX1_REQ_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */
308#define LL_DMAMUX1_REQ_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */
309#define LL_DMAMUX1_REQ_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */
310#define LL_DMAMUX1_REQ_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */
311#endif /* TIM24 */
312/**
313 * @}
314 */
315
316/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection
317 * @brief DMAMUX2 Request selection
318 * @{
319 */
320/* DMAMUX2 requests */
321#define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */
322#define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
323#define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */
324#define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */
325#define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */
326#define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */
327#define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */
328#define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */
329#define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */
330#define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */
331#define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */
332#define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */
333#define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
334#define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
335#define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
336#if defined (SAI4)
337#define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
338#define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
339#endif /* SAI4 */
340#if defined (ADC3)
341#define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */
342#endif /* ADC3 */
343#if defined (DAC2)
344#define LL_DMAMUX2_REQ_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */
345#endif /* DAC2 */
346#if defined (DFSDM2_Channel0)
347#define LL_DMAMUX2_REQ_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 Filter0 request */
348#endif /* DFSDM2_Channel0 */
349/**
350 * @}
351 */
352
353
354/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
355 * @{
356 */
357#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
358#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
359#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
360#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
361#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
362#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
363#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
364#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
365#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */
366#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */
367#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
368#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
369#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
370#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
371#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
372#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
373/**
374 * @}
375 */
376
377/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
378 * @{
379 */
380#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
381#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
382#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
383#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
384/**
385 * @}
386 */
387
388/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
389 * @{
390 */
391#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
392#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
393#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
394#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */
395#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */
396#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */
397#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */
398#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */
399
400#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
401#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
402#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
403#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
404#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
405#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
406#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */
407#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */
408#define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */
409#define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */
410#define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */
411#define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */
412#define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */
413#define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */
414#define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */
415#define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */
416
417/**
418 * @}
419 */
420
421/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
422 * @{
423 */
424#define LL_DMAMUX_REQ_GEN_0 0x00000000U
425#define LL_DMAMUX_REQ_GEN_1 0x00000001U
426#define LL_DMAMUX_REQ_GEN_2 0x00000002U
427#define LL_DMAMUX_REQ_GEN_3 0x00000003U
428#define LL_DMAMUX_REQ_GEN_4 0x00000004U
429#define LL_DMAMUX_REQ_GEN_5 0x00000005U
430#define LL_DMAMUX_REQ_GEN_6 0x00000006U
431#define LL_DMAMUX_REQ_GEN_7 0x00000007U
432/**
433 * @}
434 */
435
436/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
437 * @{
438 */
439#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
440#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
441#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
442#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
443/**
444 * @}
445 */
446
447/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
448 * @{
449 */
450#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
451#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
452#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
453#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */
454#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */
455#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */
456#define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */
457#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */
458
459#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
460#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
461#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
462#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
463#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
464#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
465#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
466#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */
467#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */
468#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */
469#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */
470#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */
471#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */
472#if defined (LPTIM4)
473#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */
474#endif /* LPTIM4 */
475#if defined (LPTIM5)
476#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */
477#endif /* LPTIM5 */
478#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */
479#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */
480#define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */
481#define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */
482#define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */
483#define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */
484#define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */
485#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */
486#define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */
487#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */
488#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */
489#if defined (ADC3)
490#define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */
491#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
492#endif /* ADC3 */
493#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */
494#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */
495/**
496 * @}
497 */
498
499/**
500 * @}
501 */
502
503/* Exported macro ------------------------------------------------------------*/
504/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
505 * @{
506 */
507
508/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
509 * @{
510 */
511/**
512 * @brief Write a value in DMAMUX register
513 * @param __INSTANCE__ DMAMUX Instance
514 * @param __REG__ Register to be written
515 * @param __VALUE__ Value to be written in the register
516 * @retval None
517 */
518#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
519
520/**
521 * @brief Read a value in DMAMUX register
522 * @param __INSTANCE__ DMAMUX Instance
523 * @param __REG__ Register to be read
524 * @retval Register value
525 */
526#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
527/**
528 * @}
529 */
530
531/**
532 * @}
533 */
534
535/* Exported functions --------------------------------------------------------*/
536/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
537 * @{
538 */
539
540/** @defgroup DMAMUX_LL_EF_Configuration Configuration
541 * @{
542 */
543/**
544 * @brief Set DMAMUX request ID for DMAMUX Channel x.
545 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
546 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
547 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
548 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
549 * @param DMAMUXx DMAMUXx Instance
550 * @param Channel This parameter can be one of the following values:
551 * @arg @ref LL_DMAMUX_CHANNEL_0
552 * @arg @ref LL_DMAMUX_CHANNEL_1
553 * @arg @ref LL_DMAMUX_CHANNEL_2
554 * @arg @ref LL_DMAMUX_CHANNEL_3
555 * @arg @ref LL_DMAMUX_CHANNEL_4
556 * @arg @ref LL_DMAMUX_CHANNEL_5
557 * @arg @ref LL_DMAMUX_CHANNEL_6
558 * @arg @ref LL_DMAMUX_CHANNEL_7
559 * @arg @ref LL_DMAMUX_CHANNEL_8
560 * @arg @ref LL_DMAMUX_CHANNEL_9
561 * @arg @ref LL_DMAMUX_CHANNEL_10
562 * @arg @ref LL_DMAMUX_CHANNEL_11
563 * @arg @ref LL_DMAMUX_CHANNEL_12
564 * @arg @ref LL_DMAMUX_CHANNEL_13
565 * @arg @ref LL_DMAMUX_CHANNEL_14
566 * @arg @ref LL_DMAMUX_CHANNEL_15
567 * @param Request This parameter can be one of the following values:
568 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
569 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
570 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
571 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
572 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
573 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
574 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
575 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
576 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
577 * @arg @ref LL_DMAMUX1_REQ_ADC1
578 * @arg @ref LL_DMAMUX1_REQ_ADC2
579 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
580 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
581 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
582 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
583 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
584 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
585 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
586 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
587 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
588 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
589 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
590 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
591 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
592 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
593 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
594 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
595 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
596 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
597 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
598 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
599 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
600 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
601 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
602 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
603 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
604 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
605 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
606 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
607 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
608 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
609 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
610 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
611 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
612 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
613 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
614 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
615 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
616 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
617 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
618 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
619 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
620 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
621 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
622 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
623 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
624 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
625 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
626 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
627 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
628 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
629 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
630 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
631 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
632 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
633 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
634 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
635 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
636 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
637 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
638 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
639 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
640 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
641 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
642 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
643 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
644 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
645 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
646 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
647 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
648 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
649 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
650 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
651 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
652 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
653 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
654 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
655 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
656 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
657 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
658 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
659 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
660 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
661 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
662 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
663 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
664 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
665 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
666 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
667 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
668 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
669 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
670 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
671 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
672 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
673 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
674 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
675 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
676 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
677 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
678 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
679 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
680 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
681 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
682 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
683 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
684 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
685 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
686 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
687 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
688 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
689 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
690 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
691 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
692 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
693 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
694 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
695 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
696 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
697 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
698 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
699 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
700 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
701 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
702 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
703 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
704 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
705 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
706 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
707 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
708 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
709 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
710 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
711 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
712 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
713 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
714 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
715 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
716 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
717 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
718 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
719 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
720 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
721 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
722 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
723 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
724 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
725 *
726 * @note (*) Availability depends on devices.
727 * @retval None
728 */
729__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
730{
731 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
732
733 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
734}
735
736/**
737 * @brief Get DMAMUX request ID for DMAMUX Channel x.
738 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
739 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
740 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
741 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
742 * @param DMAMUXx DMAMUXx Instance
743 * @param Channel This parameter can be one of the following values:
744 * @arg @ref LL_DMAMUX_CHANNEL_0
745 * @arg @ref LL_DMAMUX_CHANNEL_1
746 * @arg @ref LL_DMAMUX_CHANNEL_2
747 * @arg @ref LL_DMAMUX_CHANNEL_3
748 * @arg @ref LL_DMAMUX_CHANNEL_4
749 * @arg @ref LL_DMAMUX_CHANNEL_5
750 * @arg @ref LL_DMAMUX_CHANNEL_6
751 * @arg @ref LL_DMAMUX_CHANNEL_7
752 * @arg @ref LL_DMAMUX_CHANNEL_8
753 * @arg @ref LL_DMAMUX_CHANNEL_9
754 * @arg @ref LL_DMAMUX_CHANNEL_10
755 * @arg @ref LL_DMAMUX_CHANNEL_11
756 * @arg @ref LL_DMAMUX_CHANNEL_12
757 * @arg @ref LL_DMAMUX_CHANNEL_13
758 * @arg @ref LL_DMAMUX_CHANNEL_14
759 * @arg @ref LL_DMAMUX_CHANNEL_15
760 * @retval Returned value can be one of the following values:
761 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
762 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
763 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
764 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
765 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
766 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
767 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
768 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
769 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
770 * @arg @ref LL_DMAMUX1_REQ_ADC1
771 * @arg @ref LL_DMAMUX1_REQ_ADC2
772 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
773 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
774 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
775 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
776 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
777 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
778 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
779 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
780 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
781 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
782 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
783 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
784 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
785 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
786 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
787 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
788 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
789 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
790 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
791 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
792 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
793 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
794 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
795 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
796 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
797 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
798 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
799 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
800 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
801 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
802 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
803 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
804 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
805 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
806 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
807 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
808 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
809 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
810 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
811 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
812 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
813 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
814 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
815 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
816 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
817 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
818 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
819 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
820 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
821 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
822 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
823 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
824 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
825 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
826 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
827 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
828 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
829 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
830 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
831 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
832 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
833 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
834 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
835 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
836 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
837 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
838 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
839 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
840 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
841 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
842 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
843 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
844 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
845 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
846 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
847 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
848 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
849 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
850 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
851 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
852 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
853 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
854 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
855 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
856 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
857 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
858 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
859 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
860 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
861 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
862 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
863 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
864 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
865 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
866 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
867 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
868 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
869 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
870 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
871 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
872 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
873 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
874 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
875 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
876 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
877 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
878 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
879 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
880 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
881 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
882 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
883 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
884 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
885 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
886 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
887 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
888 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
889 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
890 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
891 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
892 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
893 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
894 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
895 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
896 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
897 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
898 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
899 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
900 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
901 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
902 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
903 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
904 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
905 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
906 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
907 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
908 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
909 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
910 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
911 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
912 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
913 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
914 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
915 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
916 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
917 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
918 *
919 * @note (*) Availability depends on devices.
920 * @retval None
921 */
922__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
923{
924 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
925
926 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
927}
928
929/**
930 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
931 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
932 * @param DMAMUXx DMAMUXx Instance
933 * @param Channel This parameter can be one of the following values:
934 * @arg @ref LL_DMAMUX_CHANNEL_0
935 * @arg @ref LL_DMAMUX_CHANNEL_1
936 * @arg @ref LL_DMAMUX_CHANNEL_2
937 * @arg @ref LL_DMAMUX_CHANNEL_3
938 * @arg @ref LL_DMAMUX_CHANNEL_4
939 * @arg @ref LL_DMAMUX_CHANNEL_5
940 * @arg @ref LL_DMAMUX_CHANNEL_6
941 * @arg @ref LL_DMAMUX_CHANNEL_7
942 * @arg @ref LL_DMAMUX_CHANNEL_8
943 * @arg @ref LL_DMAMUX_CHANNEL_9
944 * @arg @ref LL_DMAMUX_CHANNEL_10
945 * @arg @ref LL_DMAMUX_CHANNEL_11
946 * @arg @ref LL_DMAMUX_CHANNEL_12
947 * @arg @ref LL_DMAMUX_CHANNEL_13
948 * @arg @ref LL_DMAMUX_CHANNEL_14
949 * @arg @ref LL_DMAMUX_CHANNEL_15
950 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
951 * @retval None
952 */
953__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
954{
955 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
956
957 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
958}
959
960/**
961 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
962 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
963 * @param DMAMUXx DMAMUXx Instance
964 * @param Channel This parameter can be one of the following values:
965 * @arg @ref LL_DMAMUX_CHANNEL_0
966 * @arg @ref LL_DMAMUX_CHANNEL_1
967 * @arg @ref LL_DMAMUX_CHANNEL_2
968 * @arg @ref LL_DMAMUX_CHANNEL_3
969 * @arg @ref LL_DMAMUX_CHANNEL_4
970 * @arg @ref LL_DMAMUX_CHANNEL_5
971 * @arg @ref LL_DMAMUX_CHANNEL_6
972 * @arg @ref LL_DMAMUX_CHANNEL_7
973 * @arg @ref LL_DMAMUX_CHANNEL_8
974 * @arg @ref LL_DMAMUX_CHANNEL_9
975 * @arg @ref LL_DMAMUX_CHANNEL_10
976 * @arg @ref LL_DMAMUX_CHANNEL_11
977 * @arg @ref LL_DMAMUX_CHANNEL_12
978 * @arg @ref LL_DMAMUX_CHANNEL_13
979 * @arg @ref LL_DMAMUX_CHANNEL_14
980 * @arg @ref LL_DMAMUX_CHANNEL_15
981 * @retval Between Min_Data = 1 and Max_Data = 32
982 */
983__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
984{
985 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
986
987 return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
988}
989
990/**
991 * @brief Set the polarity of the signal on which the DMA request is synchronized.
992 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
993 * @param DMAMUXx DMAMUXx Instance
994 * @param Channel This parameter can be one of the following values:
995 * @arg @ref LL_DMAMUX_CHANNEL_0
996 * @arg @ref LL_DMAMUX_CHANNEL_1
997 * @arg @ref LL_DMAMUX_CHANNEL_2
998 * @arg @ref LL_DMAMUX_CHANNEL_3
999 * @arg @ref LL_DMAMUX_CHANNEL_4
1000 * @arg @ref LL_DMAMUX_CHANNEL_5
1001 * @arg @ref LL_DMAMUX_CHANNEL_6
1002 * @arg @ref LL_DMAMUX_CHANNEL_7
1003 * @arg @ref LL_DMAMUX_CHANNEL_8
1004 * @arg @ref LL_DMAMUX_CHANNEL_9
1005 * @arg @ref LL_DMAMUX_CHANNEL_10
1006 * @arg @ref LL_DMAMUX_CHANNEL_11
1007 * @arg @ref LL_DMAMUX_CHANNEL_12
1008 * @arg @ref LL_DMAMUX_CHANNEL_13
1009 * @arg @ref LL_DMAMUX_CHANNEL_14
1010 * @arg @ref LL_DMAMUX_CHANNEL_15
1011 * @param Polarity This parameter can be one of the following values:
1012 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
1013 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
1014 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
1015 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
1016 * @retval None
1017 */
1018__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
1019{
1020 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1021
1022 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
1023}
1024
1025/**
1026 * @brief Get the polarity of the signal on which the DMA request is synchronized.
1027 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
1028 * @param DMAMUXx DMAMUXx Instance
1029 * @param Channel This parameter can be one of the following values:
1030 * @arg @ref LL_DMAMUX_CHANNEL_0
1031 * @arg @ref LL_DMAMUX_CHANNEL_1
1032 * @arg @ref LL_DMAMUX_CHANNEL_2
1033 * @arg @ref LL_DMAMUX_CHANNEL_3
1034 * @arg @ref LL_DMAMUX_CHANNEL_4
1035 * @arg @ref LL_DMAMUX_CHANNEL_5
1036 * @arg @ref LL_DMAMUX_CHANNEL_6
1037 * @arg @ref LL_DMAMUX_CHANNEL_7
1038 * @arg @ref LL_DMAMUX_CHANNEL_8
1039 * @arg @ref LL_DMAMUX_CHANNEL_9
1040 * @arg @ref LL_DMAMUX_CHANNEL_10
1041 * @arg @ref LL_DMAMUX_CHANNEL_11
1042 * @arg @ref LL_DMAMUX_CHANNEL_12
1043 * @arg @ref LL_DMAMUX_CHANNEL_13
1044 * @arg @ref LL_DMAMUX_CHANNEL_14
1045 * @arg @ref LL_DMAMUX_CHANNEL_15
1046 * @retval Returned value can be one of the following values:
1047 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
1048 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
1049 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
1050 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
1051 */
1052__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1053{
1054 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1055
1056 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
1057}
1058
1059/**
1060 * @brief Enable the Event Generation on DMAMUX channel x.
1061 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
1062 * @param DMAMUXx DMAMUXx Instance
1063 * @param Channel This parameter can be one of the following values:
1064 * @arg @ref LL_DMAMUX_CHANNEL_0
1065 * @arg @ref LL_DMAMUX_CHANNEL_1
1066 * @arg @ref LL_DMAMUX_CHANNEL_2
1067 * @arg @ref LL_DMAMUX_CHANNEL_3
1068 * @arg @ref LL_DMAMUX_CHANNEL_4
1069 * @arg @ref LL_DMAMUX_CHANNEL_5
1070 * @arg @ref LL_DMAMUX_CHANNEL_6
1071 * @arg @ref LL_DMAMUX_CHANNEL_7
1072 * @arg @ref LL_DMAMUX_CHANNEL_8
1073 * @arg @ref LL_DMAMUX_CHANNEL_9
1074 * @arg @ref LL_DMAMUX_CHANNEL_10
1075 * @arg @ref LL_DMAMUX_CHANNEL_11
1076 * @arg @ref LL_DMAMUX_CHANNEL_12
1077 * @arg @ref LL_DMAMUX_CHANNEL_13
1078 * @arg @ref LL_DMAMUX_CHANNEL_14
1079 * @arg @ref LL_DMAMUX_CHANNEL_15
1080 * @retval None
1081 */
1082__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1083{
1084 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1085
1086 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
1087}
1088
1089/**
1090 * @brief Disable the Event Generation on DMAMUX channel x.
1091 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
1092 * @param DMAMUXx DMAMUXx Instance
1093 * @param Channel This parameter can be one of the following values:
1094 * @arg @ref LL_DMAMUX_CHANNEL_0
1095 * @arg @ref LL_DMAMUX_CHANNEL_1
1096 * @arg @ref LL_DMAMUX_CHANNEL_2
1097 * @arg @ref LL_DMAMUX_CHANNEL_3
1098 * @arg @ref LL_DMAMUX_CHANNEL_4
1099 * @arg @ref LL_DMAMUX_CHANNEL_5
1100 * @arg @ref LL_DMAMUX_CHANNEL_6
1101 * @arg @ref LL_DMAMUX_CHANNEL_7
1102 * @arg @ref LL_DMAMUX_CHANNEL_8
1103 * @arg @ref LL_DMAMUX_CHANNEL_9
1104 * @arg @ref LL_DMAMUX_CHANNEL_10
1105 * @arg @ref LL_DMAMUX_CHANNEL_11
1106 * @arg @ref LL_DMAMUX_CHANNEL_12
1107 * @arg @ref LL_DMAMUX_CHANNEL_13
1108 * @arg @ref LL_DMAMUX_CHANNEL_14
1109 * @arg @ref LL_DMAMUX_CHANNEL_15
1110 * @retval None
1111 */
1112__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1113{
1114 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1115
1116 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
1117}
1118
1119/**
1120 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
1121 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
1122 * @param DMAMUXx DMAMUXx Instance
1123 * @param Channel This parameter can be one of the following values:
1124 * @arg @ref LL_DMAMUX_CHANNEL_0
1125 * @arg @ref LL_DMAMUX_CHANNEL_1
1126 * @arg @ref LL_DMAMUX_CHANNEL_2
1127 * @arg @ref LL_DMAMUX_CHANNEL_3
1128 * @arg @ref LL_DMAMUX_CHANNEL_4
1129 * @arg @ref LL_DMAMUX_CHANNEL_5
1130 * @arg @ref LL_DMAMUX_CHANNEL_6
1131 * @arg @ref LL_DMAMUX_CHANNEL_7
1132 * @arg @ref LL_DMAMUX_CHANNEL_8
1133 * @arg @ref LL_DMAMUX_CHANNEL_9
1134 * @arg @ref LL_DMAMUX_CHANNEL_10
1135 * @arg @ref LL_DMAMUX_CHANNEL_11
1136 * @arg @ref LL_DMAMUX_CHANNEL_12
1137 * @arg @ref LL_DMAMUX_CHANNEL_13
1138 * @arg @ref LL_DMAMUX_CHANNEL_14
1139 * @arg @ref LL_DMAMUX_CHANNEL_15
1140 * @retval State of bit (1 or 0).
1141 */
1142__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1143{
1144 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1145
1146 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
1147}
1148
1149/**
1150 * @brief Enable the synchronization mode.
1151 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
1152 * @param DMAMUXx DMAMUXx Instance
1153 * @param Channel This parameter can be one of the following values:
1154 * @arg @ref LL_DMAMUX_CHANNEL_0
1155 * @arg @ref LL_DMAMUX_CHANNEL_1
1156 * @arg @ref LL_DMAMUX_CHANNEL_2
1157 * @arg @ref LL_DMAMUX_CHANNEL_3
1158 * @arg @ref LL_DMAMUX_CHANNEL_4
1159 * @arg @ref LL_DMAMUX_CHANNEL_5
1160 * @arg @ref LL_DMAMUX_CHANNEL_6
1161 * @arg @ref LL_DMAMUX_CHANNEL_7
1162 * @arg @ref LL_DMAMUX_CHANNEL_8
1163 * @arg @ref LL_DMAMUX_CHANNEL_9
1164 * @arg @ref LL_DMAMUX_CHANNEL_10
1165 * @arg @ref LL_DMAMUX_CHANNEL_11
1166 * @arg @ref LL_DMAMUX_CHANNEL_12
1167 * @arg @ref LL_DMAMUX_CHANNEL_13
1168 * @arg @ref LL_DMAMUX_CHANNEL_14
1169 * @arg @ref LL_DMAMUX_CHANNEL_15
1170 * @retval None
1171 */
1172__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1173{
1174 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1175
1176 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1177}
1178
1179/**
1180 * @brief Disable the synchronization mode.
1181 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
1182 * @param DMAMUXx DMAMUXx Instance
1183 * @param Channel This parameter can be one of the following values:
1184 * @arg @ref LL_DMAMUX_CHANNEL_0
1185 * @arg @ref LL_DMAMUX_CHANNEL_1
1186 * @arg @ref LL_DMAMUX_CHANNEL_2
1187 * @arg @ref LL_DMAMUX_CHANNEL_3
1188 * @arg @ref LL_DMAMUX_CHANNEL_4
1189 * @arg @ref LL_DMAMUX_CHANNEL_5
1190 * @arg @ref LL_DMAMUX_CHANNEL_6
1191 * @arg @ref LL_DMAMUX_CHANNEL_7
1192 * @arg @ref LL_DMAMUX_CHANNEL_8
1193 * @arg @ref LL_DMAMUX_CHANNEL_9
1194 * @arg @ref LL_DMAMUX_CHANNEL_10
1195 * @arg @ref LL_DMAMUX_CHANNEL_11
1196 * @arg @ref LL_DMAMUX_CHANNEL_12
1197 * @arg @ref LL_DMAMUX_CHANNEL_13
1198 * @arg @ref LL_DMAMUX_CHANNEL_14
1199 * @arg @ref LL_DMAMUX_CHANNEL_15
1200 * @retval None
1201 */
1202__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1203{
1204 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1205
1206 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1207}
1208
1209/**
1210 * @brief Check if the synchronization mode is enabled or disabled.
1211 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
1212 * @param DMAMUXx DMAMUXx Instance
1213 * @param Channel This parameter can be one of the following values:
1214 * @arg @ref LL_DMAMUX_CHANNEL_0
1215 * @arg @ref LL_DMAMUX_CHANNEL_1
1216 * @arg @ref LL_DMAMUX_CHANNEL_2
1217 * @arg @ref LL_DMAMUX_CHANNEL_3
1218 * @arg @ref LL_DMAMUX_CHANNEL_4
1219 * @arg @ref LL_DMAMUX_CHANNEL_5
1220 * @arg @ref LL_DMAMUX_CHANNEL_6
1221 * @arg @ref LL_DMAMUX_CHANNEL_7
1222 * @arg @ref LL_DMAMUX_CHANNEL_8
1223 * @arg @ref LL_DMAMUX_CHANNEL_9
1224 * @arg @ref LL_DMAMUX_CHANNEL_10
1225 * @arg @ref LL_DMAMUX_CHANNEL_11
1226 * @arg @ref LL_DMAMUX_CHANNEL_12
1227 * @arg @ref LL_DMAMUX_CHANNEL_13
1228 * @arg @ref LL_DMAMUX_CHANNEL_14
1229 * @arg @ref LL_DMAMUX_CHANNEL_15
1230 * @retval State of bit (1 or 0).
1231 */
1232__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1233{
1234 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1235
1236 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
1237}
1238
1239/**
1240 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
1241 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
1242 * @param DMAMUXx DMAMUXx Instance
1243 * @param Channel This parameter can be one of the following values:
1244 * @arg @ref LL_DMAMUX_CHANNEL_0
1245 * @arg @ref LL_DMAMUX_CHANNEL_1
1246 * @arg @ref LL_DMAMUX_CHANNEL_2
1247 * @arg @ref LL_DMAMUX_CHANNEL_3
1248 * @arg @ref LL_DMAMUX_CHANNEL_4
1249 * @arg @ref LL_DMAMUX_CHANNEL_5
1250 * @arg @ref LL_DMAMUX_CHANNEL_6
1251 * @arg @ref LL_DMAMUX_CHANNEL_7
1252 * @arg @ref LL_DMAMUX_CHANNEL_8
1253 * @arg @ref LL_DMAMUX_CHANNEL_9
1254 * @arg @ref LL_DMAMUX_CHANNEL_10
1255 * @arg @ref LL_DMAMUX_CHANNEL_11
1256 * @arg @ref LL_DMAMUX_CHANNEL_12
1257 * @arg @ref LL_DMAMUX_CHANNEL_13
1258 * @arg @ref LL_DMAMUX_CHANNEL_14
1259 * @arg @ref LL_DMAMUX_CHANNEL_15
1260 * @param SyncID This parameter can be one of the following values:
1261 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1262 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1263 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1264 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1265 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1266 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1267 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1268 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1269 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1270 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1271 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1272 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1273 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1274 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1275 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1276 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1277 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1278 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1279 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1280 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1281 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1282 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1283 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1284 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1285 * @retval None
1286 */
1287__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
1288{
1289 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1290
1291 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
1292}
1293
1294/**
1295 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
1296 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
1297 * @param DMAMUXx DMAMUXx Instance
1298 * @param Channel This parameter can be one of the following values:
1299 * @arg @ref LL_DMAMUX_CHANNEL_0
1300 * @arg @ref LL_DMAMUX_CHANNEL_1
1301 * @arg @ref LL_DMAMUX_CHANNEL_2
1302 * @arg @ref LL_DMAMUX_CHANNEL_3
1303 * @arg @ref LL_DMAMUX_CHANNEL_4
1304 * @arg @ref LL_DMAMUX_CHANNEL_5
1305 * @arg @ref LL_DMAMUX_CHANNEL_6
1306 * @arg @ref LL_DMAMUX_CHANNEL_7
1307 * @arg @ref LL_DMAMUX_CHANNEL_8
1308 * @arg @ref LL_DMAMUX_CHANNEL_9
1309 * @arg @ref LL_DMAMUX_CHANNEL_10
1310 * @arg @ref LL_DMAMUX_CHANNEL_11
1311 * @arg @ref LL_DMAMUX_CHANNEL_12
1312 * @arg @ref LL_DMAMUX_CHANNEL_13
1313 * @arg @ref LL_DMAMUX_CHANNEL_14
1314 * @arg @ref LL_DMAMUX_CHANNEL_15
1315 * @retval Returned value can be one of the following values:
1316 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1317 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1318 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1319 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1320 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1321 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1322 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1323 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1324 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1325 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1326 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1327 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1328 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1329 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1330 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1331 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1332 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1333 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1334 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1335 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1336 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1337 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1338 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1339 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1340 */
1341__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1342{
1343 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1344
1345 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
1346}
1347
1348/**
1349 * @brief Enable the Request Generator.
1350 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1351 * @param DMAMUXx DMAMUXx Instance
1352 * @param RequestGenChannel This parameter can be one of the following values:
1353 * @arg @ref LL_DMAMUX_REQ_GEN_0
1354 * @arg @ref LL_DMAMUX_REQ_GEN_1
1355 * @arg @ref LL_DMAMUX_REQ_GEN_2
1356 * @arg @ref LL_DMAMUX_REQ_GEN_3
1357 * @arg @ref LL_DMAMUX_REQ_GEN_4
1358 * @arg @ref LL_DMAMUX_REQ_GEN_5
1359 * @arg @ref LL_DMAMUX_REQ_GEN_6
1360 * @arg @ref LL_DMAMUX_REQ_GEN_7
1361 * @retval None
1362 */
1363__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1364{
1365 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1366
1367 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1368}
1369
1370/**
1371 * @brief Disable the Request Generator.
1372 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1373 * @param DMAMUXx DMAMUXx Instance
1374 * @param RequestGenChannel This parameter can be one of the following values:
1375 * @arg @ref LL_DMAMUX_REQ_GEN_0
1376 * @arg @ref LL_DMAMUX_REQ_GEN_1
1377 * @arg @ref LL_DMAMUX_REQ_GEN_2
1378 * @arg @ref LL_DMAMUX_REQ_GEN_3
1379 * @retval None
1380 */
1381__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1382{
1383 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1384
1385 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1386}
1387
1388/**
1389 * @brief Check if the Request Generator is enabled or disabled.
1390 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1391 * @param DMAMUXx DMAMUXx Instance
1392 * @param RequestGenChannel This parameter can be one of the following values:
1393 * @arg @ref LL_DMAMUX_REQ_GEN_0
1394 * @arg @ref LL_DMAMUX_REQ_GEN_1
1395 * @arg @ref LL_DMAMUX_REQ_GEN_2
1396 * @arg @ref LL_DMAMUX_REQ_GEN_3
1397 * @arg @ref LL_DMAMUX_REQ_GEN_4
1398 * @arg @ref LL_DMAMUX_REQ_GEN_5
1399 * @arg @ref LL_DMAMUX_REQ_GEN_6
1400 * @arg @ref LL_DMAMUX_REQ_GEN_7
1401 * @retval State of bit (1 or 0).
1402 */
1403__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1404{
1405 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1406
1407 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1408}
1409
1410/**
1411 * @brief Set the polarity of the signal on which the DMA request is generated.
1412 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1413 * @param DMAMUXx DMAMUXx Instance
1414 * @param RequestGenChannel This parameter can be one of the following values:
1415 * @arg @ref LL_DMAMUX_REQ_GEN_0
1416 * @arg @ref LL_DMAMUX_REQ_GEN_1
1417 * @arg @ref LL_DMAMUX_REQ_GEN_2
1418 * @arg @ref LL_DMAMUX_REQ_GEN_3
1419 * @arg @ref LL_DMAMUX_REQ_GEN_4
1420 * @arg @ref LL_DMAMUX_REQ_GEN_5
1421 * @arg @ref LL_DMAMUX_REQ_GEN_6
1422 * @arg @ref LL_DMAMUX_REQ_GEN_7
1423 * @param Polarity This parameter can be one of the following values:
1424 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1425 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1426 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1427 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1428 * @retval None
1429 */
1430__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
1431{
1432 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1433
1434 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1435}
1436
1437/**
1438 * @brief Get the polarity of the signal on which the DMA request is generated.
1439 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1440 * @param DMAMUXx DMAMUXx Instance
1441 * @param RequestGenChannel This parameter can be one of the following values:
1442 * @arg @ref LL_DMAMUX_REQ_GEN_0
1443 * @arg @ref LL_DMAMUX_REQ_GEN_1
1444 * @arg @ref LL_DMAMUX_REQ_GEN_2
1445 * @arg @ref LL_DMAMUX_REQ_GEN_3
1446 * @arg @ref LL_DMAMUX_REQ_GEN_4
1447 * @arg @ref LL_DMAMUX_REQ_GEN_5
1448 * @arg @ref LL_DMAMUX_REQ_GEN_6
1449 * @arg @ref LL_DMAMUX_REQ_GEN_7
1450 * @retval Returned value can be one of the following values:
1451 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1452 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1453 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1454 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1455 */
1456__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1457{
1458 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1459
1460 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
1461}
1462
1463/**
1464 * @brief Set the number of DMA request that will be autorized after a generation event.
1465 * @note This field can only be written when Generator is disabled.
1466 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1467 * @param DMAMUXx DMAMUXx Instance
1468 * @param RequestGenChannel This parameter can be one of the following values:
1469 * @arg @ref LL_DMAMUX_REQ_GEN_0
1470 * @arg @ref LL_DMAMUX_REQ_GEN_1
1471 * @arg @ref LL_DMAMUX_REQ_GEN_2
1472 * @arg @ref LL_DMAMUX_REQ_GEN_3
1473 * @arg @ref LL_DMAMUX_REQ_GEN_4
1474 * @arg @ref LL_DMAMUX_REQ_GEN_5
1475 * @arg @ref LL_DMAMUX_REQ_GEN_6
1476 * @arg @ref LL_DMAMUX_REQ_GEN_7
1477 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1478 * @retval None
1479 */
1480__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
1481{
1482 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1483
1484 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1485}
1486
1487/**
1488 * @brief Get the number of DMA request that will be autorized after a generation event.
1489 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1490 * @param DMAMUXx DMAMUXx Instance
1491 * @param RequestGenChannel This parameter can be one of the following values:
1492 * @arg @ref LL_DMAMUX_REQ_GEN_0
1493 * @arg @ref LL_DMAMUX_REQ_GEN_1
1494 * @arg @ref LL_DMAMUX_REQ_GEN_2
1495 * @arg @ref LL_DMAMUX_REQ_GEN_3
1496 * @arg @ref LL_DMAMUX_REQ_GEN_4
1497 * @arg @ref LL_DMAMUX_REQ_GEN_5
1498 * @arg @ref LL_DMAMUX_REQ_GEN_6
1499 * @arg @ref LL_DMAMUX_REQ_GEN_7
1500 * @retval Between Min_Data = 1 and Max_Data = 32
1501 */
1502__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1503{
1504 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1505
1506 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1507}
1508
1509/**
1510 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1511 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1512 * @param DMAMUXx DMAMUXx Instance
1513 * @param RequestGenChannel This parameter can be one of the following values:
1514 * @arg @ref LL_DMAMUX_REQ_GEN_0
1515 * @arg @ref LL_DMAMUX_REQ_GEN_1
1516 * @arg @ref LL_DMAMUX_REQ_GEN_2
1517 * @arg @ref LL_DMAMUX_REQ_GEN_3
1518 * @arg @ref LL_DMAMUX_REQ_GEN_4
1519 * @arg @ref LL_DMAMUX_REQ_GEN_5
1520 * @arg @ref LL_DMAMUX_REQ_GEN_6
1521 * @arg @ref LL_DMAMUX_REQ_GEN_7
1522 * @param RequestSignalID This parameter can be one of the following values:
1523 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
1524 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
1525 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
1526 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
1527 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
1528 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
1529 * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
1530 * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
1531 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
1532 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
1533 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
1534 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
1535 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
1536 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
1537 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
1538 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
1539 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
1540 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
1541 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
1542 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
1543 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
1544 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
1545 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
1546 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
1547 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
1548 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
1549 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
1550 * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
1551 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
1552 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
1553 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
1554 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
1555 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
1556 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
1557 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
1558 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
1559 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
1560 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
1561 * @note (*) Availability depends on devices.
1562 * @retval None
1563 */
1564__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
1565{
1566 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1567
1568 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1569}
1570
1571/**
1572 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1573 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1574 * @param DMAMUXx DMAMUXx Instance
1575 * @param RequestGenChannel This parameter can be one of the following values:
1576 * @arg @ref LL_DMAMUX_REQ_GEN_0
1577 * @arg @ref LL_DMAMUX_REQ_GEN_1
1578 * @arg @ref LL_DMAMUX_REQ_GEN_2
1579 * @arg @ref LL_DMAMUX_REQ_GEN_3
1580 * @arg @ref LL_DMAMUX_REQ_GEN_4
1581 * @arg @ref LL_DMAMUX_REQ_GEN_5
1582 * @arg @ref LL_DMAMUX_REQ_GEN_6
1583 * @arg @ref LL_DMAMUX_REQ_GEN_7
1584 * @retval Returned value can be one of the following values:
1585 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1586 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1587 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1588 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1589 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1590 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1591 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1592 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1593 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1594 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1595 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1596 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1597 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1598 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1599 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1600 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1601 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1602 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1603 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1604 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1605 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1606 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1607 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1608 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1609 */
1610__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1611{
1612 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1613
1614 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
1615}
1616
1617/**
1618 * @}
1619 */
1620
1621/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1622 * @{
1623 */
1624
1625/**
1626 * @brief Get Synchronization Event Overrun Flag Channel 0.
1627 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1628 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1629 * @retval State of bit (1 or 0).
1630 */
1631__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1632{
1633 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1634
1635 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1636}
1637
1638/**
1639 * @brief Get Synchronization Event Overrun Flag Channel 1.
1640 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1641 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1642 * @retval State of bit (1 or 0).
1643 */
1644__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1645{
1646 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1647
1648 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1649}
1650
1651/**
1652 * @brief Get Synchronization Event Overrun Flag Channel 2.
1653 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1654 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1655 * @retval State of bit (1 or 0).
1656 */
1657__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1658{
1659 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1660
1661 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1662}
1663
1664/**
1665 * @brief Get Synchronization Event Overrun Flag Channel 3.
1666 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1667 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1668 * @retval State of bit (1 or 0).
1669 */
1670__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1671{
1672 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1673
1674 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1675}
1676
1677/**
1678 * @brief Get Synchronization Event Overrun Flag Channel 4.
1679 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1680 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1681 * @retval State of bit (1 or 0).
1682 */
1683__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1684{
1685 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1686
1687 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1688}
1689
1690/**
1691 * @brief Get Synchronization Event Overrun Flag Channel 5.
1692 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1693 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1694 * @retval State of bit (1 or 0).
1695 */
1696__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
1697{
1698 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1699
1700 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1701}
1702
1703/**
1704 * @brief Get Synchronization Event Overrun Flag Channel 6.
1705 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1706 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1707 * @retval State of bit (1 or 0).
1708 */
1709__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
1710{
1711 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1712
1713 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1714}
1715
1716/**
1717 * @brief Get Synchronization Event Overrun Flag Channel 7.
1718 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1719 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1720 * @retval State of bit (1 or 0).
1721 */
1722__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
1723{
1724 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1725
1726 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1727}
1728
1729/**
1730 * @brief Get Synchronization Event Overrun Flag Channel 8.
1731 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1732 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1733 * @retval State of bit (1 or 0).
1734 */
1735__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
1736{
1737 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1738
1739 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1740}
1741
1742/**
1743 * @brief Get Synchronization Event Overrun Flag Channel 9.
1744 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1745 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1746 * @retval State of bit (1 or 0).
1747 */
1748__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
1749{
1750 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1751
1752 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1753}
1754
1755/**
1756 * @brief Get Synchronization Event Overrun Flag Channel 10.
1757 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1758 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1759 * @retval State of bit (1 or 0).
1760 */
1761__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
1762{
1763 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1764
1765 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1766}
1767
1768/**
1769 * @brief Get Synchronization Event Overrun Flag Channel 11.
1770 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1771 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1772 * @retval State of bit (1 or 0).
1773 */
1774__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
1775{
1776 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1777
1778 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1779}
1780
1781/**
1782 * @brief Get Synchronization Event Overrun Flag Channel 12.
1783 * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
1784 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1785 * @retval State of bit (1 or 0).
1786 */
1787__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx)
1788{
1789 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1790
1791 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
1792}
1793
1794/**
1795 * @brief Get Synchronization Event Overrun Flag Channel 13.
1796 * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
1797 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1798 * @retval State of bit (1 or 0).
1799 */
1800__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx)
1801{
1802 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1803
1804 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
1805}
1806
1807/**
1808 * @brief Get Synchronization Event Overrun Flag Channel 14.
1809 * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14
1810 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1811 * @retval State of bit (1 or 0).
1812 */
1813__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx)
1814{
1815 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1816
1817 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
1818}
1819
1820/**
1821 * @brief Get Synchronization Event Overrun Flag Channel 15.
1822 * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15
1823 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1824 * @retval State of bit (1 or 0).
1825 */
1826__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx)
1827{
1828 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1829
1830 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
1831}
1832
1833/**
1834 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1835 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1836 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1837 * @retval State of bit (1 or 0).
1838 */
1839__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1840{
1841 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1842
1843 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1844}
1845
1846/**
1847 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1848 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1849 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1850 * @retval State of bit (1 or 0).
1851 */
1852__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1853{
1854 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1855
1856 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1857}
1858
1859/**
1860 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1861 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1862 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1863 * @retval State of bit (1 or 0).
1864 */
1865__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1866{
1867 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1868
1869 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1870}
1871
1872/**
1873 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1874 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1875 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1876 * @retval State of bit (1 or 0).
1877 */
1878__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1879{
1880 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1881
1882 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1883}
1884
1885/**
1886 * @brief Get Request Generator 4 Trigger Event Overrun Flag.
1887 * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4
1888 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1889 * @retval State of bit (1 or 0).
1890 */
1891__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1892{
1893 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1894
1895 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
1896}
1897
1898/**
1899 * @brief Get Request Generator 5 Trigger Event Overrun Flag.
1900 * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5
1901 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1902 * @retval State of bit (1 or 0).
1903 */
1904__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
1905{
1906 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1907
1908 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
1909}
1910
1911/**
1912 * @brief Get Request Generator 6 Trigger Event Overrun Flag.
1913 * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6
1914 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1915 * @retval State of bit (1 or 0).
1916 */
1917__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
1918{
1919 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1920
1921 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
1922}
1923
1924/**
1925 * @brief Get Request Generator 7 Trigger Event Overrun Flag.
1926 * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7
1927 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1928 * @retval State of bit (1 or 0).
1929 */
1930__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
1931{
1932 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1933
1934 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
1935}
1936
1937/**
1938 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1939 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1940 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1941 * @retval None
1942 */
1943__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1944{
1945 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1946
1947 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
1948}
1949
1950/**
1951 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1952 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1953 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1954 * @retval None
1955 */
1956__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1957{
1958 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1959
1960 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
1961}
1962
1963/**
1964 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1965 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1966 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1967 * @retval None
1968 */
1969__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1970{
1971 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1972
1973 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
1974}
1975
1976/**
1977 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1978 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1979 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1980 * @retval None
1981 */
1982__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1983{
1984 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1985
1986 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
1987}
1988
1989/**
1990 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1991 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1992 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1993 * @retval None
1994 */
1995__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1996{
1997 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1998
1999 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
2000}
2001
2002/**
2003 * @brief Clear Synchronization Event Overrun Flag Channel 5.
2004 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
2005 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2006 * @retval None
2007 */
2008__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
2009{
2010 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2011
2012 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
2013}
2014
2015/**
2016 * @brief Clear Synchronization Event Overrun Flag Channel 6.
2017 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
2018 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2019 * @retval None
2020 */
2021__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
2022{
2023 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2024
2025 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
2026}
2027
2028/**
2029 * @brief Clear Synchronization Event Overrun Flag Channel 7.
2030 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
2031 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2032 * @retval None
2033 */
2034__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
2035{
2036 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2037
2038 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
2039}
2040
2041/**
2042 * @brief Clear Synchronization Event Overrun Flag Channel 8.
2043 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
2044 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2045 * @retval None
2046 */
2047__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
2048{
2049 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2050
2051 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
2052}
2053
2054/**
2055 * @brief Clear Synchronization Event Overrun Flag Channel 9.
2056 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
2057 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2058 * @retval None
2059 */
2060__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
2061{
2062 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2063
2064 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
2065}
2066
2067/**
2068 * @brief Clear Synchronization Event Overrun Flag Channel 10.
2069 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
2070 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2071 * @retval None
2072 */
2073__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
2074{
2075 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2076
2077 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
2078}
2079
2080/**
2081 * @brief Clear Synchronization Event Overrun Flag Channel 11.
2082 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
2083 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2084 * @retval None
2085 */
2086__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
2087{
2088 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2089
2090 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
2091}
2092
2093/**
2094 * @brief Clear Synchronization Event Overrun Flag Channel 12.
2095 * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
2096 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2097 * @retval None
2098 */
2099__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx)
2100{
2101 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2102
2103 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
2104}
2105
2106/**
2107 * @brief Clear Synchronization Event Overrun Flag Channel 13.
2108 * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
2109 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2110 * @retval None
2111 */
2112__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx)
2113{
2114 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2115
2116 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
2117}
2118
2119/**
2120 * @brief Clear Synchronization Event Overrun Flag Channel 14.
2121 * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
2122 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2123 * @retval None
2124 */
2125__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx)
2126{
2127 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2128
2129 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
2130}
2131
2132/**
2133 * @brief Clear Synchronization Event Overrun Flag Channel 15.
2134 * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
2135 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2136 * @retval None
2137 */
2138__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx)
2139{
2140 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2141
2142 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
2143}
2144
2145/**
2146 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
2147 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
2148 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2149 * @retval None
2150 */
2151__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
2152{
2153 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2154
2155 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
2156}
2157
2158/**
2159 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
2160 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
2161 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2162 * @retval None
2163 */
2164__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
2165{
2166 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2167
2168 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
2169}
2170
2171/**
2172 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
2173 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
2174 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2175 * @retval None
2176 */
2177__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
2178{
2179 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2180
2181 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
2182}
2183
2184/**
2185 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
2186 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
2187 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2188 * @retval None
2189 */
2190__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
2191{
2192 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2193
2194 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
2195}
2196
2197/**
2198 * @brief Clear Request Generator 4 Trigger Event Overrun Flag.
2199 * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4
2200 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2201 * @retval None
2202 */
2203__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
2204{
2205 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2206
2207 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
2208}
2209
2210/**
2211 * @brief Clear Request Generator 5 Trigger Event Overrun Flag.
2212 * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5
2213 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2214 * @retval None
2215 */
2216__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
2217{
2218 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2219
2220 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
2221}
2222
2223/**
2224 * @brief Clear Request Generator 6 Trigger Event Overrun Flag.
2225 * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6
2226 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2227 * @retval None
2228 */
2229__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
2230{
2231 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2232
2233 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
2234}
2235
2236/**
2237 * @brief Clear Request Generator 7 Trigger Event Overrun Flag.
2238 * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7
2239 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2240 * @retval None
2241 */
2242__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
2243{
2244 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2245
2246 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
2247}
2248
2249/**
2250 * @}
2251 */
2252
2253/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
2254 * @{
2255 */
2256
2257/**
2258 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2259 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
2260 * @param DMAMUXx DMAMUXx Instance
2261 * @param Channel This parameter can be one of the following values:
2262 * @arg @ref LL_DMAMUX_CHANNEL_0
2263 * @arg @ref LL_DMAMUX_CHANNEL_1
2264 * @arg @ref LL_DMAMUX_CHANNEL_2
2265 * @arg @ref LL_DMAMUX_CHANNEL_3
2266 * @arg @ref LL_DMAMUX_CHANNEL_4
2267 * @arg @ref LL_DMAMUX_CHANNEL_5
2268 * @arg @ref LL_DMAMUX_CHANNEL_6
2269 * @arg @ref LL_DMAMUX_CHANNEL_7
2270 * @arg @ref LL_DMAMUX_CHANNEL_8
2271 * @arg @ref LL_DMAMUX_CHANNEL_9
2272 * @arg @ref LL_DMAMUX_CHANNEL_10
2273 * @arg @ref LL_DMAMUX_CHANNEL_11
2274 * @arg @ref LL_DMAMUX_CHANNEL_12
2275 * @arg @ref LL_DMAMUX_CHANNEL_13
2276 * @arg @ref LL_DMAMUX_CHANNEL_14
2277 * @arg @ref LL_DMAMUX_CHANNEL_15
2278 * @retval None
2279 */
2280__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2281{
2282 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2283
2284 SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2285}
2286
2287/**
2288 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2289 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
2290 * @param DMAMUXx DMAMUXx Instance
2291 * @param Channel This parameter can be one of the following values:
2292 * @arg @ref LL_DMAMUX_CHANNEL_0
2293 * @arg @ref LL_DMAMUX_CHANNEL_1
2294 * @arg @ref LL_DMAMUX_CHANNEL_2
2295 * @arg @ref LL_DMAMUX_CHANNEL_3
2296 * @arg @ref LL_DMAMUX_CHANNEL_4
2297 * @arg @ref LL_DMAMUX_CHANNEL_5
2298 * @arg @ref LL_DMAMUX_CHANNEL_6
2299 * @arg @ref LL_DMAMUX_CHANNEL_7
2300 * @arg @ref LL_DMAMUX_CHANNEL_8
2301 * @arg @ref LL_DMAMUX_CHANNEL_9
2302 * @arg @ref LL_DMAMUX_CHANNEL_10
2303 * @arg @ref LL_DMAMUX_CHANNEL_11
2304 * @arg @ref LL_DMAMUX_CHANNEL_12
2305 * @arg @ref LL_DMAMUX_CHANNEL_13
2306 * @arg @ref LL_DMAMUX_CHANNEL_14
2307 * @arg @ref LL_DMAMUX_CHANNEL_15
2308 * @retval None
2309 */
2310__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2311{
2312 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2313
2314 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2315}
2316
2317/**
2318 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2319 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
2320 * @param DMAMUXx DMAMUXx Instance
2321 * @param Channel This parameter can be one of the following values:
2322 * @arg @ref LL_DMAMUX_CHANNEL_0
2323 * @arg @ref LL_DMAMUX_CHANNEL_1
2324 * @arg @ref LL_DMAMUX_CHANNEL_2
2325 * @arg @ref LL_DMAMUX_CHANNEL_3
2326 * @arg @ref LL_DMAMUX_CHANNEL_4
2327 * @arg @ref LL_DMAMUX_CHANNEL_5
2328 * @arg @ref LL_DMAMUX_CHANNEL_6
2329 * @arg @ref LL_DMAMUX_CHANNEL_7
2330 * @arg @ref LL_DMAMUX_CHANNEL_8
2331 * @arg @ref LL_DMAMUX_CHANNEL_9
2332 * @arg @ref LL_DMAMUX_CHANNEL_10
2333 * @arg @ref LL_DMAMUX_CHANNEL_11
2334 * @arg @ref LL_DMAMUX_CHANNEL_12
2335 * @arg @ref LL_DMAMUX_CHANNEL_13
2336 * @arg @ref LL_DMAMUX_CHANNEL_14
2337 * @arg @ref LL_DMAMUX_CHANNEL_15
2338 * @retval State of bit (1 or 0).
2339 */
2340__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2341{
2342 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2343
2344 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
2345}
2346
2347/**
2348 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2349 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
2350 * @param DMAMUXx DMAMUXx Instance
2351 * @param RequestGenChannel This parameter can be one of the following values:
2352 * @arg @ref LL_DMAMUX_REQ_GEN_0
2353 * @arg @ref LL_DMAMUX_REQ_GEN_1
2354 * @arg @ref LL_DMAMUX_REQ_GEN_2
2355 * @arg @ref LL_DMAMUX_REQ_GEN_3
2356 * @arg @ref LL_DMAMUX_REQ_GEN_4
2357 * @arg @ref LL_DMAMUX_REQ_GEN_5
2358 * @arg @ref LL_DMAMUX_REQ_GEN_6
2359 * @arg @ref LL_DMAMUX_REQ_GEN_7
2360 * @retval None
2361 */
2362__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2363{
2364 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2365
2366 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2367}
2368
2369/**
2370 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2371 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
2372 * @param DMAMUXx DMAMUXx Instance
2373 * @param RequestGenChannel This parameter can be one of the following values:
2374 * @arg @ref LL_DMAMUX_REQ_GEN_0
2375 * @arg @ref LL_DMAMUX_REQ_GEN_1
2376 * @arg @ref LL_DMAMUX_REQ_GEN_2
2377 * @arg @ref LL_DMAMUX_REQ_GEN_3
2378 * @arg @ref LL_DMAMUX_REQ_GEN_4
2379 * @arg @ref LL_DMAMUX_REQ_GEN_5
2380 * @arg @ref LL_DMAMUX_REQ_GEN_6
2381 * @arg @ref LL_DMAMUX_REQ_GEN_7
2382 * @retval None
2383 */
2384__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2385{
2386 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2387
2388 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2389}
2390
2391/**
2392 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2393 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
2394 * @param DMAMUXx DMAMUXx Instance
2395 * @param RequestGenChannel This parameter can be one of the following values:
2396 * @arg @ref LL_DMAMUX_REQ_GEN_0
2397 * @arg @ref LL_DMAMUX_REQ_GEN_1
2398 * @arg @ref LL_DMAMUX_REQ_GEN_2
2399 * @arg @ref LL_DMAMUX_REQ_GEN_3
2400 * @arg @ref LL_DMAMUX_REQ_GEN_4
2401 * @arg @ref LL_DMAMUX_REQ_GEN_5
2402 * @arg @ref LL_DMAMUX_REQ_GEN_6
2403 * @arg @ref LL_DMAMUX_REQ_GEN_7
2404 * @retval State of bit (1 or 0).
2405 */
2406__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2407{
2408 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2409
2410 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
2411}
2412
2413/**
2414 * @}
2415 */
2416
2417/**
2418 * @}
2419 */
2420
2421/**
2422 * @}
2423 */
2424
2425#endif /* DMAMUX1 || DMAMUX2 */
2426
2427/**
2428 * @}
2429 */
2430
2431#ifdef __cplusplus
2432}
2433#endif
2434
2435#endif /* __STM32H7xx_LL_DMAMUX_H */
2436
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
DMAMUX_CFR_CSOF4
#define DMAMUX_CFR_CSOF4
Channel 4 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9263
DMAMUX_CxCR_SYNC_ID
#define DMAMUX_CxCR_SYNC_ID
Synchronization identification.
Definition stm32h723xx.h:9191
DMAMUX_RGCFR_COF4
#define DMAMUX_RGCFR_COF4
Request generator channel 4 Clear trigger overrun event flag.
Definition stm32h723xx.h:9368
DMAMUX_CSR_SOF0
#define DMAMUX_CSR_SOF0
Channel 0 Synchronization overrun event flag.
Definition stm32h723xx.h:9201
DMAMUX_CSR_SOF1
#define DMAMUX_CSR_SOF1
Channel 1 Synchronization overrun event flag.
Definition stm32h723xx.h:9204
DMAMUX_RGCFR_COF1
#define DMAMUX_RGCFR_COF1
Request generator channel 1 Clear trigger overrun event flag.
Definition stm32h723xx.h:9359
DMAMUX_CSR_SOF10
#define DMAMUX_CSR_SOF10
Channel 10 Synchronization overrun event flag.
Definition stm32h723xx.h:9231
DMAMUX_RGSR_OF6
#define DMAMUX_RGSR_OF6
Request generator channel 6 Trigger overrun event flag.
Definition stm32h723xx.h:9348
DMAMUX_CSR_SOF7
#define DMAMUX_CSR_SOF7
Channel 7 Synchronization overrun event flag.
Definition stm32h723xx.h:9222
DMAMUX_CxCR_SOIE
#define DMAMUX_CxCR_SOIE
Synchronization overrun interrupt enable.
Definition stm32h723xx.h:9169
DMAMUX_RGSR_OF4
#define DMAMUX_RGSR_OF4
Request generator channel 4 Trigger overrun event flag.
Definition stm32h723xx.h:9342
DMAMUX_RGSR_OF3
#define DMAMUX_RGSR_OF3
Request generator channel 3 Trigger overrun event flag.
Definition stm32h723xx.h:9339
DMAMUX_RGCFR_COF2
#define DMAMUX_RGCFR_COF2
Request generator channel 2 Clear trigger overrun event flag.
Definition stm32h723xx.h:9362
DMAMUX_CFR_CSOF12
#define DMAMUX_CFR_CSOF12
Channel 12 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9287
DMAMUX_CSR_SOF14
#define DMAMUX_CSR_SOF14
Channel 14 Synchronization overrun event flag.
Definition stm32h723xx.h:9243
DMAMUX_CxCR_DMAREQ_ID
#define DMAMUX_CxCR_DMAREQ_ID
DMA request identification.
Definition stm32h723xx.h:9158
DMAMUX_CFR_CSOF9
#define DMAMUX_CFR_CSOF9
Channel 9 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9278
DMAMUX_RGCFR_COF7
#define DMAMUX_RGCFR_COF7
Request generator channel 7 Clear trigger overrun event flag.
Definition stm32h723xx.h:9377
DMAMUX_RGSR_OF5
#define DMAMUX_RGSR_OF5
Request generator channel 5 Trigger overrun event flag.
Definition stm32h723xx.h:9345
DMAMUX_CFR_CSOF10
#define DMAMUX_CFR_CSOF10
Channel 10 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9281
DMAMUX_RGxCR_GE
#define DMAMUX_RGxCR_GE
DMA request generator enable.
Definition stm32h723xx.h:9312
DMAMUX_RGCFR_COF5
#define DMAMUX_RGCFR_COF5
Request generator channel 5 Clear trigger overrun event flag.
Definition stm32h723xx.h:9371
DMAMUX_CFR_CSOF13
#define DMAMUX_CFR_CSOF13
Channel 13 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9290
DMAMUX_CSR_SOF4
#define DMAMUX_CSR_SOF4
Channel 4 Synchronization overrun event flag.
Definition stm32h723xx.h:9213
DMAMUX_CFR_CSOF3
#define DMAMUX_CFR_CSOF3
Channel 3 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9260
DMAMUX_CFR_CSOF6
#define DMAMUX_CFR_CSOF6
Channel 6 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9269
DMAMUX_CSR_SOF9
#define DMAMUX_CSR_SOF9
Channel 9 Synchronization overrun event flag.
Definition stm32h723xx.h:9228
DMAMUX_CSR_SOF15
#define DMAMUX_CSR_SOF15
Channel 15 Synchronization overrun event flag.
Definition stm32h723xx.h:9246
DMAMUX_RGxCR_OIE
#define DMAMUX_RGxCR_OIE
Trigger overrun interrupt enable.
Definition stm32h723xx.h:9309
DMAMUX_CSR_SOF12
#define DMAMUX_CSR_SOF12
Channel 12 Synchronization overrun event flag.
Definition stm32h723xx.h:9237
DMAMUX_RGxCR_GNBREQ_Pos
#define DMAMUX_RGxCR_GNBREQ_Pos
Definition stm32h723xx.h:9318
DMAMUX_CSR_SOF3
#define DMAMUX_CSR_SOF3
Channel 3 Synchronization overrun event flag.
Definition stm32h723xx.h:9210
DMAMUX_CFR_CSOF11
#define DMAMUX_CFR_CSOF11
Channel 11 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9284
DMAMUX_CFR_CSOF2
#define DMAMUX_CFR_CSOF2
Channel 2 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9257
DMAMUX_CFR_CSOF7
#define DMAMUX_CFR_CSOF7
Channel 7 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9272
DMAMUX_CSR_SOF2
#define DMAMUX_CSR_SOF2
Channel 2 Synchronization overrun event flag.
Definition stm32h723xx.h:9207
DMAMUX_CxCR_NBREQ_Pos
#define DMAMUX_CxCR_NBREQ_Pos
Definition stm32h723xx.h:9181
DMAMUX_RGCFR_COF6
#define DMAMUX_RGCFR_COF6
Request generator channel 6 Clear trigger overrun event flag.
Definition stm32h723xx.h:9374
DMAMUX_CSR_SOF13
#define DMAMUX_CSR_SOF13
Channel 13 Synchronization overrun event flag.
Definition stm32h723xx.h:9240
DMAMUX_CFR_CSOF8
#define DMAMUX_CFR_CSOF8
Channel 8 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9275
DMAMUX_RGSR_OF1
#define DMAMUX_RGSR_OF1
Request generator channel 1 Trigger overrun event flag.
Definition stm32h723xx.h:9333
DMAMUX_RGSR_OF2
#define DMAMUX_RGSR_OF2
Request generator channel 2 Trigger overrun event flag.
Definition stm32h723xx.h:9336
DMAMUX_RGSR_OF0
#define DMAMUX_RGSR_OF0
Request generator channel 0 Trigger overrun event flag.
Definition stm32h723xx.h:9330
DMAMUX_CxCR_EGE
#define DMAMUX_CxCR_EGE
Event generation enable.
Definition stm32h723xx.h:9172
DMAMUX_CSR_SOF8
#define DMAMUX_CSR_SOF8
Channel 8 Synchronization overrun event flag.
Definition stm32h723xx.h:9225
DMAMUX_RGSR_OF7
#define DMAMUX_RGSR_OF7
Request generator channel 7 Trigger overrun event flag.
Definition stm32h723xx.h:9351
DMAMUX_RGxCR_GPOL
#define DMAMUX_RGxCR_GPOL
DMA request generator trigger polarity.
Definition stm32h723xx.h:9315
DMAMUX_CSR_SOF11
#define DMAMUX_CSR_SOF11
Channel 11 Synchronization overrun event flag.
Definition stm32h723xx.h:9234
DMAMUX_CFR_CSOF14
#define DMAMUX_CFR_CSOF14
Channel 14 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9293
DMAMUX_CFR_CSOF5
#define DMAMUX_CFR_CSOF5
Channel 5 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9266
DMAMUX_RGxCR_SIG_ID
#define DMAMUX_RGxCR_SIG_ID
Signal identification.
Definition stm32h723xx.h:9301
DMAMUX_RGxCR_GNBREQ
#define DMAMUX_RGxCR_GNBREQ
Number of DMA requests to be generated.
Definition stm32h723xx.h:9320
DMAMUX_RGCFR_COF0
#define DMAMUX_RGCFR_COF0
Request generator channel 0 Clear trigger overrun event flag.
Definition stm32h723xx.h:9356
DMAMUX_CxCR_SE
#define DMAMUX_CxCR_SE
Synchronization enable.
Definition stm32h723xx.h:9175
DMAMUX_CFR_CSOF0
#define DMAMUX_CFR_CSOF0
Channel 0 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9251
DMAMUX_CFR_CSOF1
#define DMAMUX_CFR_CSOF1
Channel 1 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9254
DMAMUX_CSR_SOF6
#define DMAMUX_CSR_SOF6
Channel 6 Synchronization overrun event flag.
Definition stm32h723xx.h:9219
DMAMUX_CxCR_NBREQ
#define DMAMUX_CxCR_NBREQ
Number of DMA requests minus 1 to forward.
Definition stm32h723xx.h:9183
DMAMUX_CFR_CSOF15
#define DMAMUX_CFR_CSOF15
Channel 15 Clear synchronization overrun event flag.
Definition stm32h723xx.h:9296
DMAMUX_RGCFR_COF3
#define DMAMUX_RGCFR_COF3
Request generator channel 3 Clear trigger overrun event flag.
Definition stm32h723xx.h:9365
DMAMUX_CSR_SOF5
#define DMAMUX_CSR_SOF5
Channel 5 Synchronization overrun event flag.
Definition stm32h723xx.h:9216
DMAMUX_CxCR_SPOL
#define DMAMUX_CxCR_SPOL
Synchronization polarity.
Definition stm32h723xx.h:9178
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
DMAMUX_ChannelStatus_TypeDef
Definition stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition stm32h723xx.h:645