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stm32h7xx_ll_i2c.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_I2C_H
21#define STM32H7xx_LL_I2C_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5)
35
36/** @defgroup I2C_LL I2C
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
44/** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47/**
48 * @}
49 */
50
51/* Private macros ------------------------------------------------------------*/
52#if defined(USE_FULL_LL_DRIVER)
53/** @defgroup I2C_LL_Private_Macros I2C Private Macros
54 * @{
55 */
56/**
57 * @}
58 */
59#endif /*USE_FULL_LL_DRIVER*/
60
61/* Exported types ------------------------------------------------------------*/
62#if defined(USE_FULL_LL_DRIVER)
63/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
64 * @{
65 */
66typedef struct
67{
68 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
69 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
70
71 This feature can be modified afterwards using unitary function
72 @ref LL_I2C_SetMode(). */
73
74 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
75 This parameter must be set by referring to the STM32CubeMX Tool and
76 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_I2C_SetTiming(). */
80
81 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
82 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
83
84 This feature can be modified afterwards using unitary functions
85 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
86
87 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
88 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_I2C_SetDigitalFilter(). */
92
93 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
94 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
95
96 This feature can be modified afterwards using unitary function
97 @ref LL_I2C_SetOwnAddress1(). */
98
99 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
100 match code or next received byte.
101 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
102
103 This feature can be modified afterwards using unitary function
104 @ref LL_I2C_AcknowledgeNextData(). */
105
106 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
107 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
108
109 This feature can be modified afterwards using unitary function
110 @ref LL_I2C_SetOwnAddress1(). */
111} LL_I2C_InitTypeDef;
112/**
113 * @}
114 */
115#endif /*USE_FULL_LL_DRIVER*/
116
117/* Exported constants --------------------------------------------------------*/
118/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
119 * @{
120 */
121
122/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
123 * @brief Flags defines which can be used with LL_I2C_WriteReg function
124 * @{
125 */
126#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
127#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
128#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
129#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
130#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
131#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
132#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
133#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
134#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
135/**
136 * @}
137 */
138
139/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
140 * @brief Flags defines which can be used with LL_I2C_ReadReg function
141 * @{
142 */
143#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
144#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
145#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
146#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
147#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
148#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
149#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
150#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
151#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
152#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
153#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
154#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
155#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
156#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
157#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
158/**
159 * @}
160 */
161
162/** @defgroup I2C_LL_EC_IT IT Defines
163 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
164 * @{
165 */
166#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
167#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
168#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
169#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
170#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
171#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
172#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
173/**
174 * @}
175 */
176
177/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
178 * @{
179 */
180#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
181#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
182#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
183 (Default address not acknowledge) */
184#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
185/**
186 * @}
187 */
188
189/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
190 * @{
191 */
192#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
193#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
194/**
195 * @}
196 */
197
198/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
199 * @{
200 */
201#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
202#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
203/**
204 * @}
205 */
206
207/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
208 * @{
209 */
210#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
211#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
212/**
213 * @}
214 */
215
216/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
217 * @{
218 */
219#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
220#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
221#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
222#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
223#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
224#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
225#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
226#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
227 All Address2 are acknowledged. */
228/**
229 * @}
230 */
231
232/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
233 * @{
234 */
235#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
236#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
237/**
238 * @}
239 */
240
241/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
242 * @{
243 */
244#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
245#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
246/**
247 * @}
248 */
249
250/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
251 * @{
252 */
253#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
254#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
255/**
256 * @}
257 */
258
259/** @defgroup I2C_LL_EC_MODE Transfer End Mode
260 * @{
261 */
262#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
263#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
264 with no HW PEC comparison. */
265#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
266 with no HW PEC comparison. */
267#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
268 with HW PEC comparison. */
269#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
270 with HW PEC comparison. */
271#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
272 with HW PEC comparison. */
273#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
274/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
275#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
276/*!< Enable SMBUS Software end mode with HW PEC comparison. */
277/**
278 * @}
279 */
280
281/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
282 * @{
283 */
284#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
285/*!< Don't Generate Stop and Start condition. */
286#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
287/*!< Generate Stop condition (Size should be set to 0). */
288#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
289/*!< Generate Start for read request. */
290#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
291/*!< Generate Start for write request. */
292#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
293/*!< Generate Restart for read request, slave 7Bit address. */
294#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
295/*!< Generate Restart for write request, slave 7Bit address. */
296#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
297 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
298/*!< Generate Restart for read request, slave 10Bit address. */
299#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
300/*!< Generate Restart for write request, slave 10Bit address.*/
301/**
302 * @}
303 */
304
305/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
306 * @{
307 */
308#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
309 slave enters receiver mode. */
310#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
311 slave enters transmitter mode.*/
312/**
313 * @}
314 */
315
316/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
317 * @{
318 */
319#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
320 transmission */
321#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
322 reception */
323/**
324 * @}
325 */
326
327/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
328 * @{
329 */
330#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
331 SCL low level timeout. */
332#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
333 both SCL and SDA high level timeout.*/
334/**
335 * @}
336 */
337
338/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
339 * @{
340 */
341#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
342#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
343 enable bit */
344#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
345 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
346(extended clock) enable bits */
347/**
348 * @}
349 */
350
351/**
352 * @}
353 */
354
355/* Exported macro ------------------------------------------------------------*/
356/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
357 * @{
358 */
359
360/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
361 * @{
362 */
363
364/**
365 * @brief Write a value in I2C register
366 * @param __INSTANCE__ I2C Instance
367 * @param __REG__ Register to be written
368 * @param __VALUE__ Value to be written in the register
369 * @retval None
370 */
371#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
372
373/**
374 * @brief Read a value in I2C register
375 * @param __INSTANCE__ I2C Instance
376 * @param __REG__ Register to be read
377 * @retval Register value
378 */
379#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
380/**
381 * @}
382 */
383
384/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
385 * @{
386 */
387/**
388 * @brief Configure the SDA setup, hold time and the SCL high, low period.
389 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
390 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
391 (tscldel = (SCLDEL+1)xtpresc)
392 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
393 (tsdadel = SDADELxtpresc)
394 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
395 (tsclh = (SCLH+1)xtpresc)
396 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
397 (tscll = (SCLL+1)xtpresc)
398 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
399 */
400#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
401 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
402 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
403 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
404 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
405 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
406/**
407 * @}
408 */
409
410/**
411 * @}
412 */
413
414/* Exported functions --------------------------------------------------------*/
415/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
416 * @{
417 */
418
419/** @defgroup I2C_LL_EF_Configuration Configuration
420 * @{
421 */
422
423/**
424 * @brief Enable I2C peripheral (PE = 1).
425 * @rmtoll CR1 PE LL_I2C_Enable
426 * @param I2Cx I2C Instance.
427 * @retval None
428 */
429__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
430{
431 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
432}
433
434/**
435 * @brief Disable I2C peripheral (PE = 0).
436 * @note When PE = 0, the I2C SCL and SDA lines are released.
437 * Internal state machines and status bits are put back to their reset value.
438 * When cleared, PE must be kept low for at least 3 APB clock cycles.
439 * @rmtoll CR1 PE LL_I2C_Disable
440 * @param I2Cx I2C Instance.
441 * @retval None
442 */
443__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
444{
445 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
446}
447
448/**
449 * @brief Check if the I2C peripheral is enabled or disabled.
450 * @rmtoll CR1 PE LL_I2C_IsEnabled
451 * @param I2Cx I2C Instance.
452 * @retval State of bit (1 or 0).
453 */
454__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
455{
456 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
457}
458
459/**
460 * @brief Configure Noise Filters (Analog and Digital).
461 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
462 * The filters can only be programmed when the I2C is disabled (PE = 0).
463 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
464 * CR1 DNF LL_I2C_ConfigFilters
465 * @param I2Cx I2C Instance.
466 * @param AnalogFilter This parameter can be one of the following values:
467 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
468 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
469 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
470 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
471 * This parameter is used to configure the digital noise filter on SDA and SCL input.
472 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
473 * @retval None
474 */
475__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
476{
477 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
478}
479
480/**
481 * @brief Configure Digital Noise Filter.
482 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
483 * This filter can only be programmed when the I2C is disabled (PE = 0).
484 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
485 * @param I2Cx I2C Instance.
486 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
487 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
488 * This parameter is used to configure the digital noise filter on SDA and SCL input.
489 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
490 * @retval None
491 */
492__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
493{
494 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
495}
496
497/**
498 * @brief Get the current Digital Noise Filter configuration.
499 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
500 * @param I2Cx I2C Instance.
501 * @retval Value between Min_Data=0x0 and Max_Data=0xF
502 */
503__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
504{
505 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
506}
507
508/**
509 * @brief Enable Analog Noise Filter.
510 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
511 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
512 * @param I2Cx I2C Instance.
513 * @retval None
514 */
515__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
516{
517 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
518}
519
520/**
521 * @brief Disable Analog Noise Filter.
522 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
523 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
524 * @param I2Cx I2C Instance.
525 * @retval None
526 */
527__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
528{
529 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
530}
531
532/**
533 * @brief Check if Analog Noise Filter is enabled or disabled.
534 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
535 * @param I2Cx I2C Instance.
536 * @retval State of bit (1 or 0).
537 */
538__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
539{
540 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
541}
542
543/**
544 * @brief Enable DMA transmission requests.
545 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
546 * @param I2Cx I2C Instance.
547 * @retval None
548 */
549__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
550{
551 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
552}
553
554/**
555 * @brief Disable DMA transmission requests.
556 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
557 * @param I2Cx I2C Instance.
558 * @retval None
559 */
560__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
561{
562 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
563}
564
565/**
566 * @brief Check if DMA transmission requests are enabled or disabled.
567 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
568 * @param I2Cx I2C Instance.
569 * @retval State of bit (1 or 0).
570 */
571__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
572{
573 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
574}
575
576/**
577 * @brief Enable DMA reception requests.
578 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
579 * @param I2Cx I2C Instance.
580 * @retval None
581 */
582__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
583{
584 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
585}
586
587/**
588 * @brief Disable DMA reception requests.
589 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
590 * @param I2Cx I2C Instance.
591 * @retval None
592 */
593__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
594{
595 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
596}
597
598/**
599 * @brief Check if DMA reception requests are enabled or disabled.
600 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
601 * @param I2Cx I2C Instance.
602 * @retval State of bit (1 or 0).
603 */
604__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
605{
606 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
607}
608
609/**
610 * @brief Get the data register address used for DMA transfer
611 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
612 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
613 * @param I2Cx I2C Instance
614 * @param Direction This parameter can be one of the following values:
615 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
616 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
617 * @retval Address of data register
618 */
619__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
620{
621 uint32_t data_reg_addr;
622
623 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
624 {
625 /* return address of TXDR register */
626 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
627 }
628 else
629 {
630 /* return address of RXDR register */
631 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
632 }
633
634 return data_reg_addr;
635}
636
637/**
638 * @brief Enable Clock stretching.
639 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
640 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
641 * @param I2Cx I2C Instance.
642 * @retval None
643 */
644__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
645{
646 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
647}
648
649/**
650 * @brief Disable Clock stretching.
651 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
652 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
653 * @param I2Cx I2C Instance.
654 * @retval None
655 */
656__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
657{
658 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
659}
660
661/**
662 * @brief Check if Clock stretching is enabled or disabled.
663 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
664 * @param I2Cx I2C Instance.
665 * @retval State of bit (1 or 0).
666 */
667__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
668{
669 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
670}
671
672/**
673 * @brief Enable hardware byte control in slave mode.
674 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
675 * @param I2Cx I2C Instance.
676 * @retval None
677 */
678__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
679{
680 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
681}
682
683/**
684 * @brief Disable hardware byte control in slave mode.
685 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
686 * @param I2Cx I2C Instance.
687 * @retval None
688 */
689__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
690{
691 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
692}
693
694/**
695 * @brief Check if hardware byte control in slave mode is enabled or disabled.
696 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
697 * @param I2Cx I2C Instance.
698 * @retval State of bit (1 or 0).
699 */
700__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
701{
702 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
703}
704
705/**
706 * @brief Enable Wakeup from STOP.
707 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
708 * WakeUpFromStop feature is supported by the I2Cx Instance.
709 * @note This bit can only be programmed when Digital Filter is disabled.
710 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
711 * @param I2Cx I2C Instance.
712 * @retval None
713 */
714__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
715{
716 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
717}
718
719/**
720 * @brief Disable Wakeup from STOP.
721 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
722 * WakeUpFromStop feature is supported by the I2Cx Instance.
723 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
724 * @param I2Cx I2C Instance.
725 * @retval None
726 */
727__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
728{
729 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
730}
731
732/**
733 * @brief Check if Wakeup from STOP is enabled or disabled.
734 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
735 * WakeUpFromStop feature is supported by the I2Cx Instance.
736 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
737 * @param I2Cx I2C Instance.
738 * @retval State of bit (1 or 0).
739 */
740__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
741{
742 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
743}
744
745/**
746 * @brief Enable General Call.
747 * @note When enabled the Address 0x00 is ACKed.
748 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
749 * @param I2Cx I2C Instance.
750 * @retval None
751 */
752__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
753{
754 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
755}
756
757/**
758 * @brief Disable General Call.
759 * @note When disabled the Address 0x00 is NACKed.
760 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
761 * @param I2Cx I2C Instance.
762 * @retval None
763 */
764__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
765{
766 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
767}
768
769/**
770 * @brief Check if General Call is enabled or disabled.
771 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
772 * @param I2Cx I2C Instance.
773 * @retval State of bit (1 or 0).
774 */
775__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
776{
777 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
778}
779
780/**
781 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
782 * @note Changing this bit is not allowed, when the START bit is set.
783 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
784 * @param I2Cx I2C Instance.
785 * @param AddressingMode This parameter can be one of the following values:
786 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
787 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
788 * @retval None
789 */
790__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
791{
792 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
793}
794
795/**
796 * @brief Get the Master addressing mode.
797 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
798 * @param I2Cx I2C Instance.
799 * @retval Returned value can be one of the following values:
800 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
801 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
802 */
803__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
804{
805 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
806}
807
808/**
809 * @brief Set the Own Address1.
810 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
811 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
812 * @param I2Cx I2C Instance.
813 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
814 * @param OwnAddrSize This parameter can be one of the following values:
815 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
816 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
817 * @retval None
818 */
819__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
820{
821 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
822}
823
824/**
825 * @brief Enable acknowledge on Own Address1 match address.
826 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
827 * @param I2Cx I2C Instance.
828 * @retval None
829 */
830__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
831{
832 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
833}
834
835/**
836 * @brief Disable acknowledge on Own Address1 match address.
837 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
838 * @param I2Cx I2C Instance.
839 * @retval None
840 */
841__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
842{
843 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
844}
845
846/**
847 * @brief Check if Own Address1 acknowledge is enabled or disabled.
848 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
849 * @param I2Cx I2C Instance.
850 * @retval State of bit (1 or 0).
851 */
852__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
853{
854 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
855}
856
857/**
858 * @brief Set the 7bits Own Address2.
859 * @note This action has no effect if own address2 is enabled.
860 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
861 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
862 * @param I2Cx I2C Instance.
863 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
864 * @param OwnAddrMask This parameter can be one of the following values:
865 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
866 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
867 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
868 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
869 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
870 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
871 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
872 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
873 * @retval None
874 */
875__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
876{
877 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
878}
879
880/**
881 * @brief Enable acknowledge on Own Address2 match address.
882 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
883 * @param I2Cx I2C Instance.
884 * @retval None
885 */
886__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
887{
888 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
889}
890
891/**
892 * @brief Disable acknowledge on Own Address2 match address.
893 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
894 * @param I2Cx I2C Instance.
895 * @retval None
896 */
897__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
898{
899 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
900}
901
902/**
903 * @brief Check if Own Address1 acknowledge is enabled or disabled.
904 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
905 * @param I2Cx I2C Instance.
906 * @retval State of bit (1 or 0).
907 */
908__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
909{
910 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
911}
912
913/**
914 * @brief Configure the SDA setup, hold time and the SCL high, low period.
915 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
916 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
917 * @param I2Cx I2C Instance.
918 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
919 * @note This parameter is computed with the STM32CubeMX Tool.
920 * @retval None
921 */
922__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
923{
924 WRITE_REG(I2Cx->TIMINGR, Timing);
925}
926
927/**
928 * @brief Get the Timing Prescaler setting.
929 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
930 * @param I2Cx I2C Instance.
931 * @retval Value between Min_Data=0x0 and Max_Data=0xF
932 */
933__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
934{
935 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
936}
937
938/**
939 * @brief Get the SCL low period setting.
940 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
941 * @param I2Cx I2C Instance.
942 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
943 */
944__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
945{
946 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
947}
948
949/**
950 * @brief Get the SCL high period setting.
951 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
952 * @param I2Cx I2C Instance.
953 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
954 */
955__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
956{
957 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
958}
959
960/**
961 * @brief Get the SDA hold time.
962 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
963 * @param I2Cx I2C Instance.
964 * @retval Value between Min_Data=0x0 and Max_Data=0xF
965 */
966__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
967{
968 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
969}
970
971/**
972 * @brief Get the SDA setup time.
973 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
974 * @param I2Cx I2C Instance.
975 * @retval Value between Min_Data=0x0 and Max_Data=0xF
976 */
977__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
978{
979 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
980}
981
982/**
983 * @brief Configure peripheral mode.
984 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
985 * SMBus feature is supported by the I2Cx Instance.
986 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
987 * CR1 SMBDEN LL_I2C_SetMode
988 * @param I2Cx I2C Instance.
989 * @param PeripheralMode This parameter can be one of the following values:
990 * @arg @ref LL_I2C_MODE_I2C
991 * @arg @ref LL_I2C_MODE_SMBUS_HOST
992 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
993 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
994 * @retval None
995 */
996__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
997{
998 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
999}
1000
1001/**
1002 * @brief Get peripheral mode.
1003 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1004 * SMBus feature is supported by the I2Cx Instance.
1005 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
1006 * CR1 SMBDEN LL_I2C_GetMode
1007 * @param I2Cx I2C Instance.
1008 * @retval Returned value can be one of the following values:
1009 * @arg @ref LL_I2C_MODE_I2C
1010 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1011 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1012 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1013 */
1014__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
1015{
1016 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1017}
1018
1019/**
1020 * @brief Enable SMBus alert (Host or Device mode)
1021 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1022 * SMBus feature is supported by the I2Cx Instance.
1023 * @note SMBus Device mode:
1024 * - SMBus Alert pin is drived low and
1025 * Alert Response Address Header acknowledge is enabled.
1026 * SMBus Host mode:
1027 * - SMBus Alert pin management is supported.
1028 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1029 * @param I2Cx I2C Instance.
1030 * @retval None
1031 */
1032__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1033{
1034 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1035}
1036
1037/**
1038 * @brief Disable SMBus alert (Host or Device mode)
1039 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1040 * SMBus feature is supported by the I2Cx Instance.
1041 * @note SMBus Device mode:
1042 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1043 * Alert Response Address Header acknowledge is disabled.
1044 * SMBus Host mode:
1045 * - SMBus Alert pin management is not supported.
1046 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1047 * @param I2Cx I2C Instance.
1048 * @retval None
1049 */
1050__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1051{
1052 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1053}
1054
1055/**
1056 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1057 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1058 * SMBus feature is supported by the I2Cx Instance.
1059 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1060 * @param I2Cx I2C Instance.
1061 * @retval State of bit (1 or 0).
1062 */
1063__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
1064{
1065 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1066}
1067
1068/**
1069 * @brief Enable SMBus Packet Error Calculation (PEC).
1070 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1071 * SMBus feature is supported by the I2Cx Instance.
1072 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1073 * @param I2Cx I2C Instance.
1074 * @retval None
1075 */
1076__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1077{
1078 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1079}
1080
1081/**
1082 * @brief Disable SMBus Packet Error Calculation (PEC).
1083 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1084 * SMBus feature is supported by the I2Cx Instance.
1085 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1086 * @param I2Cx I2C Instance.
1087 * @retval None
1088 */
1089__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1090{
1091 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1092}
1093
1094/**
1095 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1096 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1097 * SMBus feature is supported by the I2Cx Instance.
1098 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1099 * @param I2Cx I2C Instance.
1100 * @retval State of bit (1 or 0).
1101 */
1102__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
1103{
1104 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1105}
1106
1107/**
1108 * @brief Configure the SMBus Clock Timeout.
1109 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1110 * SMBus feature is supported by the I2Cx Instance.
1111 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1112 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1113 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1114 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1115 * @param I2Cx I2C Instance.
1116 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1117 * @param TimeoutAMode This parameter can be one of the following values:
1118 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1119 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1120 * @param TimeoutB
1121 * @retval None
1122 */
1123__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1124 uint32_t TimeoutB)
1125{
1126 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1127 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1128}
1129
1130/**
1131 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1132 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1133 * SMBus feature is supported by the I2Cx Instance.
1134 * @note These bits can only be programmed when TimeoutA is disabled.
1135 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1136 * @param I2Cx I2C Instance.
1137 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1138 * @retval None
1139 */
1140__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1141{
1142 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1143}
1144
1145/**
1146 * @brief Get the SMBus Clock TimeoutA setting.
1147 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1148 * SMBus feature is supported by the I2Cx Instance.
1149 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1150 * @param I2Cx I2C Instance.
1151 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1152 */
1153__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
1154{
1155 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1156}
1157
1158/**
1159 * @brief Set the SMBus Clock TimeoutA mode.
1160 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1161 * SMBus feature is supported by the I2Cx Instance.
1162 * @note This bit can only be programmed when TimeoutA is disabled.
1163 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1164 * @param I2Cx I2C Instance.
1165 * @param TimeoutAMode This parameter can be one of the following values:
1166 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1167 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1168 * @retval None
1169 */
1170__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1171{
1172 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1173}
1174
1175/**
1176 * @brief Get the SMBus Clock TimeoutA mode.
1177 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1178 * SMBus feature is supported by the I2Cx Instance.
1179 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1180 * @param I2Cx I2C Instance.
1181 * @retval Returned value can be one of the following values:
1182 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1183 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1184 */
1185__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
1186{
1187 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1188}
1189
1190/**
1191 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1192 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1193 * SMBus feature is supported by the I2Cx Instance.
1194 * @note These bits can only be programmed when TimeoutB is disabled.
1195 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1196 * @param I2Cx I2C Instance.
1197 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1198 * @retval None
1199 */
1200__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1201{
1202 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1203}
1204
1205/**
1206 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1207 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1208 * SMBus feature is supported by the I2Cx Instance.
1209 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1210 * @param I2Cx I2C Instance.
1211 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1212 */
1213__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
1214{
1215 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1216}
1217
1218/**
1219 * @brief Enable the SMBus Clock Timeout.
1220 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1221 * SMBus feature is supported by the I2Cx Instance.
1222 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1223 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1224 * @param I2Cx I2C Instance.
1225 * @param ClockTimeout This parameter can be one of the following values:
1226 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1227 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1228 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1229 * @retval None
1230 */
1231__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1232{
1233 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1234}
1235
1236/**
1237 * @brief Disable the SMBus Clock Timeout.
1238 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1239 * SMBus feature is supported by the I2Cx Instance.
1240 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1241 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1242 * @param I2Cx I2C Instance.
1243 * @param ClockTimeout This parameter can be one of the following values:
1244 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1245 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1246 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1247 * @retval None
1248 */
1249__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1250{
1251 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1252}
1253
1254/**
1255 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1256 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1257 * SMBus feature is supported by the I2Cx Instance.
1258 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1259 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1260 * @param I2Cx I2C Instance.
1261 * @param ClockTimeout This parameter can be one of the following values:
1262 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1263 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1264 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1265 * @retval State of bit (1 or 0).
1266 */
1267__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1268{
1269 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1270 (ClockTimeout)) ? 1UL : 0UL);
1271}
1272
1273/**
1274 * @}
1275 */
1276
1277/** @defgroup I2C_LL_EF_IT_Management IT_Management
1278 * @{
1279 */
1280
1281/**
1282 * @brief Enable TXIS interrupt.
1283 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1284 * @param I2Cx I2C Instance.
1285 * @retval None
1286 */
1287__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1288{
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1290}
1291
1292/**
1293 * @brief Disable TXIS interrupt.
1294 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1295 * @param I2Cx I2C Instance.
1296 * @retval None
1297 */
1298__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1299{
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1301}
1302
1303/**
1304 * @brief Check if the TXIS Interrupt is enabled or disabled.
1305 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1306 * @param I2Cx I2C Instance.
1307 * @retval State of bit (1 or 0).
1308 */
1309__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
1310{
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1312}
1313
1314/**
1315 * @brief Enable RXNE interrupt.
1316 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1317 * @param I2Cx I2C Instance.
1318 * @retval None
1319 */
1320__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1321{
1322 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1323}
1324
1325/**
1326 * @brief Disable RXNE interrupt.
1327 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1328 * @param I2Cx I2C Instance.
1329 * @retval None
1330 */
1331__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1332{
1333 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1334}
1335
1336/**
1337 * @brief Check if the RXNE Interrupt is enabled or disabled.
1338 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1339 * @param I2Cx I2C Instance.
1340 * @retval State of bit (1 or 0).
1341 */
1342__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
1343{
1344 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1345}
1346
1347/**
1348 * @brief Enable Address match interrupt (slave mode only).
1349 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1350 * @param I2Cx I2C Instance.
1351 * @retval None
1352 */
1353__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1354{
1355 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1356}
1357
1358/**
1359 * @brief Disable Address match interrupt (slave mode only).
1360 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1361 * @param I2Cx I2C Instance.
1362 * @retval None
1363 */
1364__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1365{
1366 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1367}
1368
1369/**
1370 * @brief Check if Address match interrupt is enabled or disabled.
1371 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1372 * @param I2Cx I2C Instance.
1373 * @retval State of bit (1 or 0).
1374 */
1375__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
1376{
1377 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1378}
1379
1380/**
1381 * @brief Enable Not acknowledge received interrupt.
1382 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1383 * @param I2Cx I2C Instance.
1384 * @retval None
1385 */
1386__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1387{
1388 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1389}
1390
1391/**
1392 * @brief Disable Not acknowledge received interrupt.
1393 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1394 * @param I2Cx I2C Instance.
1395 * @retval None
1396 */
1397__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1398{
1399 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1400}
1401
1402/**
1403 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1404 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1405 * @param I2Cx I2C Instance.
1406 * @retval State of bit (1 or 0).
1407 */
1408__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
1409{
1410 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1411}
1412
1413/**
1414 * @brief Enable STOP detection interrupt.
1415 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1416 * @param I2Cx I2C Instance.
1417 * @retval None
1418 */
1419__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1420{
1421 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1422}
1423
1424/**
1425 * @brief Disable STOP detection interrupt.
1426 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1427 * @param I2Cx I2C Instance.
1428 * @retval None
1429 */
1430__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1431{
1432 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1433}
1434
1435/**
1436 * @brief Check if STOP detection interrupt is enabled or disabled.
1437 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1438 * @param I2Cx I2C Instance.
1439 * @retval State of bit (1 or 0).
1440 */
1441__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
1442{
1443 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1444}
1445
1446/**
1447 * @brief Enable Transfer Complete interrupt.
1448 * @note Any of these events will generate interrupt :
1449 * Transfer Complete (TC)
1450 * Transfer Complete Reload (TCR)
1451 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1452 * @param I2Cx I2C Instance.
1453 * @retval None
1454 */
1455__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1456{
1457 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1458}
1459
1460/**
1461 * @brief Disable Transfer Complete interrupt.
1462 * @note Any of these events will generate interrupt :
1463 * Transfer Complete (TC)
1464 * Transfer Complete Reload (TCR)
1465 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1466 * @param I2Cx I2C Instance.
1467 * @retval None
1468 */
1469__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1470{
1471 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1472}
1473
1474/**
1475 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1476 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1477 * @param I2Cx I2C Instance.
1478 * @retval State of bit (1 or 0).
1479 */
1480__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
1481{
1482 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1483}
1484
1485/**
1486 * @brief Enable Error interrupts.
1487 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1488 * SMBus feature is supported by the I2Cx Instance.
1489 * @note Any of these errors will generate interrupt :
1490 * Arbitration Loss (ARLO)
1491 * Bus Error detection (BERR)
1492 * Overrun/Underrun (OVR)
1493 * SMBus Timeout detection (TIMEOUT)
1494 * SMBus PEC error detection (PECERR)
1495 * SMBus Alert pin event detection (ALERT)
1496 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1497 * @param I2Cx I2C Instance.
1498 * @retval None
1499 */
1500__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1501{
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1503}
1504
1505/**
1506 * @brief Disable Error interrupts.
1507 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1508 * SMBus feature is supported by the I2Cx Instance.
1509 * @note Any of these errors will generate interrupt :
1510 * Arbitration Loss (ARLO)
1511 * Bus Error detection (BERR)
1512 * Overrun/Underrun (OVR)
1513 * SMBus Timeout detection (TIMEOUT)
1514 * SMBus PEC error detection (PECERR)
1515 * SMBus Alert pin event detection (ALERT)
1516 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1517 * @param I2Cx I2C Instance.
1518 * @retval None
1519 */
1520__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1521{
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1523}
1524
1525/**
1526 * @brief Check if Error interrupts are enabled or disabled.
1527 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1528 * @param I2Cx I2C Instance.
1529 * @retval State of bit (1 or 0).
1530 */
1531__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
1532{
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1534}
1535
1536/**
1537 * @}
1538 */
1539
1540/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1541 * @{
1542 */
1543
1544/**
1545 * @brief Indicate the status of Transmit data register empty flag.
1546 * @note RESET: When next data is written in Transmit data register.
1547 * SET: When Transmit data register is empty.
1548 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1549 * @param I2Cx I2C Instance.
1550 * @retval State of bit (1 or 0).
1551 */
1552__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
1553{
1554 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1555}
1556
1557/**
1558 * @brief Indicate the status of Transmit interrupt flag.
1559 * @note RESET: When next data is written in Transmit data register.
1560 * SET: When Transmit data register is empty.
1561 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1562 * @param I2Cx I2C Instance.
1563 * @retval State of bit (1 or 0).
1564 */
1565__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
1566{
1567 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1568}
1569
1570/**
1571 * @brief Indicate the status of Receive data register not empty flag.
1572 * @note RESET: When Receive data register is read.
1573 * SET: When the received data is copied in Receive data register.
1574 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1575 * @param I2Cx I2C Instance.
1576 * @retval State of bit (1 or 0).
1577 */
1578__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
1579{
1580 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1581}
1582
1583/**
1584 * @brief Indicate the status of Address matched flag (slave mode).
1585 * @note RESET: Clear default value.
1586 * SET: When the received slave address matched with one of the enabled slave address.
1587 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1588 * @param I2Cx I2C Instance.
1589 * @retval State of bit (1 or 0).
1590 */
1591__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
1592{
1593 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1594}
1595
1596/**
1597 * @brief Indicate the status of Not Acknowledge received flag.
1598 * @note RESET: Clear default value.
1599 * SET: When a NACK is received after a byte transmission.
1600 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1601 * @param I2Cx I2C Instance.
1602 * @retval State of bit (1 or 0).
1603 */
1604__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
1605{
1606 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1607}
1608
1609/**
1610 * @brief Indicate the status of Stop detection flag.
1611 * @note RESET: Clear default value.
1612 * SET: When a Stop condition is detected.
1613 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1614 * @param I2Cx I2C Instance.
1615 * @retval State of bit (1 or 0).
1616 */
1617__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
1618{
1619 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1620}
1621
1622/**
1623 * @brief Indicate the status of Transfer complete flag (master mode).
1624 * @note RESET: Clear default value.
1625 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1626 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1627 * @param I2Cx I2C Instance.
1628 * @retval State of bit (1 or 0).
1629 */
1630__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
1631{
1632 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1633}
1634
1635/**
1636 * @brief Indicate the status of Transfer complete flag (master mode).
1637 * @note RESET: Clear default value.
1638 * SET: When RELOAD=1 and NBYTES date have been transferred.
1639 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1640 * @param I2Cx I2C Instance.
1641 * @retval State of bit (1 or 0).
1642 */
1643__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
1644{
1645 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1646}
1647
1648/**
1649 * @brief Indicate the status of Bus error flag.
1650 * @note RESET: Clear default value.
1651 * SET: When a misplaced Start or Stop condition is detected.
1652 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1653 * @param I2Cx I2C Instance.
1654 * @retval State of bit (1 or 0).
1655 */
1656__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
1657{
1658 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1659}
1660
1661/**
1662 * @brief Indicate the status of Arbitration lost flag.
1663 * @note RESET: Clear default value.
1664 * SET: When arbitration lost.
1665 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1666 * @param I2Cx I2C Instance.
1667 * @retval State of bit (1 or 0).
1668 */
1669__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
1670{
1671 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1672}
1673
1674/**
1675 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1676 * @note RESET: Clear default value.
1677 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1678 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1679 * @param I2Cx I2C Instance.
1680 * @retval State of bit (1 or 0).
1681 */
1682__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
1683{
1684 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1685}
1686
1687/**
1688 * @brief Indicate the status of SMBus PEC error flag in reception.
1689 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1690 * SMBus feature is supported by the I2Cx Instance.
1691 * @note RESET: Clear default value.
1692 * SET: When the received PEC does not match with the PEC register content.
1693 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1694 * @param I2Cx I2C Instance.
1695 * @retval State of bit (1 or 0).
1696 */
1697__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
1698{
1699 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1700}
1701
1702/**
1703 * @brief Indicate the status of SMBus Timeout detection flag.
1704 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1705 * SMBus feature is supported by the I2Cx Instance.
1706 * @note RESET: Clear default value.
1707 * SET: When a timeout or extended clock timeout occurs.
1708 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1709 * @param I2Cx I2C Instance.
1710 * @retval State of bit (1 or 0).
1711 */
1712__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
1713{
1714 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1715}
1716
1717/**
1718 * @brief Indicate the status of SMBus alert flag.
1719 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1720 * SMBus feature is supported by the I2Cx Instance.
1721 * @note RESET: Clear default value.
1722 * SET: When SMBus host configuration, SMBus alert enabled and
1723 * a falling edge event occurs on SMBA pin.
1724 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1725 * @param I2Cx I2C Instance.
1726 * @retval State of bit (1 or 0).
1727 */
1728__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
1729{
1730 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1731}
1732
1733/**
1734 * @brief Indicate the status of Bus Busy flag.
1735 * @note RESET: Clear default value.
1736 * SET: When a Start condition is detected.
1737 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1738 * @param I2Cx I2C Instance.
1739 * @retval State of bit (1 or 0).
1740 */
1741__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
1742{
1743 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1744}
1745
1746/**
1747 * @brief Clear Address Matched flag.
1748 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1749 * @param I2Cx I2C Instance.
1750 * @retval None
1751 */
1752__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1753{
1754 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1755}
1756
1757/**
1758 * @brief Clear Not Acknowledge flag.
1759 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1760 * @param I2Cx I2C Instance.
1761 * @retval None
1762 */
1763__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1764{
1765 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1766}
1767
1768/**
1769 * @brief Clear Stop detection flag.
1770 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1771 * @param I2Cx I2C Instance.
1772 * @retval None
1773 */
1774__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1775{
1776 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1777}
1778
1779/**
1780 * @brief Clear Transmit data register empty flag (TXE).
1781 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1782 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1783 * @param I2Cx I2C Instance.
1784 * @retval None
1785 */
1786__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1787{
1788 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1789}
1790
1791/**
1792 * @brief Clear Bus error flag.
1793 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1794 * @param I2Cx I2C Instance.
1795 * @retval None
1796 */
1797__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1798{
1799 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1800}
1801
1802/**
1803 * @brief Clear Arbitration lost flag.
1804 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1805 * @param I2Cx I2C Instance.
1806 * @retval None
1807 */
1808__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1809{
1810 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1811}
1812
1813/**
1814 * @brief Clear Overrun/Underrun flag.
1815 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1816 * @param I2Cx I2C Instance.
1817 * @retval None
1818 */
1819__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1820{
1821 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1822}
1823
1824/**
1825 * @brief Clear SMBus PEC error flag.
1826 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1827 * SMBus feature is supported by the I2Cx Instance.
1828 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1829 * @param I2Cx I2C Instance.
1830 * @retval None
1831 */
1832__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1833{
1834 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1835}
1836
1837/**
1838 * @brief Clear SMBus Timeout detection flag.
1839 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1840 * SMBus feature is supported by the I2Cx Instance.
1841 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1842 * @param I2Cx I2C Instance.
1843 * @retval None
1844 */
1845__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1846{
1847 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1848}
1849
1850/**
1851 * @brief Clear SMBus Alert flag.
1852 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1853 * SMBus feature is supported by the I2Cx Instance.
1854 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1855 * @param I2Cx I2C Instance.
1856 * @retval None
1857 */
1858__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1859{
1860 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1861}
1862
1863/**
1864 * @}
1865 */
1866
1867/** @defgroup I2C_LL_EF_Data_Management Data_Management
1868 * @{
1869 */
1870
1871/**
1872 * @brief Enable automatic STOP condition generation (master mode).
1873 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1874 * This bit has no effect in slave mode or when RELOAD bit is set.
1875 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1876 * @param I2Cx I2C Instance.
1877 * @retval None
1878 */
1879__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1880{
1881 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1882}
1883
1884/**
1885 * @brief Disable automatic STOP condition generation (master mode).
1886 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1887 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1888 * @param I2Cx I2C Instance.
1889 * @retval None
1890 */
1891__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1892{
1893 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1894}
1895
1896/**
1897 * @brief Check if automatic STOP condition is enabled or disabled.
1898 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1899 * @param I2Cx I2C Instance.
1900 * @retval State of bit (1 or 0).
1901 */
1902__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
1903{
1904 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1905}
1906
1907/**
1908 * @brief Enable reload mode (master mode).
1909 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1910 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1911 * @param I2Cx I2C Instance.
1912 * @retval None
1913 */
1914__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1915{
1916 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1917}
1918
1919/**
1920 * @brief Disable reload mode (master mode).
1921 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1922 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1923 * @param I2Cx I2C Instance.
1924 * @retval None
1925 */
1926__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1927{
1928 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1929}
1930
1931/**
1932 * @brief Check if reload mode is enabled or disabled.
1933 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1934 * @param I2Cx I2C Instance.
1935 * @retval State of bit (1 or 0).
1936 */
1937__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
1938{
1939 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1940}
1941
1942/**
1943 * @brief Configure the number of bytes for transfer.
1944 * @note Changing these bits when START bit is set is not allowed.
1945 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1946 * @param I2Cx I2C Instance.
1947 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1948 * @retval None
1949 */
1950__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1951{
1952 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1953}
1954
1955/**
1956 * @brief Get the number of bytes configured for transfer.
1957 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1958 * @param I2Cx I2C Instance.
1959 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1960 */
1961__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
1962{
1963 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1964}
1965
1966/**
1967 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
1968 or next received byte.
1969 * @note Usage in Slave mode only.
1970 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1971 * @param I2Cx I2C Instance.
1972 * @param TypeAcknowledge This parameter can be one of the following values:
1973 * @arg @ref LL_I2C_ACK
1974 * @arg @ref LL_I2C_NACK
1975 * @retval None
1976 */
1977__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1978{
1979 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1980}
1981
1982/**
1983 * @brief Generate a START or RESTART condition
1984 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1985 * This action has no effect when RELOAD is set.
1986 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1987 * @param I2Cx I2C Instance.
1988 * @retval None
1989 */
1990__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1991{
1992 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1993}
1994
1995/**
1996 * @brief Generate a STOP condition after the current byte transfer (master mode).
1997 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1998 * @param I2Cx I2C Instance.
1999 * @retval None
2000 */
2001__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2002{
2003 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2004}
2005
2006/**
2007 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
2008 * @note The master sends the complete 10bit slave address read sequence :
2009 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2010 in Read direction.
2011 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
2012 * @param I2Cx I2C Instance.
2013 * @retval None
2014 */
2015__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2016{
2017 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2018}
2019
2020/**
2021 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
2022 * @note The master only sends the first 7 bits of 10bit address in Read direction.
2023 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
2024 * @param I2Cx I2C Instance.
2025 * @retval None
2026 */
2027__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2028{
2029 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2030}
2031
2032/**
2033 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2034 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2035 * @param I2Cx I2C Instance.
2036 * @retval State of bit (1 or 0).
2037 */
2038__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
2039{
2040 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2041}
2042
2043/**
2044 * @brief Configure the transfer direction (master mode).
2045 * @note Changing these bits when START bit is set is not allowed.
2046 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2047 * @param I2Cx I2C Instance.
2048 * @param TransferRequest This parameter can be one of the following values:
2049 * @arg @ref LL_I2C_REQUEST_WRITE
2050 * @arg @ref LL_I2C_REQUEST_READ
2051 * @retval None
2052 */
2053__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2054{
2055 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2056}
2057
2058/**
2059 * @brief Get the transfer direction requested (master mode).
2060 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2061 * @param I2Cx I2C Instance.
2062 * @retval Returned value can be one of the following values:
2063 * @arg @ref LL_I2C_REQUEST_WRITE
2064 * @arg @ref LL_I2C_REQUEST_READ
2065 */
2066__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
2067{
2068 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2069}
2070
2071/**
2072 * @brief Configure the slave address for transfer (master mode).
2073 * @note Changing these bits when START bit is set is not allowed.
2074 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2075 * @param I2Cx I2C Instance.
2076 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2077 * @retval None
2078 */
2079__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2080{
2081 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2082}
2083
2084/**
2085 * @brief Get the slave address programmed for transfer.
2086 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2087 * @param I2Cx I2C Instance.
2088 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2089 */
2090__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
2091{
2092 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2093}
2094
2095/**
2096 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2097 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2098 * CR2 ADD10 LL_I2C_HandleTransfer\n
2099 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2100 * CR2 START LL_I2C_HandleTransfer\n
2101 * CR2 STOP LL_I2C_HandleTransfer\n
2102 * CR2 RELOAD LL_I2C_HandleTransfer\n
2103 * CR2 NBYTES LL_I2C_HandleTransfer\n
2104 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2105 * CR2 HEAD10R LL_I2C_HandleTransfer
2106 * @param I2Cx I2C Instance.
2107 * @param SlaveAddr Specifies the slave address to be programmed.
2108 * @param SlaveAddrSize This parameter can be one of the following values:
2109 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2110 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2111 * @param TransferSize Specifies the number of bytes to be programmed.
2112 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2113 * @param EndMode This parameter can be one of the following values:
2114 * @arg @ref LL_I2C_MODE_RELOAD
2115 * @arg @ref LL_I2C_MODE_AUTOEND
2116 * @arg @ref LL_I2C_MODE_SOFTEND
2117 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2118 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2119 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2120 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2121 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2122 * @param Request This parameter can be one of the following values:
2123 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2124 * @arg @ref LL_I2C_GENERATE_STOP
2125 * @arg @ref LL_I2C_GENERATE_START_READ
2126 * @arg @ref LL_I2C_GENERATE_START_WRITE
2127 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2128 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2129 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2130 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2131 * @retval None
2132 */
2133__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2134 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2135{
2136 /* Declaration of tmp to prevent undefined behavior of volatile usage */
2137 uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
2138 ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
2139 (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
2140 (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
2141
2142 /* update CR2 register */
2143 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2144 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2145 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2146 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2147 tmp);
2148}
2149
2150/**
2151 * @brief Indicate the value of transfer direction (slave mode).
2152 * @note RESET: Write transfer, Slave enters in receiver mode.
2153 * SET: Read transfer, Slave enters in transmitter mode.
2154 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2155 * @param I2Cx I2C Instance.
2156 * @retval Returned value can be one of the following values:
2157 * @arg @ref LL_I2C_DIRECTION_WRITE
2158 * @arg @ref LL_I2C_DIRECTION_READ
2159 */
2160__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
2161{
2162 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2163}
2164
2165/**
2166 * @brief Return the slave matched address.
2167 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2168 * @param I2Cx I2C Instance.
2169 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2170 */
2171__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
2172{
2173 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2174}
2175
2176/**
2177 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2178 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2179 * SMBus feature is supported by the I2Cx Instance.
2180 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2181 or an Address Matched is received.
2182 * This bit has no effect when RELOAD bit is set.
2183 * This bit has no effect in device mode when SBC bit is not set.
2184 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2185 * @param I2Cx I2C Instance.
2186 * @retval None
2187 */
2188__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2189{
2190 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2191}
2192
2193/**
2194 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2195 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2196 * SMBus feature is supported by the I2Cx Instance.
2197 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2198 * @param I2Cx I2C Instance.
2199 * @retval State of bit (1 or 0).
2200 */
2201__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
2202{
2203 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2204}
2205
2206/**
2207 * @brief Get the SMBus Packet Error byte calculated.
2208 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2209 * SMBus feature is supported by the I2Cx Instance.
2210 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2211 * @param I2Cx I2C Instance.
2212 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2213 */
2214__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
2215{
2216 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2217}
2218
2219/**
2220 * @brief Read Receive Data register.
2221 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2222 * @param I2Cx I2C Instance.
2223 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2224 */
2225__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
2226{
2227 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2228}
2229
2230/**
2231 * @brief Write in Transmit Data Register .
2232 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2233 * @param I2Cx I2C Instance.
2234 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2235 * @retval None
2236 */
2237__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2238{
2239 WRITE_REG(I2Cx->TXDR, Data);
2240}
2241
2242/**
2243 * @}
2244 */
2245
2246#if defined(USE_FULL_LL_DRIVER)
2247/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2248 * @{
2249 */
2250
2251ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
2252ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
2253void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2254
2255
2256/**
2257 * @}
2258 */
2259#endif /* USE_FULL_LL_DRIVER */
2260
2261/**
2262 * @}
2263 */
2264
2265/**
2266 * @}
2267 */
2268
2269#endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 */
2270
2271/**
2272 * @}
2273 */
2274
2275#ifdef __cplusplus
2276}
2277#endif
2278
2279#endif /* STM32H7xx_LL_I2C_H */
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
ErrorStatus
ErrorStatus
Definition stm32h7xx.h:194
I2C_ISR_RXNE
#define I2C_ISR_RXNE
Receive data register not empty.
Definition stm32h723xx.h:13233
I2C_ISR_ADDR
#define I2C_ISR_ADDR
Address matched (slave mode).
Definition stm32h723xx.h:13236
I2C_ISR_BERR
#define I2C_ISR_BERR
Bus error.
Definition stm32h723xx.h:13251
I2C_ISR_BUSY
#define I2C_ISR_BUSY
Bus busy.
Definition stm32h723xx.h:13269
I2C_TIMINGR_PRESC_Pos
#define I2C_TIMINGR_PRESC_Pos
Definition stm32h723xx.h:13203
I2C_TIMINGR_SCLDEL_Pos
#define I2C_TIMINGR_SCLDEL_Pos
Definition stm32h723xx.h:13200
I2C_CR2_RD_WRN_Pos
#define I2C_CR2_RD_WRN_Pos
Definition stm32h723xx.h:13115
I2C_CR1_NOSTRETCH
#define I2C_CR1_NOSTRETCH
Clock stretching disable.
Definition stm32h723xx.h:13091
I2C_CR2_SADD
#define I2C_CR2_SADD
Slave address (master mode).
Definition stm32h723xx.h:13114
I2C_ICR_ARLOCF
#define I2C_ICR_ARLOCF
Arbitration lost clear flag.
Definition stm32h723xx.h:13292
I2C_CR1_TXDMAEN
#define I2C_CR1_TXDMAEN
DMA transmission requests enable.
Definition stm32h723xx.h:13082
I2C_ISR_TXE
#define I2C_ISR_TXE
Transmit data register empty.
Definition stm32h723xx.h:13227
I2C_TIMINGR_SCLH
#define I2C_TIMINGR_SCLH
SCL high period (master mode).
Definition stm32h723xx.h:13196
I2C_CR1_STOPIE
#define I2C_CR1_STOPIE
STOP detection interrupt enable.
Definition stm32h723xx.h:13067
I2C_CR1_ALERTEN
#define I2C_CR1_ALERTEN
SMBus alert enable.
Definition stm32h723xx.h:13106
I2C_CR2_RELOAD
#define I2C_CR2_RELOAD
NBYTES reload mode.
Definition stm32h723xx.h:13138
I2C_CR2_NBYTES
#define I2C_CR2_NBYTES
Number of bytes.
Definition stm32h723xx.h:13135
I2C_ISR_STOPF
#define I2C_ISR_STOPF
STOP detection flag.
Definition stm32h723xx.h:13242
I2C_CR2_RD_WRN
#define I2C_CR2_RD_WRN
Transfer direction (master mode).
Definition stm32h723xx.h:13117
I2C_CR1_ADDRIE
#define I2C_CR1_ADDRIE
Address match interrupt enable.
Definition stm32h723xx.h:13061
I2C_ISR_ADDCODE_Pos
#define I2C_ISR_ADDCODE_Pos
Definition stm32h723xx.h:13273
I2C_TIMEOUTR_TIMEOUTB_Pos
#define I2C_TIMEOUTR_TIMEOUTB_Pos
Definition stm32h723xx.h:13217
I2C_OAR2_OA2MSK
#define I2C_OAR2_OA2MSK
Own address 2 masks.
Definition stm32h723xx.h:13163
I2C_CR2_HEAD10R
#define I2C_CR2_HEAD10R
10-bit address header only read direction (master mode)
Definition stm32h723xx.h:13123
I2C_TIMINGR_SCLL_Pos
#define I2C_TIMINGR_SCLL_Pos
Definition stm32h723xx.h:13191
I2C_CR2_STOP
#define I2C_CR2_STOP
STOP generation (master mode).
Definition stm32h723xx.h:13129
I2C_CR1_PECEN
#define I2C_CR1_PECEN
PEC enable.
Definition stm32h723xx.h:13109
I2C_TIMINGR_SDADEL
#define I2C_TIMINGR_SDADEL
Data hold time.
Definition stm32h723xx.h:13199
I2C_OAR2_OA2
#define I2C_OAR2_OA2
Interface own address 2.
Definition stm32h723xx.h:13160
I2C_TIMEOUTR_TIMOUTEN
#define I2C_TIMEOUTR_TIMOUTEN
Clock timeout enable.
Definition stm32h723xx.h:13216
I2C_CR1_ANFOFF
#define I2C_CR1_ANFOFF
Analog noise filter OFF.
Definition stm32h723xx.h:13079
I2C_ISR_ALERT
#define I2C_ISR_ALERT
SMBus alert.
Definition stm32h723xx.h:13266
I2C_CR2_NBYTES_Pos
#define I2C_CR2_NBYTES_Pos
Definition stm32h723xx.h:13133
I2C_CR2_ADD10
#define I2C_CR2_ADD10
10-bit addressing mode (master mode)
Definition stm32h723xx.h:13120
I2C_RXDR_RXDATA
#define I2C_RXDR_RXDATA
8-bit receive data
Definition stm32h723xx.h:13314
I2C_ISR_ARLO
#define I2C_ISR_ARLO
Arbitration lost.
Definition stm32h723xx.h:13254
I2C_CR2_START
#define I2C_CR2_START
START generation.
Definition stm32h723xx.h:13126
I2C_ICR_OVRCF
#define I2C_ICR_OVRCF
Overrun/Underrun clear flag.
Definition stm32h723xx.h:13295
I2C_TIMEOUTR_TIMEOUTB
#define I2C_TIMEOUTR_TIMEOUTB
Bus timeout B.
Definition stm32h723xx.h:13219
I2C_OAR1_OA1MODE
#define I2C_OAR1_OA1MODE
Own address 1 10-bit mode.
Definition stm32h723xx.h:13152
I2C_ISR_TIMEOUT
#define I2C_ISR_TIMEOUT
Timeout or Tlow detection flag.
Definition stm32h723xx.h:13263
I2C_CR1_SMBDEN
#define I2C_CR1_SMBDEN
SMBus device default address enable.
Definition stm32h723xx.h:13103
I2C_CR2_PECBYTE
#define I2C_CR2_PECBYTE
Packet error checking byte.
Definition stm32h723xx.h:13144
I2C_CR1_TCIE
#define I2C_CR1_TCIE
Transfer complete interrupt enable.
Definition stm32h723xx.h:13070
I2C_TIMINGR_SDADEL_Pos
#define I2C_TIMINGR_SDADEL_Pos
Definition stm32h723xx.h:13197
I2C_CR1_WUPEN
#define I2C_CR1_WUPEN
Wakeup from STOP enable.
Definition stm32h723xx.h:13094
I2C_CR1_ERRIE
#define I2C_CR1_ERRIE
Errors interrupt enable.
Definition stm32h723xx.h:13073
I2C_ISR_TCR
#define I2C_ISR_TCR
Transfer complete reload.
Definition stm32h723xx.h:13248
I2C_TIMINGR_SCLH_Pos
#define I2C_TIMINGR_SCLH_Pos
Definition stm32h723xx.h:13194
I2C_ICR_PECCF
#define I2C_ICR_PECCF
PAC error clear flag.
Definition stm32h723xx.h:13298
I2C_CR1_RXDMAEN
#define I2C_CR1_RXDMAEN
DMA reception requests enable.
Definition stm32h723xx.h:13085
I2C_ISR_PECERR
#define I2C_ISR_PECERR
PEC error in reception.
Definition stm32h723xx.h:13260
I2C_CR2_NACK
#define I2C_CR2_NACK
NACK generation (slave mode).
Definition stm32h723xx.h:13132
I2C_CR1_TXIE
#define I2C_CR1_TXIE
TX interrupt enable.
Definition stm32h723xx.h:13055
I2C_ISR_ADDCODE
#define I2C_ISR_ADDCODE
Address match code (slave mode).
Definition stm32h723xx.h:13275
I2C_TIMINGR_SCLDEL
#define I2C_TIMINGR_SCLDEL
Data setup time.
Definition stm32h723xx.h:13202
I2C_CR1_PE
#define I2C_CR1_PE
Peripheral enable.
Definition stm32h723xx.h:13052
I2C_TIMEOUTR_TEXTEN
#define I2C_TIMEOUTR_TEXTEN
Extended clock timeout enable.
Definition stm32h723xx.h:13222
I2C_CR1_SBC
#define I2C_CR1_SBC
Slave byte control.
Definition stm32h723xx.h:13088
I2C_ICR_BERRCF
#define I2C_ICR_BERRCF
Bus error clear flag.
Definition stm32h723xx.h:13289
I2C_ICR_TIMOUTCF
#define I2C_ICR_TIMOUTCF
Timeout clear flag.
Definition stm32h723xx.h:13301
I2C_ISR_DIR
#define I2C_ISR_DIR
Transfer direction (slave mode).
Definition stm32h723xx.h:13272
I2C_OAR2_OA2EN
#define I2C_OAR2_OA2EN
Own address 2 enable.
Definition stm32h723xx.h:13188
I2C_ISR_TXIS
#define I2C_ISR_TXIS
Transmit interrupt status.
Definition stm32h723xx.h:13230
I2C_TIMEOUTR_TIDLE
#define I2C_TIMEOUTR_TIDLE
Idle clock timeout detection.
Definition stm32h723xx.h:13213
I2C_OAR1_OA1EN
#define I2C_OAR1_OA1EN
Own address 1 enable.
Definition stm32h723xx.h:13155
I2C_ICR_NACKCF
#define I2C_ICR_NACKCF
NACK clear flag.
Definition stm32h723xx.h:13283
I2C_OAR1_OA1
#define I2C_OAR1_OA1
Interface own address 1.
Definition stm32h723xx.h:13149
I2C_CR2_AUTOEND
#define I2C_CR2_AUTOEND
Automatic end mode (master mode).
Definition stm32h723xx.h:13141
I2C_ICR_STOPCF
#define I2C_ICR_STOPCF
STOP detection clear flag.
Definition stm32h723xx.h:13286
I2C_CR1_GCEN
#define I2C_CR1_GCEN
General call enable.
Definition stm32h723xx.h:13097
I2C_PECR_PEC
#define I2C_PECR_PEC
PEC register.
Definition stm32h723xx.h:13309
I2C_ICR_ADDRCF
#define I2C_ICR_ADDRCF
Address matched clear flag.
Definition stm32h723xx.h:13280
I2C_ISR_TC
#define I2C_ISR_TC
Transfer complete (master mode).
Definition stm32h723xx.h:13245
I2C_TIMEOUTR_TIMEOUTA
#define I2C_TIMEOUTR_TIMEOUTA
Bus timeout A.
Definition stm32h723xx.h:13210
I2C_CR1_SMBHEN
#define I2C_CR1_SMBHEN
SMBus host address enable.
Definition stm32h723xx.h:13100
I2C_TIMINGR_SCLL
#define I2C_TIMINGR_SCLL
SCL low period (master mode).
Definition stm32h723xx.h:13193
I2C_ISR_NACKF
#define I2C_ISR_NACKF
NACK received flag.
Definition stm32h723xx.h:13239
I2C_CR1_DNF_Pos
#define I2C_CR1_DNF_Pos
Definition stm32h723xx.h:13074
I2C_CR1_DNF
#define I2C_CR1_DNF
Digital noise filter.
Definition stm32h723xx.h:13076
I2C_CR1_NACKIE
#define I2C_CR1_NACKIE
NACK received interrupt enable.
Definition stm32h723xx.h:13064
I2C_TIMINGR_PRESC
#define I2C_TIMINGR_PRESC
Timings prescaler.
Definition stm32h723xx.h:13205
I2C_ICR_ALERTCF
#define I2C_ICR_ALERTCF
Alert clear flag.
Definition stm32h723xx.h:13304
I2C_CR1_RXIE
#define I2C_CR1_RXIE
RX interrupt enable.
Definition stm32h723xx.h:13058
I2C_ISR_OVR
#define I2C_ISR_OVR
Overrun/Underrun.
Definition stm32h723xx.h:13257
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition stm32h723xx.h:1133
I2C_TypeDef::ISR
__IO uint32_t ISR
I2C Interrupt and status register, Address offset: 0x18.
Definition stm32h723xx.h:1140
I2C_TypeDef::CR2
__IO uint32_t CR2
I2C Control register 2, Address offset: 0x04.
Definition stm32h723xx.h:1135
I2C_TypeDef::RXDR
__IO uint32_t RXDR
I2C Receive data register, Address offset: 0x24.
Definition stm32h723xx.h:1143
I2C_TypeDef::PECR
__IO uint32_t PECR
I2C PEC register, Address offset: 0x20.
Definition stm32h723xx.h:1142
I2C_TypeDef::OAR2
__IO uint32_t OAR2
I2C Own address 2 register, Address offset: 0x0C.
Definition stm32h723xx.h:1137
I2C_TypeDef::ICR
__IO uint32_t ICR
I2C Interrupt clear register, Address offset: 0x1C.
Definition stm32h723xx.h:1141
I2C_TypeDef::CR1
__IO uint32_t CR1
I2C Control register 1, Address offset: 0x00.
Definition stm32h723xx.h:1134
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
I2C Timing register, Address offset: 0x10.
Definition stm32h723xx.h:1138
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
I2C Timeout register, Address offset: 0x14.
Definition stm32h723xx.h:1139
I2C_TypeDef::TXDR
__IO uint32_t TXDR
I2C Transmit data register, Address offset: 0x28.
Definition stm32h723xx.h:1144
I2C_TypeDef::OAR1
__IO uint32_t OAR1
I2C Own address 1 register, Address offset: 0x08.
Definition stm32h723xx.h:1136