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stm32h7xx_ll_pwr.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_PWR_H
21#define STM32H7xx_LL_PWR_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined (PWR)
35
36/** @defgroup PWR_LL PWR
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private constants ---------------------------------------------------------*/
43/** @defgroup PWR_LL_Private_Constants PWR Private Constants
44 * @{
45 */
46
47/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
48 * @brief Flags defines which can be used with LL_PWR_WriteReg function
49 * @{
50 */
51/* Wake-Up Pins PWR register offsets */
52#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
53#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
54/**
55 * @}
56 */
57/**
58 * @}
59 */
60/* Private macros ------------------------------------------------------------*/
61/* Exported types ------------------------------------------------------------*/
62/* Exported constants --------------------------------------------------------*/
63/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
64 * @{
65 */
66
67/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
69 * @{
70 */
71#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */
72#if defined (DUAL_CORE)
73#define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */
74#endif /* DUAL_CORE */
75#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */
76#if defined (PWR_WKUPCR_WKUPC5)
77#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */
78#endif /* defined (PWR_WKUPCR_WKUPC5) */
79#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */
80#if defined (PWR_WKUPCR_WKUPC3)
81#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */
82#endif /* defined (PWR_WKUPCR_WKUPC3) */
83#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */
84#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */
85/**
86 * @}
87 */
88
89/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
90 * @brief Flags defines which can be used with LL_PWR_ReadReg function
91 * @{
92 */
93#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */
94#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */
95#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */
96#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
97#if defined (PWR_CSR1_MMCVDO)
98#define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */
99#endif /* PWR_CSR1_MMCVDO */
100
101#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */
102#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */
103#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */
104#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */
105#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */
106
107#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */
108#define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */
109
110#if defined (PWR_CPUCR_SBF_D2)
111#define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */
112#endif /* PWR_CPUCR_SBF_D2 */
113#if defined (PWR_CPUCR_SBF_D1)
114#define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */
115#endif /* PWR_CPUCR_SBF_D1 */
116#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */
117#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */
118#if defined (DUAL_CORE)
119#define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */
120#endif /* DUAL_CORE */
121
122#if defined (DUAL_CORE)
123#define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */
124#define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */
125#define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */
126#define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */
127#define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */
128#endif /* DUAL_CORE */
129
130#if defined (PWR_CPUCR_PDDS_D2)
131#define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */
132#else
133#define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */
134#endif /* PWR_CPUCR_PDDS_D2 */
135
136#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */
137#if defined (PWR_WKUPFR_WKUPF5)
138#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
139#endif /* defined (PWR_WKUPFR_WKUPF5) */
140#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
141#if defined (PWR_WKUPFR_WKUPF3)
142#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */
143#endif /* defined (PWR_WKUPFR_WKUPF3) */
144#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
145#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
146/**
147 * @}
148 */
149
150/** @defgroup PWR_LL_EC_MODE_PWR Power mode
151 * @{
152 */
153#if defined (PWR_CPUCR_PDDS_D2)
154#define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */
155#define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */
156#else
157#define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */
158#define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */
159#endif /* PWR_CPUCR_PDDS_D2 */
160
161#if defined (PWR_CPUCR_PDDS_D2)
162#define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */
163#define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */
164#endif /* PWR_CPUCR_PDDS_D2 */
165
166#if defined (PWR_CPUCR_PDDS_D2)
167#define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */
168#define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */
169#define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */
170#else
171#define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */
172#define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */
173#define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */
174#endif /* PWR_CPUCR_PDDS_D2 */
175
176#if defined (DUAL_CORE)
177#define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */
178#define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */
179#define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */
180#define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */
181#define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */
182#define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */
183#define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */
184#endif /* DUAL_CORE */
185/**
186 * @}
187 */
188
189/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
190 * @{
191 */
192#if defined (PWR_CPUCR_PDDS_D2)
193#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */
194#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */
195#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
196#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
197#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
198#else
199#define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */
200#endif /* defined (SYSCFG_PWRCR_ODEN) */
201#else
202#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */
203#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */
204#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */
205#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
206#endif /* PWR_CPUCR_PDDS_D2 */
207/**
208 * @}
209 */
210
211/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
212 * @{
213 */
214#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */
215#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */
216#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
217/**
218 * @}
219 */
220
221/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
222 * @{
223 */
224#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
225#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */
226/**
227 * @}
228 */
229
230/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
231 * @{
232 */
233#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */
234#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */
235#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */
236#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */
237#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */
238#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */
239#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */
240#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
241/**
242 * @}
243 */
244
245/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
246 * @{
247 */
248#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */
249#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */
250#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */
251#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */
252
253/**
254 * @}
255 */
256
257/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
258 * @{
259 */
260#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */
261#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */
262/**
263 * @}
264 */
265
266/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
267 * @{
268 */
269#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */
270#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */
271#if defined (PWR_WKUPEPR_WKUPEN3)
272#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */
273#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
274#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */
275#if defined (PWR_WKUPEPR_WKUPEN5)
276#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */
277#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
278#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */
279/**
280 * @}
281 */
282
283/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
284 * @{
285 */
286#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */
287#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */
288#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */
289/**
290 * @}
291 */
292
293/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
294 * @{
295 */
296#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */
297#if defined (SMPS)
298#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */
299#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
300#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
301#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
302#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
303#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
304#define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
305#endif /* SMPS */
306#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */
307/**
308 * @}
309 */
310
311/**
312 * @}
313 */
314/* Exported macro ------------------------------------------------------------*/
315/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
316 * @{
317 */
318
319/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
320 * @{
321 */
322
323/**
324 * @brief Write a value in PWR register
325 * @param __REG__ Register to be written
326 * @param __VALUE__ Value to be written in the register
327 * @retval None
328 */
329#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
330
331/**
332 * @brief Read a value in PWR register
333 * @param __REG__ Register to be read
334 * @retval Register value
335 */
336#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
337/**
338 * @}
339 */
340
341/**
342 * @}
343 */
344/* Exported functions --------------------------------------------------------*/
345/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
346 * @{
347 */
348
349/** @defgroup PWR_LL_EF_Configuration Configuration
350 * @{
351 */
352
353 /**
354 * @brief Set the voltage Regulator mode during deep sleep mode
355 * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS
356 * @param RegulMode This parameter can be one of the following values:
357 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
358 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
359 * @retval None
360 */
361__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
362{
363 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
364}
365
366/**
367 * @brief Get the voltage Regulator mode during deep sleep mode
368 * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS
369 * @retval Returned value can be one of the following values:
370 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
371 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
372 */
373__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
374{
375 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
376}
377
378/**
379 * @brief Enable Power Voltage Detector
380 * @rmtoll CR1 PVDEN LL_PWR_EnablePVD
381 * @retval None
382 */
383__STATIC_INLINE void LL_PWR_EnablePVD(void)
384{
385 SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
386}
387
388/**
389 * @brief Disable Power Voltage Detector
390 * @rmtoll CR1 PVDEN LL_PWR_DisablePVD
391 * @retval None
392 */
393__STATIC_INLINE void LL_PWR_DisablePVD(void)
394{
395 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
396}
397
398/**
399 * @brief Check if Power Voltage Detector is enabled
400 * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD
401 * @retval State of bit (1 or 0).
402 */
403__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
404{
405 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
406}
407
408/**
409 * @brief Configure the voltage threshold detected by the Power Voltage Detector
410 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel
411 * @param PVDLevel This parameter can be one of the following values:
412 * @arg @ref LL_PWR_PVDLEVEL_0
413 * @arg @ref LL_PWR_PVDLEVEL_1
414 * @arg @ref LL_PWR_PVDLEVEL_2
415 * @arg @ref LL_PWR_PVDLEVEL_3
416 * @arg @ref LL_PWR_PVDLEVEL_4
417 * @arg @ref LL_PWR_PVDLEVEL_5
418 * @arg @ref LL_PWR_PVDLEVEL_6
419 * @arg @ref LL_PWR_PVDLEVEL_7
420 * @retval None
421 */
422__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
423{
424 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
425}
426
427/**
428 * @brief Get the voltage threshold detection
429 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel
430 * @retval Returned value can be one of the following values:
431 * @arg @ref LL_PWR_PVDLEVEL_0
432 * @arg @ref LL_PWR_PVDLEVEL_1
433 * @arg @ref LL_PWR_PVDLEVEL_2
434 * @arg @ref LL_PWR_PVDLEVEL_3
435 * @arg @ref LL_PWR_PVDLEVEL_4
436 * @arg @ref LL_PWR_PVDLEVEL_5
437 * @arg @ref LL_PWR_PVDLEVEL_6
438 * @arg @ref LL_PWR_PVDLEVEL_7
439 */
440__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
441{
442 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
443}
444
445/**
446 * @brief Enable access to the backup domain
447 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
448 * @retval None
449 */
450__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
451{
452 SET_BIT(PWR->CR1, PWR_CR1_DBP);
453}
454
455/**
456 * @brief Disable access to the backup domain
457 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
458 * @retval None
459 */
460__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
461{
462 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
463}
464
465/**
466 * @brief Check if the backup domain is enabled
467 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
468 * @retval State of bit (1 or 0).
469 */
470__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
471{
472 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
473}
474
475/**
476 * @brief Enable the Flash Power Down in Stop Mode
477 * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown
478 * @retval None
479 */
480__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
481{
482 SET_BIT(PWR->CR1, PWR_CR1_FLPS);
483}
484
485/**
486 * @brief Disable the Flash Power Down in Stop Mode
487 * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown
488 * @retval None
489 */
490__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
491{
492 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
493}
494
495/**
496 * @brief Check if the Flash Power Down in Stop Mode is enabled
497 * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown
498 * @retval State of bit (1 or 0).
499 */
500__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
501{
502 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
503}
504
505#if defined (PWR_CR1_BOOSTE)
506/**
507 * @brief Enable the Analog Voltage Booster (VDDA)
508 * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster
509 * @retval None
510 */
511__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
512{
513 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
514}
515
516/**
517 * @brief Disable the Analog Voltage Booster (VDDA)
518 * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster
519 * @retval None
520 */
521__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
522{
523 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
524}
525
526/**
527 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
528 * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster
529 * @retval State of bit (1 or 0).
530 */
531__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
532{
533 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
534}
535#endif /* PWR_CR1_BOOSTE */
536
537#if defined (PWR_CR1_AVD_READY)
538/**
539 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
540 * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady
541 * @retval None
542 */
543__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
544{
545 SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
546}
547
548/**
549 * @brief Disable the Analog Voltage Ready (VDDA)
550 * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady
551 * @retval None
552 */
553__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
554{
555 CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
556}
557
558/**
559 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
560 * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady
561 * @retval State of bit (1 or 0).
562 */
563__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
564{
565 return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
566}
567#endif /* PWR_CR1_AVD_READY */
568
569/**
570 * @brief Set the internal Regulator output voltage in STOP mode
571 * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
572 * @param VoltageScaling This parameter can be one of the following values:
573 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
574 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
575 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
576 * @retval None
577 */
578__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
579{
580 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
581}
582
583/**
584 * @brief Get the internal Regulator output voltage in STOP mode
585 * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
586 * @retval Returned value can be one of the following values:
587 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
588 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
589 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
590 */
591__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
592{
593 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
594}
595
596/**
597 * @brief Enable Analog Power Voltage Detector
598 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD
599 * @retval None
600 */
601__STATIC_INLINE void LL_PWR_EnableAVD(void)
602{
603 SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
604}
605
606/**
607 * @brief Disable Analog Power Voltage Detector
608 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD
609 * @retval None
610 */
611__STATIC_INLINE void LL_PWR_DisableAVD(void)
612{
613 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
614}
615
616/**
617 * @brief Check if Analog Power Voltage Detector is enabled
618 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
619 * @retval State of bit (1 or 0).
620 */
621__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
622{
623 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
624}
625
626/**
627 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
628 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel
629 * @param AVDLevel This parameter can be one of the following values:
630 * @arg @ref LL_PWR_AVDLEVEL_0
631 * @arg @ref LL_PWR_AVDLEVEL_1
632 * @arg @ref LL_PWR_AVDLEVEL_2
633 * @arg @ref LL_PWR_AVDLEVEL_3
634 * @retval None
635 */
636__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
637{
638 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
639}
640
641/**
642 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
643 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
644 * @retval Returned value can be one of the following values:
645 * @arg @ref LL_PWR_AVDLEVEL_0
646 * @arg @ref LL_PWR_AVDLEVEL_1
647 * @arg @ref LL_PWR_AVDLEVEL_2
648 * @arg @ref LL_PWR_AVDLEVEL_3
649 */
650__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
651{
652 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
653}
654
655#if defined (PWR_CR1_AXIRAM1SO)
656/**
657 * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode
658 * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff
659 * @retval None
660 */
661__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
662{
663 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
664}
665
666/**
667 * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode
668 * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff
669 * @retval None
670 */
671__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
672{
673 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
674}
675
676/**
677 * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
678 * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff
679 * @retval State of bit (1 or 0).
680 */
681__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
682{
683 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
684}
685#endif /* PWR_CR1_AXIRAM1SO */
686
687#if defined (PWR_CR1_AXIRAM2SO)
688/**
689 * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode
690 * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff
691 * @retval None
692 */
693__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
694{
695 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
696}
697
698/**
699 * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode
700 * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff
701 * @retval None
702 */
703__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
704{
705 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
706}
707
708/**
709 * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
710 * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff
711 * @retval State of bit (1 or 0).
712 */
713__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
714{
715 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
716}
717#endif /* PWR_CR1_AXIRAM2SO */
718
719#if defined (PWR_CR1_AXIRAM3SO)
720/**
721 * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode
722 * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff
723 * @retval None
724 */
725__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
726{
727 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
728}
729
730/**
731 * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode
732 * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff
733 * @retval None
734 */
735__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
736{
737 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
738}
739
740/**
741 * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
742 * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff
743 * @retval State of bit (1 or 0).
744 */
745__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
746{
747 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
748}
749#endif /* PWR_CR1_AXIRAM3SO */
750
751#if defined (PWR_CR1_AHBRAM1SO)
752/**
753 * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode
754 * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff
755 * @retval None
756 */
757__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
758{
759 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
760}
761
762/**
763 * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode
764 * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff
765 * @retval None
766 */
767__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
768{
769 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
770}
771
772/**
773 * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
774 * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff
775 * @retval State of bit (1 or 0).
776 */
777__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
778{
779 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
780}
781#endif /* PWR_CR1_AHBRAM1SO */
782
783#if defined (PWR_CR1_AHBRAM2SO)
784/**
785 * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode
786 * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff
787 * @retval None
788 */
789__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
790{
791 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
792}
793
794/**
795 * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode
796 * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff
797 * @retval None
798 */
799__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
800{
801 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
802}
803
804/**
805 * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
806 * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff
807 * @retval State of bit (1 or 0).
808 */
809__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
810{
811 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
812}
813#endif /* PWR_CR1_AHBRAM2SO */
814
815#if defined (PWR_CR1_ITCMSO)
816/**
817 * @brief Enable the ITCM shut-off in DStop/DStop2 mode
818 * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff
819 * @retval None
820 */
821__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
822{
823 SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
824}
825
826/**
827 * @brief Disable the ITCM shut-off in DStop/DStop2 mode
828 * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff
829 * @retval None
830 */
831__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
832{
833 CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
834}
835
836/**
837 * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled
838 * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff
839 * @retval State of bit (1 or 0).
840 */
841__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
842{
843 return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
844}
845#endif /* PWR_CR1_ITCMSO */
846
847#if defined (PWR_CR1_HSITFSO)
848/**
849 * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode
850 * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff
851 * @retval None
852 */
853__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
854{
855 SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
856}
857
858/**
859 * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode
860 * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff
861 * @retval None
862 */
863__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
864{
865 CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
866}
867
868/**
869 * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
870 * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff
871 * @retval State of bit (1 or 0).
872 */
873__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
874{
875 return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
876}
877#endif /* PWR_CR1_HSITFSO */
878
879#if defined (PWR_CR1_SRDRAMSO)
880/**
881 * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
882 * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff
883 * @retval None
884 */
885__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
886{
887 SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
888}
889
890/**
891 * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
892 * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff
893 * @retval None
894 */
895__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
896{
897 CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
898}
899
900/**
901 * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
902 * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff
903 * @retval State of bit (1 or 0).
904 */
905__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
906{
907 return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
908}
909#endif /* PWR_CR1_SRDRAMSO */
910
911/**
912 * @brief Enable Backup Regulator
913 * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator
914 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
915 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
916 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
917 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
918 * the data written into the RAM will be maintained in the Standby and VBAT modes.
919 * @retval None
920 */
921__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
922{
923 SET_BIT(PWR->CR2, PWR_CR2_BREN);
924}
925
926/**
927 * @brief Disable Backup Regulator
928 * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator
929 * @retval None
930 */
931__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
932{
933 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
934}
935
936/**
937 * @brief Check if the backup Regulator is enabled
938 * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator
939 * @retval State of bit (1 or 0).
940 */
941__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
942{
943 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
944}
945
946/**
947 * @brief Enable VBAT and Temperature monitoring
948 * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring
949 * @retval None
950 */
951__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
952{
953 SET_BIT(PWR->CR2, PWR_CR2_MONEN);
954}
955
956/**
957 * @brief Disable VBAT and Temperature monitoring
958 * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring
959 * @retval None
960 */
961__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
962{
963 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
964}
965
966/**
967 * @brief Check if the VBAT and Temperature monitoring is enabled
968 * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring
969 * @retval State of bit (1 or 0).
970 */
971__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
972{
973 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
974}
975
976#if defined (SMPS)
977/**
978 * @brief Configure the PWR supply
979 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
980 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
981 * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply
982 * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply
983 * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply
984 * @param SupplySource This parameter can be one of the following values:
985 * @arg @ref LL_PWR_LDO_SUPPLY
986 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
987 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
988 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
989 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
990 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
991 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
992 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
993 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
994 * @retval None
995 */
996__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
997{
998 /* Set the power supply configuration */
999 MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
1000}
1001#else
1002/**
1003 * @brief Configure the PWR supply
1004 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
1005 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
1006 * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply
1007 * @param SupplySource This parameter can be one of the following values:
1008 * @arg @ref LL_PWR_LDO_SUPPLY
1009 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1010 * @retval None
1011 */
1012__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
1013{
1014 /* Set the power supply configuration */
1015 MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
1016}
1017#endif /* defined (SMPS) */
1018
1019#if defined (SMPS)
1020/**
1021 * @brief Get the PWR supply
1022 * @rmtoll CR3 BYPASS LL_PWR_GetSupply
1023 * @rmtoll CR3 LDOEN LL_PWR_GetSupply
1024 * @rmtoll CR3 SMPSEN LL_PWR_GetSupply
1025 * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply
1026 * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply
1027 * @retval Returned value can be one of the following values:
1028 * @arg @ref LL_PWR_LDO_SUPPLY
1029 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
1030 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
1031 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
1032 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
1033 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
1034 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
1035 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
1036 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1037 */
1038__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
1039{
1040 /* Get the power supply configuration */
1041 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
1042}
1043#else
1044/**
1045 * @brief Get the PWR supply
1046 * @rmtoll CR3 BYPASS LL_PWR_GetSupply
1047 * @rmtoll CR3 LDOEN LL_PWR_GetSupply
1048 * @rmtoll CR3 SCUEN LL_PWR_GetSupply
1049 * @retval Returned value can be one of the following values:
1050 * @arg @ref LL_PWR_LDO_SUPPLY
1051 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1052 */
1053__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
1054{
1055 /* Get the power supply configuration */
1056 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
1057}
1058#endif /* defined (SMPS) */
1059
1060/**
1061 * @brief Enable battery charging
1062 * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging
1063 * @retval None
1064 */
1065__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
1066{
1067 SET_BIT(PWR->CR3, PWR_CR3_VBE);
1068}
1069
1070/**
1071 * @brief Disable battery charging
1072 * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging
1073 * @retval None
1074 */
1075__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
1076{
1077 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
1078}
1079
1080/**
1081 * @brief Check if battery charging is enabled
1082 * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging
1083 * @retval State of bit (1 or 0).
1084 */
1085__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1086{
1087 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
1088}
1089
1090/**
1091 * @brief Set the Battery charge resistor impedance
1092 * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor
1093 * @param Resistor This parameter can be one of the following values:
1094 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1095 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1096 * @retval None
1097 */
1098__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
1099{
1100 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
1101}
1102
1103/**
1104 * @brief Get the Battery charge resistor impedance
1105 * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor
1106 * @retval Returned value can be one of the following values:
1107 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1108 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1109 */
1110__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
1111{
1112 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
1113}
1114
1115/**
1116 * @brief Enable the USB regulator
1117 * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg
1118 * @retval None
1119 */
1120__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
1121{
1122 SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
1123}
1124
1125/**
1126 * @brief Disable the USB regulator
1127 * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg
1128 * @retval None
1129 */
1130__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
1131{
1132 CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
1133}
1134
1135/**
1136 * @brief Check if the USB regulator is enabled
1137 * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg
1138 * @retval State of bit (1 or 0).
1139 */
1140__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
1141{
1142 return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
1143}
1144
1145/**
1146 * @brief Enable the USB voltage detector
1147 * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
1148 * @retval None
1149 */
1150__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
1151{
1152 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
1153}
1154
1155/**
1156 * @brief Disable the USB voltage detector
1157 * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
1158 * @retval None
1159 */
1160__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
1161{
1162 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
1163}
1164
1165/**
1166 * @brief Check if the USB voltage detector is enabled
1167 * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
1168 * @retval State of bit (1 or 0).
1169 */
1170__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
1171{
1172 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
1173}
1174
1175#if defined (PWR_CPUCR_PDDS_D2)
1176/**
1177 * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep
1178 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode
1179 * @param PDMode This parameter can be one of the following values:
1180 * @arg @ref LL_PWR_CPU_MODE_D1STOP
1181 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY
1182 * @retval None
1183 */
1184__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
1185{
1186 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
1187}
1188#else
1189/**
1190 * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep
1191 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode
1192 * @param PDMode This parameter can be one of the following values:
1193 * @arg @ref LL_PWR_CPU_MODE_CDSTOP
1194 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2
1195 * @retval None
1196 */
1197__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
1198{
1199 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
1200}
1201#endif /* PWR_CPUCR_PDDS_D2 */
1202
1203#if defined (DUAL_CORE)
1204/**
1205 * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep
1206 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode
1207 * @param PDMode This parameter can be one of the following values:
1208 * @arg @ref LL_PWR_CPU2_MODE_D1STOP
1209 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
1210 * @retval None
1211 */
1212__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
1213{
1214 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
1215}
1216#endif /* DUAL_CORE */
1217
1218#if defined (PWR_CPUCR_PDDS_D2)
1219/**
1220 * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep
1221 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode
1222 * @retval Returned value can be one of the following values:
1223 * @arg @ref LL_PWR_CPU_MODE_D1STOP
1224 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY
1225 */
1226__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
1227{
1228 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
1229}
1230#else
1231/**
1232 * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep
1233 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode
1234 * @retval Returned value can be one of the following values:
1235 * @arg @ref LL_PWR_CPU_MODE_CDSTOP
1236 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2
1237 */
1238__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
1239{
1240 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
1241}
1242#endif /* PWR_CPUCR_PDDS_D2 */
1243
1244#if defined (DUAL_CORE)
1245/**
1246 * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
1247 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode
1248 * @retval Returned value can be one of the following values:
1249 * @arg @ref LL_PWR_CPU2_MODE_D1STOP
1250 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
1251 */
1252__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
1253{
1254 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
1255}
1256#endif /* DUAL_CORE */
1257
1258#if defined (PWR_CPUCR_PDDS_D2)
1259/**
1260 * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep
1261 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode
1262 * @param PDMode This parameter can be one of the following values:
1263 * @arg @ref LL_PWR_CPU_MODE_D2STOP
1264 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY
1265 * @retval None
1266 */
1267__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
1268{
1269 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
1270}
1271#endif /* PWR_CPUCR_PDDS_D2 */
1272
1273#if defined (DUAL_CORE)
1274/**
1275 * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep
1276 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode
1277 * @param PDMode This parameter can be one of the following values:
1278 * @arg @ref LL_PWR_CPU2_MODE_D2STOP
1279 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
1280 * @retval None
1281 */
1282__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
1283{
1284 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
1285}
1286#endif /* DUAL_CORE */
1287
1288#if defined (PWR_CPUCR_PDDS_D2)
1289/**
1290 * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep
1291 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode
1292 * @retval Returned value can be one of the following values:
1293 * @arg @ref LL_PWR_CPU_MODE_D2STOP
1294 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY
1295 */
1296__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
1297{
1298 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
1299}
1300#endif /* PWR_CPUCR_PDDS_D2 */
1301
1302#if defined (DUAL_CORE)
1303/**
1304 * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
1305 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode
1306 * @retval Returned value can be one of the following values:
1307 * @arg @ref LL_PWR_CPU2_MODE_D2STOP
1308 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
1309 */
1310__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
1311{
1312 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
1313}
1314#endif /* DUAL_CORE */
1315
1316#if defined (PWR_CPUCR_PDDS_D2)
1317/**
1318 * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep
1319 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode
1320 * @param PDMode This parameter can be one of the following values:
1321 * @arg @ref LL_PWR_CPU_MODE_D3STOP
1322 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY
1323 * @retval None
1324 */
1325__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
1326{
1327 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
1328}
1329#else
1330/**
1331 * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep
1332 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode
1333 * @param PDMode This parameter can be one of the following values:
1334 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP
1335 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
1336 * @retval None
1337 */
1338__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
1339{
1340 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
1341}
1342#endif /* PWR_CPUCR_PDDS_D2 */
1343
1344#if defined (DUAL_CORE)
1345/**
1346 * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep
1347 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode
1348 * @param PDMode This parameter can be one of the following values:
1349 * @arg @ref LL_PWR_CPU2_MODE_D3STOP
1350 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
1351 * @retval None
1352 */
1353__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
1354{
1355 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
1356}
1357#endif /* DUAL_CORE */
1358
1359#if defined (PWR_CPUCR_PDDS_D2)
1360/**
1361 * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep
1362 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode
1363 * @retval Returned value can be one of the following values:
1364 * @arg @ref LL_PWR_CPU_MODE_D3STOP
1365 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY
1366 */
1367__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
1368{
1369 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
1370}
1371#else
1372/**
1373 * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep
1374 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode
1375 * @retval Returned value can be one of the following values:
1376 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP
1377 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
1378 */
1379__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
1380{
1381 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
1382}
1383#endif /* PWR_CPUCR_PDDS_D2 */
1384
1385#if defined (DUAL_CORE)
1386/**
1387 * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
1388 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode
1389 * @retval Returned value can be one of the following values:
1390 * @arg @ref LL_PWR_CPU2_MODE_D3STOP
1391 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
1392 */
1393__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
1394{
1395 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
1396}
1397#endif /* DUAL_CORE */
1398
1399#if defined (DUAL_CORE)
1400/**
1401 * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode
1402 * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1
1403 * @retval None
1404 */
1405__STATIC_INLINE void LL_PWR_HoldCPU1(void)
1406{
1407 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1408}
1409
1410/**
1411 * @brief Release the CPU1 and allocated peripherals
1412 * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1
1413 * @retval None
1414 */
1415__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
1416{
1417 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1418}
1419
1420/**
1421 * @brief Ckeck if the CPU1 and allocated peripherals are held
1422 * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held
1423 * @retval State of bit (1 or 0).
1424 */
1425__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
1426{
1427 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL);
1428}
1429
1430/**
1431 * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode
1432 * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2
1433 * @retval None
1434 */
1435__STATIC_INLINE void LL_PWR_HoldCPU2(void)
1436{
1437 SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
1438}
1439
1440/**
1441 * @brief Release the CPU2 and allocated peripherals
1442 * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2
1443 * @retval None
1444 */
1445__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
1446{
1447 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
1448}
1449
1450/**
1451 * @brief Ckeck if the CPU2 and allocated peripherals are held
1452 * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held
1453 * @retval State of bit (1 or 0).
1454 */
1455__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
1456{
1457 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
1458}
1459#endif /* DUAL_CORE */
1460
1461#if defined (PWR_CPUCR_PDDS_D2)
1462/**
1463 * @brief D3 domain remains in Run mode regardless of CPU subsystem modes
1464 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode
1465 * @retval None
1466 */
1467__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
1468{
1469 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
1470}
1471#else
1472/**
1473 * @brief SRD domain remains in Run mode regardless of CPU subsystem modes
1474 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode
1475 * @retval None
1476 */
1477__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
1478{
1479 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
1480}
1481#endif /* PWR_CPUCR_PDDS_D2 */
1482
1483#if defined (DUAL_CORE)
1484/**
1485 * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes
1486 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode
1487 * @retval None
1488 */
1489__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
1490{
1491 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
1492}
1493#endif /* DUAL_CORE */
1494
1495#if defined (PWR_CPUCR_PDDS_D2)
1496/**
1497 * @brief D3 domain follows CPU subsystem modes
1498 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode
1499 * @retval None
1500 */
1501__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
1502{
1503 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
1504}
1505#else
1506/**
1507 * @brief SRD domain follows CPU subsystem modes
1508 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode
1509 * @retval None
1510 */
1511__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
1512{
1513 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
1514}
1515#endif /* PWR_CPUCR_PDDS_D2 */
1516
1517#if defined (DUAL_CORE)
1518/**
1519 * @brief D3 domain follows CPU2 subsystem modes
1520 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode
1521 * @retval None
1522 */
1523__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
1524{
1525 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
1526}
1527#endif /* DUAL_CORE */
1528
1529#if defined (PWR_CPUCR_PDDS_D2)
1530/**
1531 * @brief Check if D3 is kept in Run mode when CPU enters low power mode
1532 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
1533 * @retval State of bit (1 or 0).
1534 */
1535__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
1536{
1537 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
1538}
1539#else
1540/**
1541 * @brief Check if SRD is kept in Run mode when CPU enters low power mode
1542 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
1543 * @retval State of bit (1 or 0).
1544 */
1545__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
1546{
1547 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
1548}
1549#endif /* PWR_CPUCR_PDDS_D2 */
1550
1551#if defined (DUAL_CORE)
1552/**
1553 * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode
1554 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
1555 * @retval State of bit (1 or 0).
1556 */
1557__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
1558{
1559 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
1560}
1561#endif /* DUAL_CORE */
1562
1563/**
1564 * @brief Set the main internal Regulator output voltage
1565 * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling
1566 * @param VoltageScaling This parameter can be one of the following values:
1567 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1568 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1569 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1570 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1571 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
1572 * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1.
1573 * @retval None
1574 */
1575__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
1576{
1577#if defined (PWR_CPUCR_PDDS_D2)
1578 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
1579#else
1580 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
1581#endif /* PWR_CPUCR_PDDS_D2 */
1582}
1583
1584/**
1585 * @brief Get the main internal Regulator output voltage
1586 * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling
1587 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
1588 * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
1589 * @retval Returned value can be one of the following values:
1590 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1591 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1592 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1593 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1594 */
1595__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
1596{
1597#if defined (PWR_CPUCR_PDDS_D2)
1598 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
1599#else
1600 return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
1601#endif /* PWR_CPUCR_PDDS_D2 */
1602}
1603
1604/**
1605 * @brief Enable the WakeUp PINx functionality
1606 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n
1607 * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n
1608 * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n
1609 * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n
1610 * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n
1611 * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin
1612 * @param WakeUpPin This parameter can be one of the following values:
1613 * @arg @ref LL_PWR_WAKEUP_PIN1
1614 * @arg @ref LL_PWR_WAKEUP_PIN2
1615 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1616 * @arg @ref LL_PWR_WAKEUP_PIN4
1617 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1618 * @arg @ref LL_PWR_WAKEUP_PIN6
1619 *
1620 * (*) value not defined in all devices.
1621 *
1622 * @retval None
1623 */
1624__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1625{
1626 SET_BIT(PWR->WKUPEPR, WakeUpPin);
1627}
1628
1629/**
1630 * @brief Disable the WakeUp PINx functionality
1631 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n
1632 * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n
1633 * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n
1634 * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n
1635 * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n
1636 * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin
1637 * @param WakeUpPin This parameter can be one of the following values:
1638 * @arg @ref LL_PWR_WAKEUP_PIN1
1639 * @arg @ref LL_PWR_WAKEUP_PIN2
1640 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1641 * @arg @ref LL_PWR_WAKEUP_PIN4
1642 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1643 * @arg @ref LL_PWR_WAKEUP_PIN6
1644 *
1645 * (*) value not defined in all devices.
1646 *
1647 * @retval None
1648 */
1649__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1650{
1651 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
1652}
1653
1654/**
1655 * @brief Check if the WakeUp PINx functionality is enabled
1656 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
1657 * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
1658 * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
1659 * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n
1660 * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n
1661 * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
1662 * @param WakeUpPin This parameter can be one of the following values:
1663 * @arg @ref LL_PWR_WAKEUP_PIN1
1664 * @arg @ref LL_PWR_WAKEUP_PIN2
1665 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1666 * @arg @ref LL_PWR_WAKEUP_PIN4
1667 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1668 * @arg @ref LL_PWR_WAKEUP_PIN6
1669 *
1670 * (*) value not defined in all devices.
1671 *
1672 * @retval State of bit (1 or 0).
1673 */
1674__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1675{
1676 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1677}
1678
1679/**
1680 * @brief Set the Wake-Up pin polarity low for the event detection
1681 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1682 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1683 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1684 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1685 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1686 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
1687 * @param WakeUpPin This parameter can be one of the following values:
1688 * @arg @ref LL_PWR_WAKEUP_PIN1
1689 * @arg @ref LL_PWR_WAKEUP_PIN2
1690 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1691 * @arg @ref LL_PWR_WAKEUP_PIN4
1692 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1693 * @arg @ref LL_PWR_WAKEUP_PIN6
1694 *
1695 * (*) value not defined in all devices.
1696 *
1697 * @retval None
1698 */
1699__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1700{
1701 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1702}
1703
1704/**
1705 * @brief Set the Wake-Up pin polarity high for the event detection
1706 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1707 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1708 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1709 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1710 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
1711 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
1712 * @param WakeUpPin This parameter can be one of the following values:
1713 * @arg @ref LL_PWR_WAKEUP_PIN1
1714 * @arg @ref LL_PWR_WAKEUP_PIN2
1715 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1716 * @arg @ref LL_PWR_WAKEUP_PIN4
1717 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1718 * @arg @ref LL_PWR_WAKEUP_PIN6
1719 *
1720 * (*) value not defined in all devices.
1721 *
1722 * @retval None
1723 */
1724__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1725{
1726 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1727}
1728
1729/**
1730 * @brief Get the Wake-Up pin polarity for the event detection
1731 * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
1732 * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
1733 * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
1734 * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
1735 * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
1736 * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
1737 * @param WakeUpPin This parameter can be one of the following values:
1738 * @arg @ref LL_PWR_WAKEUP_PIN1
1739 * @arg @ref LL_PWR_WAKEUP_PIN2
1740 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1741 * @arg @ref LL_PWR_WAKEUP_PIN4
1742 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1743 * @arg @ref LL_PWR_WAKEUP_PIN6
1744 *
1745 * (*) value not defined in all devices.
1746 *
1747 * @retval State of bit (1 or 0).
1748 */
1749__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1750{
1751 return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
1752}
1753
1754/**
1755 * @brief Set the Wake-Up pin Pull None
1756 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
1757 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
1758 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
1759 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
1760 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
1761 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
1762 * @param WakeUpPin This parameter can be one of the following values:
1763 * @arg @ref LL_PWR_WAKEUP_PIN1
1764 * @arg @ref LL_PWR_WAKEUP_PIN2
1765 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1766 * @arg @ref LL_PWR_WAKEUP_PIN4
1767 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1768 * @arg @ref LL_PWR_WAKEUP_PIN6
1769 *
1770 * (*) value not defined in all devices.
1771 *
1772 * @retval None
1773 */
1774__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1775{
1776 MODIFY_REG(PWR->WKUPEPR, \
1777 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1778 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1779}
1780
1781/**
1782 * @brief Set the Wake-Up pin Pull Up
1783 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
1784 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
1785 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
1786 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
1787 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
1788 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
1789 * @param WakeUpPin This parameter can be one of the following values:
1790 * @arg @ref LL_PWR_WAKEUP_PIN1
1791 * @arg @ref LL_PWR_WAKEUP_PIN2
1792 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1793 * @arg @ref LL_PWR_WAKEUP_PIN4
1794 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1795 * @arg @ref LL_PWR_WAKEUP_PIN6
1796 *
1797 * (*) value not defined in all devices.
1798 *
1799 * @retval None
1800 */
1801__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1802{
1803 MODIFY_REG(PWR->WKUPEPR, \
1804 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1805 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1806}
1807
1808/**
1809 * @brief Set the Wake-Up pin Pull Down
1810 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
1811 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
1812 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
1813 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
1814 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
1815 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
1816 * @param WakeUpPin This parameter can be one of the following values:
1817 * @arg @ref LL_PWR_WAKEUP_PIN1
1818 * @arg @ref LL_PWR_WAKEUP_PIN2
1819 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1820 * @arg @ref LL_PWR_WAKEUP_PIN4
1821 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1822 * @arg @ref LL_PWR_WAKEUP_PIN6
1823 *
1824 * (*) value not defined in all devices.
1825 *
1826 * @retval None
1827 */
1828__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1829{
1830 MODIFY_REG(PWR->WKUPEPR, \
1831 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1832 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1833}
1834
1835/**
1836 * @brief Get the Wake-Up pin pull
1837 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
1838 * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
1839 * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
1840 * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n
1841 * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n
1842 * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
1843 * @param WakeUpPin This parameter can be one of the following values:
1844 * @arg @ref LL_PWR_WAKEUP_PIN1
1845 * @arg @ref LL_PWR_WAKEUP_PIN2
1846 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1847 * @arg @ref LL_PWR_WAKEUP_PIN4
1848 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1849 * @arg @ref LL_PWR_WAKEUP_PIN6
1850 *
1851 * (*) value not defined in all devices.
1852 *
1853 * @retval Returned value can be one of the following values:
1854 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1855 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1856 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1857 */
1858__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1859{
1860 uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1861
1862 return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1863}
1864
1865/**
1866 * @}
1867 */
1868
1869/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1870 * @{
1871 */
1872
1873/**
1874 * @brief Indicate whether VDD voltage is below the selected PVD threshold
1875 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
1876 * @retval State of bit (1 or 0).
1877 */
1878__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1879{
1880 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
1881}
1882
1883/**
1884 * @brief Indicate whether the voltage level is ready for current actual used VOS
1885 * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1886 * @retval State of bit (1 or 0).
1887 */
1888__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1889{
1890 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
1891}
1892
1893/**
1894 * @brief Indicate whether VDDA voltage is below the selected AVD threshold
1895 * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
1896 * @retval State of bit (1 or 0).
1897 */
1898__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
1899{
1900 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
1901}
1902
1903#if defined (PWR_CSR1_MMCVDO)
1904/**
1905 * @brief Indicate whether VDDMMC voltage is below 1V2
1906 * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO
1907 * @retval State of bit (1 or 0).
1908 */
1909__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
1910{
1911 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
1912}
1913#endif /* PWR_CSR1_MMCVDO */
1914
1915/**
1916 * @brief Get Backup Regulator ready Flag
1917 * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR
1918 * @retval State of bit (1 or 0).
1919 */
1920__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
1921{
1922 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
1923}
1924
1925/**
1926 * @brief Indicate whether the VBAT level is above or below low threshold
1927 * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL
1928 * @retval State of bit (1 or 0).
1929 */
1930__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1931{
1932 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
1933}
1934
1935/**
1936 * @brief Indicate whether the VBAT level is above or below high threshold
1937 * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH
1938 * @retval State of bit (1 or 0).
1939 */
1940__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1941{
1942 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
1943}
1944
1945/**
1946 * @brief Indicate whether the CPU temperature level is above or below low threshold
1947 * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
1948 * @retval State of bit (1 or 0).
1949 */
1950__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1951{
1952 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
1953}
1954
1955/**
1956 * @brief Indicate whether the CPU temperature level is above or below high threshold
1957 * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
1958 * @retval State of bit (1 or 0).
1959 */
1960__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1961{
1962 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
1963}
1964
1965#if defined (SMPS)
1966/**
1967 * @brief Indicate whether the SMPS external supply is ready or not
1968 * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT
1969 * @retval State of bit (1 or 0).
1970 */
1971__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
1972{
1973 return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
1974}
1975#endif /* SMPS */
1976
1977/**
1978 * @brief Indicate whether the USB supply is ready or not
1979 * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB
1980 * @retval State of bit (1 or 0).
1981 */
1982__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
1983{
1984 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
1985}
1986
1987#if defined (DUAL_CORE)
1988/**
1989 * @brief Get HOLD2 Flag
1990 * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2
1991 * @retval State of bit (1 or 0).
1992 */
1993__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
1994{
1995 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
1996}
1997
1998/**
1999 * @brief Get HOLD1 Flag
2000 * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1
2001 * @retval State of bit (1 or 0).
2002 */
2003__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
2004{
2005 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
2006}
2007#endif /* DUAL_CORE */
2008
2009/**
2010 * @brief Get CPU System Stop Flag
2011 * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP
2012 * @retval State of bit (1 or 0).
2013 */
2014__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
2015{
2016 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
2017}
2018
2019#if defined (DUAL_CORE)
2020/**
2021 * @brief Get CPU2 System Stop Flag
2022 * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP
2023 * @retval State of bit (1 or 0).
2024 */
2025__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
2026{
2027 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
2028}
2029#endif /* DUAL_CORE */
2030
2031/**
2032 * @brief Get CPU System Standby Flag
2033 * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB
2034 * @retval State of bit (1 or 0).
2035 */
2036__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
2037{
2038 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
2039}
2040
2041#if defined (DUAL_CORE)
2042/**
2043 * @brief Get CPU2 System Standby Flag
2044 * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB
2045 * @retval State of bit (1 or 0).
2046 */
2047__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
2048{
2049 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
2050}
2051#endif /* DUAL_CORE */
2052
2053#if defined (PWR_CPUCR_SBF_D1)
2054/**
2055 * @brief Get CPU D1 Domain Standby Flag
2056 * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1
2057 * @retval State of bit (1 or 0).
2058 */
2059__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
2060{
2061 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
2062}
2063#endif /* PWR_CPUCR_SBF_D1 */
2064
2065#if defined (DUAL_CORE)
2066/**
2067 * @brief Get CPU2 D1 Domain Standby Flag
2068 * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1
2069 * @retval State of bit (1 or 0).
2070 */
2071__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
2072{
2073 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
2074}
2075#endif /* DUAL_CORE */
2076
2077#if defined (PWR_CPUCR_SBF_D2)
2078/**
2079 * @brief Get CPU D2 Domain Standby Flag
2080 * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2
2081 * @retval State of bit (1 or 0).
2082 */
2083__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
2084{
2085 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
2086}
2087#endif /* PWR_CPUCR_SBF_D2 */
2088
2089#if defined (DUAL_CORE)
2090/**
2091 * @brief Get CPU2 D2 Domain Standby Flag
2092 * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2
2093 * @retval State of bit (1 or 0).
2094 */
2095__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
2096{
2097 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
2098}
2099#endif /* DUAL_CORE */
2100
2101
2102/**
2103 * @brief Indicate whether the Regulator is ready in the selected voltage range
2104 * or if its output voltage is still changing to the required voltage level
2105 * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS
2106 * @retval State of bit (1 or 0).
2107 */
2108__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2109{
2110#if defined (PWR_CPUCR_PDDS_D2)
2111 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
2112#else
2113 return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
2114#endif /* PWR_CPUCR_PDDS_D2 */
2115}
2116
2117/**
2118 * @brief Get Wake-up Flag 6
2119 * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
2120 * @retval State of bit (1 or 0).
2121 */
2122__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
2123{
2124 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
2125}
2126
2127#if defined (PWR_WKUPFR_WKUPF5)
2128/**
2129 * @brief Get Wake-up Flag 5
2130 * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
2131 * @retval State of bit (1 or 0).
2132 */
2133__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
2134{
2135 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
2136}
2137#endif /* defined (PWR_WKUPFR_WKUPF5) */
2138
2139/**
2140 * @brief Get Wake-up Flag 4
2141 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
2142 * @retval State of bit (1 or 0).
2143 */
2144__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
2145{
2146 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
2147}
2148
2149#if defined (PWR_WKUPFR_WKUPF3)
2150/**
2151 * @brief Get Wake-up Flag 3
2152 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
2153 * @retval State of bit (1 or 0).
2154 */
2155__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
2156{
2157 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
2158}
2159#endif /* defined (PWR_WKUPFR_WKUPF3) */
2160
2161/**
2162 * @brief Get Wake-up Flag 2
2163 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
2164 * @retval State of bit (1 or 0).
2165 */
2166__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
2167{
2168 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
2169}
2170
2171/**
2172 * @brief Get Wake-up Flag 1
2173 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
2174 * @retval State of bit (1 or 0).
2175 */
2176__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
2177{
2178 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
2179}
2180
2181/**
2182 * @brief Clear CPU STANDBY, STOP and HOLD flags
2183 * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU
2184 * @retval None
2185 */
2186__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
2187{
2188 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
2189}
2190
2191#if defined (DUAL_CORE)
2192/**
2193 * @brief Clear CPU2 STANDBY, STOP and HOLD flags
2194 * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2
2195 * @retval None
2196 */
2197__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
2198{
2199 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
2200}
2201#endif /* DUAL_CORE */
2202
2203/**
2204 * @brief Clear Wake-up Flag 6
2205 * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
2206 * @retval None
2207 */
2208__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
2209{
2210 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
2211}
2212
2213#if defined (PWR_WKUPCR_WKUPC5)
2214/**
2215 * @brief Clear Wake-up Flag 5
2216 * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
2217 * @retval None
2218 */
2219__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
2220{
2221 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
2222}
2223#endif /* defined (PWR_WKUPCR_WKUPC5) */
2224
2225/**
2226 * @brief Clear Wake-up Flag 4
2227 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
2228 * @retval None
2229 */
2230__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
2231{
2232 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
2233}
2234
2235#if defined (PWR_WKUPCR_WKUPC3)
2236/**
2237 * @brief Clear Wake-up Flag 3
2238 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
2239 * @retval None
2240 */
2241__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
2242{
2243 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
2244}
2245#endif /* defined (PWR_WKUPCR_WKUPC3) */
2246
2247/**
2248 * @brief Clear Wake-up Flag 2
2249 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
2250 * @retval None
2251 */
2252__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
2253{
2254 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
2255}
2256
2257/**
2258 * @brief Clear Wake-up Flag 1
2259 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
2260 * @retval None
2261 */
2262__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
2263{
2264 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
2265}
2266
2267#if defined (USE_FULL_LL_DRIVER)
2268/** @defgroup PWR_LL_EF_Init De-initialization function
2269 * @{
2270 */
2271ErrorStatus LL_PWR_DeInit(void);
2272/**
2273 * @}
2274 */
2275#endif /* defined (USE_FULL_LL_DRIVER) */
2276
2277
2278/**
2279 * @}
2280 */
2281
2282/**
2283 * @}
2284 */
2285
2286/**
2287 * @}
2288 */
2289
2290#endif /* defined (PWR) */
2291
2292/**
2293 * @}
2294 */
2295
2296#ifdef __cplusplus
2297}
2298#endif
2299
2300#endif /* STM32H7xx_LL_PWR_H */
2301
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
POSITION_VAL
#define POSITION_VAL(VAL)
Definition stm32h7xx.h:221
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
ErrorStatus
ErrorStatus
Definition stm32h7xx.h:194
PWR_CSR1_AVDO
#define PWR_CSR1_AVDO
Analog Voltage Detect Output.
Definition stm32h723xx.h:14261
PWR_CR1_DBP
#define PWR_CR1_DBP
Disable Back-up domain Protection.
Definition stm32h723xx.h:14208
PWR_WKUPFR_WKUPF4
#define PWR_WKUPFR_WKUPF4
Wakeup Pin Flag 4.
Definition stm32h723xx.h:14383
PWR_CPUCR_SBF_D1
#define PWR_CPUCR_SBF_D1
D1 domain DSTANDBY Flag.
Definition stm32h723xx.h:14335
PWR_CR2_TEMPL
#define PWR_CR2_TEMPL
Monitored temperature level above low threshold.
Definition stm32h723xx.h:14280
PWR_CR3_BYPASS
#define PWR_CR3_BYPASS
Power Management Unit bypass.
Definition stm32h723xx.h:14321
PWR_CPUCR_PDDS_D2
#define PWR_CPUCR_PDDS_D2
D2 domain Power Down Deepsleep.
Definition stm32h723xx.h:14347
PWR_CR3_VBRS
#define PWR_CR3_VBRS
VBAT charging resistor selection.
Definition stm32h723xx.h:14309
PWR_WKUPCR_WKUPC4
#define PWR_WKUPCR_WKUPC4
Clear Wakeup Pin Flag 4.
Definition stm32h723xx.h:14369
PWR_CR1_FLPS
#define PWR_CR1_FLPS
Flash low power mode in DSTOP.
Definition stm32h723xx.h:14205
PWR_CR1_SVOS
#define PWR_CR1_SVOS
System STOP mode Voltage Scaling selection.
Definition stm32h723xx.h:14200
PWR_CR3_LDOEN
#define PWR_CR3_LDOEN
Low Drop Output regulator enable.
Definition stm32h723xx.h:14318
PWR_WKUPEPR_WKUPP1_Pos
#define PWR_WKUPEPR_WKUPP1_Pos
Definition stm32h723xx.h:14421
PWR_CR2_VBATL
#define PWR_CR2_VBATL
Monitored VBAT level above low threshold.
Definition stm32h723xx.h:14286
PWR_WKUPEPR_WKUPPUPD1
#define PWR_WKUPEPR_WKUPPUPD1
Wakeup Pin pull configuration for WKUP1.
Definition stm32h723xx.h:14409
PWR_CPUCR_STOPF
#define PWR_CPUCR_STOPF
STOP Flag.
Definition stm32h723xx.h:14341
PWR_CR3_USB33DEN
#define PWR_CR3_USB33DEN
VDD33_USB voltage level detector enable.
Definition stm32h723xx.h:14306
PWR_D3CR_VOSRDY
#define PWR_D3CR_VOSRDY
VOS Ready bit for VDD11 Voltage Scaling output selection.
Definition stm32h723xx.h:14361
PWR_CPUCR_PDDS_D1
#define PWR_CPUCR_PDDS_D1
D1 domain Power Down Deepsleep selection.
Definition stm32h723xx.h:14350
PWR_CPUCR_SBF
#define PWR_CPUCR_SBF
System STANDBY Flag.
Definition stm32h723xx.h:14338
PWR_CR1_ALS
#define PWR_CR1_ALS
Analog Voltage Detector level selection.
Definition stm32h723xx.h:14192
PWR_D3CR_VOS
#define PWR_D3CR_VOS
Voltage Scaling selection according performance.
Definition stm32h723xx.h:14356
PWR_WKUPEPR_WKUPPUPD1_Pos
#define PWR_WKUPEPR_WKUPPUPD1_Pos
Definition stm32h723xx.h:14407
PWR_CR3_USB33RDY
#define PWR_CR3_USB33RDY
USB supply ready.
Definition stm32h723xx.h:14300
PWR_CSR1_ACTVOSRDY
#define PWR_CSR1_ACTVOSRDY
Ready bit for current actual used VOS for VDD11 Voltage Scaling.
Definition stm32h723xx.h:14269
PWR_WKUPFR_WKUPF2
#define PWR_WKUPFR_WKUPF2
Wakeup Pin Flag 2.
Definition stm32h723xx.h:14386
PWR_CR2_MONEN
#define PWR_CR2_MONEN
VBAT and temperature monitoring enable.
Definition stm32h723xx.h:14292
PWR_CPUCR_PDDS_D3
#define PWR_CPUCR_PDDS_D3
System D3 domain Power Down Deepsleep.
Definition stm32h723xx.h:14344
PWR_CR2_BREN
#define PWR_CR2_BREN
Backup regulator enable.
Definition stm32h723xx.h:14295
PWR_CPUCR_CSSF
#define PWR_CPUCR_CSSF
Clear D1 domain CPU1 STANDBY, STOP and HOLD flags.
Definition stm32h723xx.h:14329
PWR_CR3_VBE
#define PWR_CR3_VBE
VBAT charging enable.
Definition stm32h723xx.h:14312
PWR_CR2_VBATH
#define PWR_CR2_VBATH
Monitored VBAT level above high threshold.
Definition stm32h723xx.h:14283
PWR_WKUPCR_WKUPC1
#define PWR_WKUPCR_WKUPC1
Clear Wakeup Pin Flag 1.
Definition stm32h723xx.h:14375
PWR_CR2_TEMPH
#define PWR_CR2_TEMPH
Monitored temperature level above high threshold.
Definition stm32h723xx.h:14277
PWR_CPUCR_RUN_D3
#define PWR_CPUCR_RUN_D3
Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes.
Definition stm32h723xx.h:14326
PWR_CR1_PVDEN
#define PWR_CR1_PVDEN
Programmable Voltage detector enable.
Definition stm32h723xx.h:14217
PWR_CR1_LPDS
#define PWR_CR1_LPDS
Low Power Deepsleep with SVOS3.
Definition stm32h723xx.h:14220
PWR_CPUCR_SBF_D2
#define PWR_CPUCR_SBF_D2
D2 domain DSTANDBY Flag.
Definition stm32h723xx.h:14332
PWR_WKUPFR_WKUPF1
#define PWR_WKUPFR_WKUPF1
Wakeup Pin Flag 1.
Definition stm32h723xx.h:14389
PWR_CR3_USBREGEN
#define PWR_CR3_USBREGEN
USB regulator enable.
Definition stm32h723xx.h:14303
PWR_WKUPCR_WKUPC2
#define PWR_WKUPCR_WKUPC2
Clear Wakeup Pin Flag 2.
Definition stm32h723xx.h:14372
PWR_WKUPCR_WKUPC6
#define PWR_WKUPCR_WKUPC6
Clear Wakeup Pin Flag 6.
Definition stm32h723xx.h:14366
PWR_CR2_BRRDY
#define PWR_CR2_BRRDY
Backup regulator ready.
Definition stm32h723xx.h:14289
PWR_CR1_AVDEN
#define PWR_CR1_AVDEN
Analog Voltage Detector Enable.
Definition stm32h723xx.h:14197
PWR_CSR1_PVDO
#define PWR_CSR1_PVDO
Programmable Voltage Detect Output.
Definition stm32h723xx.h:14272
PWR_CR3_SCUEN
#define PWR_CR3_SCUEN
Supply configuration update enable.
Definition stm32h723xx.h:14315
PWR_CR1_PLS
#define PWR_CR1_PLS
Programmable Voltage Detector level selection.
Definition stm32h723xx.h:14211
PWR_WKUPFR_WKUPF6
#define PWR_WKUPFR_WKUPF6
Wakeup Pin Flag 6.
Definition stm32h723xx.h:14380
PWR
#define PWR
Definition stm32h723xx.h:2457
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.