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stm32h7xx_ll_system.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2017 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33/* Define to prevent recursive inclusion -------------------------------------*/
34#ifndef __STM32H7xx_LL_SYSTEM_H
35#define __STM32H7xx_LL_SYSTEM_H
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41/* Includes ------------------------------------------------------------------*/
42#include "stm32h7xx.h"
43
44/** @addtogroup STM32H7xx_LL_Driver
45 * @{
46 */
47
48#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
50/** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54/* Private types -------------------------------------------------------------*/
55/* Private variables ---------------------------------------------------------*/
56
57/* Private constants ---------------------------------------------------------*/
58/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
62 * @{
63 */
64#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
65#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
66#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
67#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
68#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
69#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
70#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
71#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
72/**
73 * @}
74 */
75
76/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
77 * @{
78 */
79#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
80#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
81#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
82#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
83#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
84#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
85#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
86#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
87/**
88 * @}
89 */
90/**
91 * @}
92 */
93
94/* Private macros ------------------------------------------------------------*/
95
96/* Exported types ------------------------------------------------------------*/
97/* Exported constants --------------------------------------------------------*/
98/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
99 * @{
100 */
101
102/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
103 * @{
104 */
105#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
106#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
107#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
108#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
109#if defined(I2C5)
110#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */
111#endif /*I2C5*/
112#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
113#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
114#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
115#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
116/**
117 * @}
118 */
119
120/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
121* @{
122*/
123#if defined(SYSCFG_PMCR_BOOSTEN)
124#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */
125#endif /*SYSCFG_PMCR_BOOSTEN*/
126#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */
127#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */
128#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */
129#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */
130/**
131 * @}
132 */
133
134#if defined(SYSCFG_PMCR_EPIS_SEL)
135/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
136* @{
137*/
138#define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */
139#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */
140/**
141 * @}
142 */
143#endif /* SYSCFG_PMCR_EPIS_SEL */
144
145/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
146 * @{
147 */
148#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
149#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
150#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
151#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
152#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
153#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
154#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
155#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
156#if defined(GPIOI)
157#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
158#endif /*GPIOI*/
159#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
160#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
161/**
162 * @}
163 */
164
165/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
166 * @{
167 */
168#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
169#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
170#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
171#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
172#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
173#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
174#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
175#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
176#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
177#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
178#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
179#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
180#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
181#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
182#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
183#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
184/**
185 * @}
186 */
187
188/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
189 * @{
190 */
191#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
192 with Break Input of TIM1/8/15/16/17 and HRTIM */
193
194#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal
195 with Break Input of TIM1/8/15/16/17 and HRTIM */
196
197#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal
198 with Break Input of TIM1/8/15/16/17 and HRTIM */
199
200#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal
201 with Break Input of TIM1/8/15/16/17 and HRTIM */
202
203#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal
204 with Break Input of TIM1/8/15/16/17 and HRTIM */
205
206#if defined(SYSCFG_CFGR_SRAM3L)
207#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal
208 with Break Input of TIM1/8/15/16/17 and HRTIM */
209#endif /*SYSCFG_CFGR_SRAM3L*/
210
211#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal
212 with Break Input of TIM1/8/15/16/17 and HRTIM */
213
214#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal
215 with Break Input of TIM1/8/15/16/17 and HRTIM */
216
217#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal
218 with Break Input of TIM1/8/15/16/17 and HRTIM */
219
220#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal
221 with Break Input of TIM1/8/15/16/17 and HRTIM */
222
223#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection
224 with TIM1/8/15/16/17 and HRTIM Break Input
225 and also the PVDE and PLS bits of the Power Control Interface */
226#if defined(DUAL_CORE)
227#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal
228 with Break Input of TIM1/8/15/16/17 and HRTIM */
229#endif /* DUAL_CORE */
230/**
231 * @}
232 */
233
234/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
235 * @{
236 */
237#define LL_SYSCFG_CELL_CODE 0U
238#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
239/**
240 * @}
241 */
242
243/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
244 * @{
245 */
246#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
247#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
248/**
249 * @}
250 */
251
252#if defined (DUAL_CORE)
253/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
254 * @{
255 */
256#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
257#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M
258/**
259 * @}
260 */
261#endif /* DUAL_CORE */
262
263/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
264 * @{
265 */
266#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
267#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
268#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
269#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
270/**
271 * @}
272 */
273#ifdef SYSCFG_UR17_TCM_AXI_CFG
274/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
275 * @{
276 */
277#define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U
278#define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U
279#define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U
280#define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U
281/**
282 * @}
283 */
284#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
285#if defined(SYSCFG_PKGR_PKG)
286/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
287 * @{
288 */
289#if (STM32H7_DEV_ID == 0x450UL)
290#if defined(STM32H742xx) || defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H753xx)
291#define LL_SYSCFG_LQFP100_PACKAGE 0U
292#define LL_SYSCFG_TQFP144_PACKAGE 2U
293#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
294#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
295#else
296#define LL_SYSCFG_UFBGA169_LQFP176_PACKAGE 2U
297#define LL_SYSCFG_LQFP144_PACKAGE 3U
298#define LL_SYSCFG_LQFP176_PACKAGE 6U
299#define LL_SYSCFG_UFBGA176_PACKAGE 7U
300#define LL_SYSCFG_LQFP208_STM32H7x7_PACKAGE 9U
301#define LL_SYSCFG_LQFP208_STM32H7x5_PACKAGE 10U
302#endif
303#elif (STM32H7_DEV_ID == 0x483UL)
304#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U
305#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U
306#define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U
307#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U
308#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U
309#define LL_SYSCFG_LQFP144_PACKAGE 5U
310#define LL_SYSCFG_UFBGA144_PACKAGE 6U
311#define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U
312#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U
313#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
314#define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U
315#endif /* STM32H7_DEV_ID == 0x450UL */
316/**
317 * @}
318 */
319#endif /* SYSCFG_PKGR_PKG */
320
321/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
322 * @{
323 */
324#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
325#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
326#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
327#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
328
329/**
330 * @}
331 */
332
333/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
334 * @{
335 */
336#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
337#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
338#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
339#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
340#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
341/**
342 * @}
343 */
344
345/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
346 * @{
347 */
348#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */
349#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */
350#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */
351#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */
352#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */
353#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */
354#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */
355#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */
356#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */
357#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */
358#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
359#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
360#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
361#if defined(I2C5)
362#define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
363#endif /*I2C5*/
364/**
365 * @}
366 */
367
368
369/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
370 * @{
371 */
372#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
373#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */
374#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
375#if defined(TIM23)
376#define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */
377#endif /*TIM23*/
378#if defined(TIM24)
379#define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */
380#endif /*TIM24*/
381/**
382 * @}
383 */
384
385/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
386 * @{
387 */
388#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */
389#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */
390#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */
391#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */
392#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */
393#if defined(HRTIM1)
394#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */
395#endif /*HRTIM1*/
396/**
397 * @}
398 */
399
400/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
401 * @{
402 */
403#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */
404/**
405 * @}
406 */
407
408/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
409 * @{
410 */
411#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */
412#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */
413#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */
414#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */
415#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */
416#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */
417#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */
418/**
419 * @}
420 */
421
422/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
423 * @{
424 */
425#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
426#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
427#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
428#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
429#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
430#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
431#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
432#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
433/**
434 * @}
435 */
436
437/**
438 * @}
439 */
440
441/* Exported macro ------------------------------------------------------------*/
442
443/* Exported functions --------------------------------------------------------*/
444/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
445 * @{
446 */
447
448/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
449 * @{
450 */
451
452#if defined(SYSCFG_PMCR_EPIS_SEL)
453/**
454 * @brief Select Ethernet PHY interface
455 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface
456 * @param Interface This parameter can be one of the following values:
457 * @arg @ref LL_SYSCFG_ETH_MII
458 * @arg @ref LL_SYSCFG_ETH_RMII
459 * @retval None
460 */
461__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
462{
463 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
464}
465
466/**
467 * @brief Get Ethernet PHY interface
468 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface
469 * @retval Returned value can be one of the following values:
470 * @arg @ref LL_SYSCFG_ETH_MII
471 * @arg @ref LL_SYSCFG_ETH_RMII
472 */
473__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
474{
475 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
476}
477
478#endif /* SYSCFG_PMCR_EPIS_SEL */
479/**
480 * @brief Open an Analog Switch
481 * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch
482 * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch
483 * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch
484 * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch
485 * @param AnalogSwitch This parameter can be one of the following values:
486 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
487 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
488 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
489 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
490 * @retval None
491 */
492__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
493{
494 SET_BIT(SYSCFG->PMCR, AnalogSwitch);
495}
496
497/**
498 * @brief Close an Analog Switch
499 * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch
500 * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch
501 * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch
502 * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch
503 * @param AnalogSwitch This parameter can be one of the following values:
504 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
505 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
506 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
507 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
508 * @retval None
509 */
510__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
511{
512 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
513}
514#ifdef SYSCFG_PMCR_BOOSTEN
515/**
516 * @brief Enable the Analog booster to reduce the total harmonic distortion
517 * of the analog switch when the supply voltage is lower than 2.7 V
518 * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster
519 * @note Activating the booster allows to guaranty the analog switch AC performance
520 * when the supply voltage is below 2.7 V: in this case, the analog switch
521 * performance is the same on the full voltage range
522 * @retval None
523 */
524__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
525{
526 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
527}
528
529/**
530 * @brief Disable the Analog booster
531 * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster
532 * @note Activating the booster allows to guaranty the analog switch AC performance
533 * when the supply voltage is below 2.7 V: in this case, the analog switch
534 * performance is the same on the full voltage range
535 * @retval None
536 */
537__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
538{
539 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
540}
541#endif /*SYSCFG_PMCR_BOOSTEN*/
542/**
543 * @brief Enable the I2C fast mode plus driving capability.
544 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
545 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus
546 * @param ConfigFastModePlus This parameter can be a combination of the following values:
547 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
548 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
549 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
550 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
551 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
552 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
553 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
554 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
555 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
556 *
557 * (*) value not defined in all devices
558 * @retval None
559 */
560__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
561{
562 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
563}
564
565/**
566 * @brief Disable the I2C fast mode plus driving capability.
567 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
568 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus
569 * @param ConfigFastModePlus This parameter can be a combination of the following values:
570 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
571 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
572 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
573 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
574 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
575 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
576 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
577 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
578 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
579 *
580 * (*) value not defined in all devices
581 * @retval None
582 */
583__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
584{
585 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
586}
587
588/**
589 * @brief Configure source input for the EXTI external interrupt.
590 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
591 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
592 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
593 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
594 * @param Port This parameter can be one of the following values:
595 * @arg @ref LL_SYSCFG_EXTI_PORTA
596 * @arg @ref LL_SYSCFG_EXTI_PORTB
597 * @arg @ref LL_SYSCFG_EXTI_PORTC
598 * @arg @ref LL_SYSCFG_EXTI_PORTD
599 * @arg @ref LL_SYSCFG_EXTI_PORTE
600 * @arg @ref LL_SYSCFG_EXTI_PORTF
601 * @arg @ref LL_SYSCFG_EXTI_PORTG
602 * @arg @ref LL_SYSCFG_EXTI_PORTH
603 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
604 * @arg @ref LL_SYSCFG_EXTI_PORTJ
605 * @arg @ref LL_SYSCFG_EXTI_PORTK
606 *
607 * (*) value not defined in all devices
608 * @param Line This parameter can be one of the following values:
609 * @arg @ref LL_SYSCFG_EXTI_LINE0
610 * @arg @ref LL_SYSCFG_EXTI_LINE1
611 * @arg @ref LL_SYSCFG_EXTI_LINE2
612 * @arg @ref LL_SYSCFG_EXTI_LINE3
613 * @arg @ref LL_SYSCFG_EXTI_LINE4
614 * @arg @ref LL_SYSCFG_EXTI_LINE5
615 * @arg @ref LL_SYSCFG_EXTI_LINE6
616 * @arg @ref LL_SYSCFG_EXTI_LINE7
617 * @arg @ref LL_SYSCFG_EXTI_LINE8
618 * @arg @ref LL_SYSCFG_EXTI_LINE9
619 * @arg @ref LL_SYSCFG_EXTI_LINE10
620 * @arg @ref LL_SYSCFG_EXTI_LINE11
621 * @arg @ref LL_SYSCFG_EXTI_LINE12
622 * @arg @ref LL_SYSCFG_EXTI_LINE13
623 * @arg @ref LL_SYSCFG_EXTI_LINE14
624 * @arg @ref LL_SYSCFG_EXTI_LINE15
625 * @retval None
626 */
627__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
628{
629 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
630}
631
632/**
633 * @brief Get the configured defined for specific EXTI Line
634 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
635 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
636 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
637 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
638 * @param Line This parameter can be one of the following values:
639 * @arg @ref LL_SYSCFG_EXTI_LINE0
640 * @arg @ref LL_SYSCFG_EXTI_LINE1
641 * @arg @ref LL_SYSCFG_EXTI_LINE2
642 * @arg @ref LL_SYSCFG_EXTI_LINE3
643 * @arg @ref LL_SYSCFG_EXTI_LINE4
644 * @arg @ref LL_SYSCFG_EXTI_LINE5
645 * @arg @ref LL_SYSCFG_EXTI_LINE6
646 * @arg @ref LL_SYSCFG_EXTI_LINE7
647 * @arg @ref LL_SYSCFG_EXTI_LINE8
648 * @arg @ref LL_SYSCFG_EXTI_LINE9
649 * @arg @ref LL_SYSCFG_EXTI_LINE10
650 * @arg @ref LL_SYSCFG_EXTI_LINE11
651 * @arg @ref LL_SYSCFG_EXTI_LINE12
652 * @arg @ref LL_SYSCFG_EXTI_LINE13
653 * @arg @ref LL_SYSCFG_EXTI_LINE14
654 * @arg @ref LL_SYSCFG_EXTI_LINE15
655 * @retval Returned value can be one of the following values:
656 * @arg @ref LL_SYSCFG_EXTI_PORTA
657 * @arg @ref LL_SYSCFG_EXTI_PORTB
658 * @arg @ref LL_SYSCFG_EXTI_PORTC
659 * @arg @ref LL_SYSCFG_EXTI_PORTD
660 * @arg @ref LL_SYSCFG_EXTI_PORTE
661 * @arg @ref LL_SYSCFG_EXTI_PORTF
662 * @arg @ref LL_SYSCFG_EXTI_PORTG
663 * @arg @ref LL_SYSCFG_EXTI_PORTH
664 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
665 * @arg @ref LL_SYSCFG_EXTI_PORTJ
666 * @arg @ref LL_SYSCFG_EXTI_PORTK
667 * (*) value not defined in all devices
668 */
669__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
670{
671 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
672}
673
674/**
675 * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
676 * @note this feature is available on STM32H7 rev.B and above
677 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n
678 * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n
679 * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n
680 * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n
681 * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n
682 * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n
683 * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n
684 * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n
685 * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n
686 * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n
687 * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n
688 * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs
689 * @param Break This parameter can be a combination of the following values:
690 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
691 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
692 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
693 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
694 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
695 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
696 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
697 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
698 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
699 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
700 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
701 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
702 * @retval None
703 * (*) value not defined in all devices
704 */
705__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
706{
707#if defined(DUAL_CORE)
708 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
709 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
710 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
711#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
712 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
713 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
714 SYSCFG_CFGR_PVDL, Break);
715#elif defined(SYSCFG_CFGR_AXISRAML)
716 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
717 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
718 Break);
719#else
720 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
721 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
722 SYSCFG_CFGR_PVDL, Break);
723#endif /* DUAL_CORE */
724}
725
726/**
727 * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
728 * @note this feature is available on STM32H7 rev.B and above
729 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n
730 * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n
731 * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n
732 * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n
733 * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n
734 * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n
735 * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n
736 * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n
737 * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n
738 * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n
739 * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n
740 * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs
741 * @retval Returned value can be can be a combination of the following values:
742 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
743 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
744 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
745 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
746 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
747 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
748 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
749 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
750 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
751 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
752 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
753 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
754 * (*) value not defined in all devices
755 */
756__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
757{
758#if defined(DUAL_CORE)
759 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
760 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
761 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
762 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
763#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
764 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
765 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
766 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
767 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
768#elif defined (SYSCFG_CFGR_AXISRAML)
769 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
770 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
771 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
772 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
773#else
774 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
775 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
776#endif /* DUAL_CORE */
777}
778
779/**
780 * @brief Enable the Compensation Cell
781 * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell
782 * @note The I/O compensation cell can be used only when the device supply
783 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
784 * @retval None
785 */
786__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
787{
788 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
789}
790
791/**
792 * @brief Disable the Compensation Cell
793 * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell
794 * @note The I/O compensation cell can be used only when the device supply
795 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
796 * @retval None
797 */
798__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
799{
800 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
801}
802
803/**
804 * @brief Check if the Compensation Cell is enabled
805 * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell
806 * @retval State of bit (1 or 0).
807 */
808__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
809{
810 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
811}
812
813/**
814 * @brief Get Compensation Cell ready Flag
815 * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR
816 * @retval State of bit (1 or 0).
817 */
818__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
819{
820 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
821}
822
823/**
824 * @brief Enable the I/O speed optimization when the product voltage is low.
825 * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize
826 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
827 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
828 * might be destructive.
829 * @retval None
830 */
831__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
832{
833#if defined(SYSCFG_CCCSR_HSLV)
834 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
835#else
836 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
837#endif /* SYSCFG_CCCSR_HSLV */
838}
839
840#if defined(SYSCFG_CCCSR_HSLV1)
841/**
842 * @brief Enable the I/O speed optimization when the product voltage is low.
843 * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize
844 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
845 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
846 * might be destructive.
847 * @retval None
848 */
849__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
850{
851 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
852}
853
854/**
855 * @brief Enable the I/O speed optimization when the product voltage is low.
856 * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize
857 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
858 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
859 * might be destructive.
860 * @retval None
861 */
862__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
863{
864 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
865}
866
867/**
868 * @brief Enable the I/O speed optimization when the product voltage is low.
869 * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize
870 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
871 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
872 * might be destructive.
873 * @retval None
874 */
875__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
876{
877 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
878}
879#endif /*SYSCFG_CCCSR_HSLV1*/
880
881
882/**
883 * @brief To Disable optimize the I/O speed when the product voltage is low.
884 * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize
885 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
886 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
887 * might be destructive.
888 * @retval None
889 */
890__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
891{
892#if defined(SYSCFG_CCCSR_HSLV)
893 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
894#else
895 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
896#endif /* SYSCFG_CCCSR_HSLV */
897}
898
899#if defined(SYSCFG_CCCSR_HSLV1)
900/**
901 * @brief To Disable optimize the I/O speed when the product voltage is low.
902 * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize
903 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
904 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
905 * might be destructive.
906 * @retval None
907 */
908__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
909{
910 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
911}
912
913/**
914 * @brief To Disable optimize the I/O speed when the product voltage is low.
915 * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize
916 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
917 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
918 * might be destructive.
919 * @retval None
920 */
921__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
922{
923 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
924}
925
926/**
927 * @brief To Disable optimize the I/O speed when the product voltage is low.
928 * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize
929 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
930 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
931 * might be destructive.
932 * @retval None
933 */
934__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
935{
936 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
937}
938#endif /*SYSCFG_CCCSR_HSLV1*/
939
940/**
941 * @brief Check if the I/O speed optimization is enabled
942 * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization
943 * @retval State of bit (1 or 0).
944 */
945__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
946{
947#if defined(SYSCFG_CCCSR_HSLV)
948 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
949#else
950 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
951#endif /*SYSCFG_CCCSR_HSLV*/
952}
953
954#if defined(SYSCFG_CCCSR_HSLV1)
955/**
956 * @brief Check if the I/O speed optimization is enabled
957 * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization
958 * @retval State of bit (1 or 0).
959 */
960__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
961{
962 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
963}
964
965/**
966 * @brief Check if the I/O speed optimization is enabled
967 * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization
968 * @retval State of bit (1 or 0).
969 */
970__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
971{
972 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
973}
974
975/**
976 * @brief Check if the I/O speed optimization is enabled
977 * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization
978 * @retval State of bit (1 or 0).
979 */
980__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
981{
982 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
983}
984#endif /*SYSCFG_CCCSR_HSLV1*/
985
986/**
987 * @brief Set the code selection for the I/O Compensation cell
988 * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode
989 * @param CompCode: Selects the code to be applied for the I/O compensation cell
990 * This parameter can be one of the following values:
991 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
992 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
993 * @retval None
994 */
995__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
996{
997 SET_BIT(SYSCFG->CCCSR, CompCode);
998}
999
1000/**
1001 * @brief Get the code selected for the I/O Compensation cell
1002 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
1003 * @retval Returned value can be one of the following values:
1004 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1005 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1006 */
1007__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
1008{
1009 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
1010}
1011
1012#ifdef SYSCFG_CCCSR_CS_MMC
1013
1014/**
1015 * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail
1016 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
1017 * @retval Returned value can be one of the following values:
1018 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1019 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1020 */
1021__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
1022{
1023 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
1024}
1025#endif /*SYSCFG_CCCSR_CS_MMC*/
1026
1027/**
1028 * @brief Get I/O compensation cell value for PMOS transistors
1029 * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue
1030 * @retval Returned value is the I/O compensation cell value for PMOS transistors
1031 */
1032__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
1033{
1034 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
1035}
1036
1037/**
1038 * @brief Get I/O compensation cell value for NMOS transistors
1039 * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue
1040 * @retval Returned value is the I/O compensation cell value for NMOS transistors
1041 */
1042__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
1043{
1044 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
1045}
1046
1047/**
1048 * @brief Set I/O compensation cell code for PMOS transistors
1049 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1050 * @param PMOSCode PMOS compensation code
1051 * This code is applied to the I/O compensation cell when the CS bit of the
1052 * SYSCFG_CMPCR is set
1053 * @retval None
1054 */
1055__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
1056{
1057 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
1058}
1059
1060/**
1061 * @brief Get I/O compensation cell code for PMOS transistors
1062 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1063 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1064 */
1065__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
1066{
1067 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
1068}
1069
1070#ifdef SYSCFG_CCCR_PCC_MMC
1071
1072/**
1073 * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1074 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1075 * @param PMOSCode PMOS compensation code
1076 * This code is applied to the I/O compensation cell when the CS bit of the
1077 * SYSCFG_CMPCR is set
1078 * @retval None
1079 */
1080__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
1081{
1082 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
1083}
1084
1085/**
1086 * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1087 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1088 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1089 */
1090__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
1091{
1092 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
1093}
1094#endif /* SYSCFG_CCCR_PCC_MMC */
1095
1096/**
1097 * @brief Set I/O compensation cell code for NMOS transistors
1098 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1099 * @param NMOSCode NMOS compensation code
1100 * This code is applied to the I/O compensation cell when the CS bit of the
1101 * SYSCFG_CMPCR is set
1102 * @retval None
1103 */
1104__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
1105{
1106 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
1107}
1108
1109/**
1110 * @brief Get I/O compensation cell code for NMOS transistors
1111 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1112 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1113 */
1114__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
1115{
1116 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
1117}
1118
1119#ifdef SYSCFG_CCCR_NCC_MMC
1120
1121/**
1122 * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1123 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1124 * @param NMOSCode: NMOS compensation code
1125 * This code is applied to the I/O compensation cell when the CS bit of the
1126 * SYSCFG_CMPCR is set
1127 * @retval None
1128 */
1129__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
1130{
1131 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
1132}
1133
1134/**
1135 * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1136 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1137 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1138 */
1139__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
1140{
1141 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
1142}
1143#endif /*SYSCFG_CCCR_NCC_MMC*/
1144
1145#ifdef SYSCFG_PKGR_PKG
1146/**
1147 * @brief Get the device package
1148 * @rmtoll PKGR PKG LL_SYSCFG_GetPackage
1149 * @retval Returned value can be one of the following values:
1150 * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*)
1151 * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*)
1152 * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*)
1153 * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*)
1154 * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*)
1155 * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*)
1156 * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**)
1157 * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**)
1158 * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**)
1159 * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**)
1160 * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**)
1161 * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**)
1162 * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**)
1163 * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**)
1164 * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**)
1165 *
1166 * (*) : For stm32h74xxx and stm32h75xxx family lines.
1167 * (**): For stm32h72xxx and stm32h73xxx family lines.
1168 */
1169__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
1170{
1171 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
1172}
1173#endif /*SYSCFG_PKGR_PKG*/
1174
1175#ifdef SYSCFG_UR0_RDP
1176/**
1177 * @brief Get the Flash memory protection level
1178 * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel
1179 * @retval Returned value can be one of the following values:
1180 * 0xAA : RDP level 0
1181 * 0xCC : RDP level 2
1182 * Any other value : RDP level 1
1183 */
1184__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
1185{
1186 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
1187}
1188#ifdef SYSCFG_UR0_BKS
1189/**
1190 * @brief Indicate if the Flash memory bank addresses are inverted or not
1191 * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped
1192 * @retval State of bit (1 or 0).
1193 */
1194__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
1195{
1196 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
1197}
1198#endif /*SYSCFG_UR0_BKS*/
1199
1200/**
1201 * @brief Get the BOR Threshold Reset Level
1202 * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel
1203 * @retval Returned value can be one of the following values:
1204 * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
1205 * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
1206 * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
1207 * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
1208 */
1209__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
1210{
1211 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
1212}
1213/**
1214 * @brief BootCM7 address 0 configuration
1215 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0
1216 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
1217 * @retval None
1218 */
1219__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
1220{
1221 /* Configure CM7 BOOT ADD0 */
1222#if defined(DUAL_CORE)
1223 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
1224#else
1225 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
1226#endif /*DUAL_CORE*/
1227
1228}
1229
1230/**
1231 * @brief Get BootCM7 address 0
1232 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0
1233 * @retval Returned the CM7 Boot Address0
1234 */
1235__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
1236{
1237 /* Get CM7 BOOT ADD0 */
1238#if defined(DUAL_CORE)
1239 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
1240#else
1241 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
1242#endif /*DUAL_CORE*/
1243}
1244
1245/**
1246 * @brief BootCM7 address 1 configuration
1247 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1
1248 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
1249 * @retval None
1250 */
1251__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
1252{
1253 /* Configure CM7 BOOT ADD1 */
1254#if defined(DUAL_CORE)
1255 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
1256#else
1257 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
1258#endif /*DUAL_CORE*/
1259}
1260
1261/**
1262 * @brief Get BootCM7 address 1
1263 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1
1264 * @retval Returned the CM7 Boot Address0
1265 */
1266__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
1267{
1268 /* Get CM7 BOOT ADD0 */
1269#if defined(DUAL_CORE)
1270 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
1271#else
1272 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
1273#endif /* DUAL_CORE */
1274}
1275
1276#if defined(DUAL_CORE)
1277/**
1278 * @brief BootCM4 address 0 configuration
1279 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0
1280 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
1281 * @retval None
1282 */
1283__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
1284{
1285 /* Configure CM4 BOOT ADD0 */
1286 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
1287}
1288
1289/**
1290 * @brief Get BootCM4 address 0
1291 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0
1292 * @retval Returned the CM4 Boot Address0
1293 */
1294__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
1295{
1296 /* Get CM4 BOOT ADD0 */
1297 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
1298}
1299
1300/**
1301 * @brief BootCM4 address 1 configuration
1302 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1
1303 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
1304 * @retval None
1305 */
1306__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
1307{
1308 /* Configure CM4 BOOT ADD1 */
1309 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
1310}
1311
1312/**
1313 * @brief Get BootCM4 address 1
1314 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1
1315 * @retval Returned the CM4 Boot Address0
1316 */
1317__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
1318{
1319 /* Get CM4 BOOT ADD0 */
1320 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
1321}
1322#endif /*DUAL_CORE*/
1323
1324/**
1325 * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase
1326 * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable
1327 * @retval State of bit (1 or 0).
1328 */
1329__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
1330{
1331 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
1332}
1333
1334/**
1335 * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase
1336 * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable
1337 * @retval State of bit (1 or 0).
1338 */
1339__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
1340{
1341 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
1342}
1343
1344/**
1345 * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected
1346 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected
1347 * @retval State of bit (1 or 0).
1348 */
1349__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
1350{
1351 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1352}
1353
1354/**
1355 * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected
1356 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected
1357 * @retval State of bit (1 or 0).
1358 */
1359__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
1360{
1361 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1362}
1363
1364/**
1365 * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected
1366 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected
1367 * @retval State of bit (1 or 0).
1368 */
1369__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
1370{
1371 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1372}
1373
1374/**
1375 * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected
1376 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected
1377 * @retval State of bit (1 or 0).
1378 */
1379__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
1380{
1381 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1382}
1383
1384/**
1385 * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected
1386 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected
1387 * @retval State of bit (1 or 0).
1388 */
1389__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
1390{
1391 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1392}
1393
1394/**
1395 * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected
1396 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected
1397 * @retval State of bit (1 or 0).
1398 */
1399__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
1400{
1401 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1402}
1403
1404/**
1405 * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected
1406 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected
1407 * @retval State of bit (1 or 0).
1408 */
1409__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
1410{
1411 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1412}
1413
1414/**
1415 * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected
1416 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected
1417 * @retval State of bit (1 or 0).
1418 */
1419__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
1420{
1421 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1422}
1423
1424/**
1425 * @brief Get the protected area start address for Flash bank 1
1426 * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
1427 * @retval Returned the protected area start address for Flash bank 1
1428 */
1429__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
1430{
1431 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
1432}
1433
1434/**
1435 * @brief Get the protected area end address for Flash bank 1
1436 * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
1437 * @retval Returned the protected area end address for Flash bank 1
1438 */
1439__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
1440{
1441 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
1442}
1443
1444/**
1445 * @brief Get the secured area start address for Flash bank 1
1446 * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
1447 * @retval Returned the secured area start address for Flash bank 1
1448 */
1449__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
1450{
1451 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
1452}
1453
1454/**
1455 * @brief Get the secured area end address for Flash bank 1
1456 * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
1457 * @retval Returned the secured area end address for Flash bank 1
1458 */
1459__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
1460{
1461 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
1462}
1463
1464#ifdef SYSCFG_UR8_MEPAD_BANK2
1465/**
1466 * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase
1467 * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable
1468 * @retval State of bit (1 or 0).
1469 */
1470__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
1471{
1472 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
1473}
1474
1475/**
1476 * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase
1477 * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable
1478 * @retval State of bit (1 or 0).
1479 */
1480__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
1481{
1482 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
1483}
1484#endif /*SYSCFG_UR8_MEPAD_BANK2*/
1485
1486#ifdef SYSCFG_UR9_WRPN_BANK2
1487/**
1488 * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected
1489 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected
1490 * @retval State of bit (1 or 0).
1491 */
1492__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
1493{
1494 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1495}
1496
1497/**
1498 * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected
1499 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected
1500 * @retval State of bit (1 or 0).
1501 */
1502__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
1503{
1504 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1505}
1506
1507/**
1508 * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected
1509 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected
1510 * @retval State of bit (1 or 0).
1511 */
1512__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
1513{
1514 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1515}
1516
1517/**
1518 * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected
1519 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected
1520 * @retval State of bit (1 or 0).
1521 */
1522__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
1523{
1524 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1525}
1526
1527/**
1528 * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected
1529 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected
1530 * @retval State of bit (1 or 0).
1531 */
1532__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
1533{
1534 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1535}
1536
1537/**
1538 * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected
1539 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected
1540 * @retval State of bit (1 or 0).
1541 */
1542__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
1543{
1544 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1545}
1546
1547/**
1548 * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected
1549 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected
1550 * @retval State of bit (1 or 0).
1551 */
1552__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
1553{
1554 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1555}
1556
1557/**
1558 * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected
1559 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected
1560 * @retval State of bit (1 or 0).
1561 */
1562__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
1563{
1564 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1565}
1566
1567/**
1568 * @brief Get the protected area start address for Flash bank 2
1569 * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
1570 * @retval Returned the protected area start address for Flash bank 2
1571 */
1572__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
1573{
1574 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
1575}
1576#endif /*SYSCFG_UR9_WRPN_BANK2*/
1577
1578#ifdef SYSCFG_UR10_PAEND_BANK2
1579/**
1580 * @brief Get the protected area end address for Flash bank 2
1581 * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
1582 * @retval Returned the protected area end address for Flash bank 2
1583 */
1584__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
1585{
1586 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
1587}
1588
1589/**
1590 * @brief Get the secured area start address for Flash bank 2
1591 * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
1592 * @retval Returned the secured area start address for Flash bank 2
1593 */
1594__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
1595{
1596 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
1597}
1598#endif /*SYSCFG_UR10_PAEND_BANK2*/
1599
1600#ifdef SYSCFG_UR11_SAEND_BANK2
1601/**
1602 * @brief Get the secured area end address for Flash bank 2
1603 * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
1604 * @retval Returned the secured area end address for Flash bank 2
1605 */
1606__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
1607{
1608 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
1609}
1610#endif /*SYSCFG_UR11_SAEND_BANK2*/
1611
1612/**
1613 * @brief Get the Independent Watchdog 1 control mode (Software or Hardware)
1614 * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode
1615 * @retval Returned value can be one of the following values:
1616 * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
1617 * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
1618 */
1619__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
1620{
1621 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
1622}
1623
1624#if defined (DUAL_CORE)
1625/**
1626 * @brief Get the Independent Watchdog 2 control mode (Software or Hardware)
1627 * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode
1628 * @retval Returned value can be one of the following values:
1629 * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
1630 * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
1631 */
1632__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
1633{
1634 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
1635}
1636#endif /* DUAL_CORE */
1637
1638/**
1639 * @brief Indicates the Secure mode status
1640 * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled
1641 * @retval State of bit (1 or 0).
1642 */
1643__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
1644{
1645 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
1646}
1647
1648/**
1649 * @brief Indicates if a reset is generated when D1 domain enters DStandby mode
1650 * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset
1651 * @retval State of bit (1 or 0).
1652 */
1653__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
1654{
1655 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
1656}
1657
1658/**
1659 * @brief Get the secured DTCM RAM size
1660 * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize
1661 * @retval Returned value can be one of the following values:
1662 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
1663 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
1664 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
1665 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
1666 */
1667__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
1668{
1669 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
1670}
1671
1672/**
1673 * @brief Indicates if a reset is generated when D1 domain enters DStop mode
1674 * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset
1675 * @retval State of bit (1 or 0).
1676 */
1677__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
1678{
1679 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
1680}
1681
1682#if defined (DUAL_CORE)
1683/**
1684 * @brief Indicates if a reset is generated when D2 domain enters DStandby mode
1685 * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset
1686 * @retval State of bit (1 or 0).
1687 */
1688__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
1689{
1690 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
1691}
1692
1693/**
1694 * @brief Indicates if a reset is generated when D2 domain enters DStop mode
1695 * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset
1696 * @retval State of bit (1 or 0).
1697 */
1698__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
1699{
1700 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
1701}
1702#endif /* DUAL_CORE */
1703
1704/**
1705 * @brief Indicates if the independent watchdog is frozen in Standby mode
1706 * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode
1707 * @retval State of bit (1 or 0).
1708 */
1709__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
1710{
1711 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
1712}
1713
1714/**
1715 * @brief Indicates if the independent watchdog is frozen in Stop mode
1716 * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode
1717 * @retval State of bit (1 or 0).
1718 */
1719__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
1720{
1721 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
1722}
1723
1724/**
1725 * @brief Indicates if the device private key is programmed
1726 * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed
1727 * @retval State of bit (1 or 0).
1728 */
1729__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
1730{
1731 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
1732}
1733
1734/**
1735 * @brief Indicates if the Product is working on the full voltage range or not
1736 * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV
1737 * @note When the IOHSLV option bit is set the Product is working below 2.7 V.
1738 * When the IOHSLV option bit is reset the Product is working on the
1739 * full voltage range.
1740 * @retval State of bit (1 or 0).
1741 */
1742__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
1743{
1744 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
1745}
1746
1747#ifdef SYSCFG_UR17_TCM_AXI_CFG
1748/**
1749 * @brief Get the size of ITCM-RAM and AXI-SRAM
1750 * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size
1751 * @retval Returned value can be one of the following values:
1752 * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB
1753 * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB
1754 * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB
1755 * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB
1756 */
1757__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
1758{
1759 return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
1760}
1761#endif /*SYSCFG_UR17_TCM_AXI_CFG*/
1762
1763#ifdef SYSCFG_UR18_CPU_FREQ_BOOST
1764/**
1765 * @brief Indicates if the CPU maximum frequency boost is enabled
1766 * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled
1767 * @retval State of bit (1 or 0).
1768 */
1769__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
1770{
1771 return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
1772}
1773#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
1774
1775#endif /*SYSCFG_UR0_RDP*/
1776
1777/**
1778 * @}
1779 */
1780
1781/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1782 * @{
1783 */
1784
1785/**
1786 * @brief Return the device identifier
1787 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1788 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1789 */
1790__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1791{
1792 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1793}
1794
1795/**
1796 * @brief Return the device revision identifier
1797 * @note This field indicates the revision of the device.
1798 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
1799 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1800 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1801 */
1802__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1803{
1804 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1805}
1806
1807/**
1808 * @brief Enable D1 Domain/CDomain debug during SLEEP mode
1809 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode
1810 * @retval None
1811 */
1812__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
1813{
1814 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1815}
1816
1817/**
1818 * @brief Disable D1 Domain/CDomain debug during SLEEP mode
1819 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode
1820 * @retval None
1821 */
1822__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
1823{
1824 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1825}
1826
1827/**
1828 * @brief Enable D1 Domain/CDomain debug during STOP mode
1829 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode
1830 * @retval None
1831 */
1832__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
1833{
1834 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1835}
1836
1837/**
1838 * @brief Disable D1 Domain/CDomain debug during STOP mode
1839 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode
1840 * @retval None
1841 */
1842__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
1843{
1844 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1845}
1846
1847/**
1848 * @brief Enable D1 Domain/CDomain debug during STANDBY mode
1849 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode
1850 * @retval None
1851 */
1852__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
1853{
1854 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1855}
1856
1857/**
1858 * @brief Disable D1 Domain/CDomain debug during STANDBY mode
1859 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode
1860 * @retval None
1861 */
1862__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
1863{
1864 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1865}
1866
1867#if defined (DUAL_CORE)
1868/**
1869 * @brief Enable D2 Domain debug during SLEEP mode
1870 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode
1871 * @retval None
1872 */
1873__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
1874{
1875 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1876}
1877
1878/**
1879 * @brief Disable D2 Domain debug during SLEEP mode
1880 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode
1881 * @retval None
1882 */
1883__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
1884{
1885 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1886}
1887
1888/**
1889 * @brief Enable D2 Domain debug during STOP mode
1890 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode
1891 * @retval None
1892 */
1893__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
1894{
1895 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1896}
1897
1898/**
1899 * @brief Disable D2 Domain debug during STOP mode
1900 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode
1901 * @retval None
1902 */
1903__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
1904{
1905 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1906}
1907
1908/**
1909 * @brief Enable D2 Domain debug during STANDBY mode
1910 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode
1911 * @retval None
1912 */
1913__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
1914{
1915 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1916}
1917
1918/**
1919 * @brief Disable D2 Domain debug during STANDBY mode
1920 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode
1921 * @retval None
1922 */
1923__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
1924{
1925 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1926}
1927#endif /* DUAL_CORE */
1928
1929
1930#if defined(DBGMCU_CR_DBG_STOPD3)
1931/**
1932 * @brief Enable D3 Domain/SRDomain debug during STOP mode
1933 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode
1934 * @retval None
1935 */
1936__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
1937{
1938 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1939}
1940
1941/**
1942 * @brief Disable D3 Domain/SRDomain debug during STOP mode
1943 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode
1944 * @retval None
1945 */
1946__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
1947{
1948 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1949}
1950#endif /*DBGMCU_CR_DBG_STOPD3*/
1951
1952#if defined(DBGMCU_CR_DBG_STANDBYD3)
1953/**
1954 * @brief Enable D3 Domain/SRDomain debug during STANDBY mode
1955 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode
1956 * @retval None
1957 */
1958__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
1959{
1960 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1961}
1962
1963/**
1964 * @brief Disable D3 Domain/SRDomain debug during STANDBY mode
1965 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode
1966 * @retval None
1967 */
1968__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
1969{
1970 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1971}
1972#endif /*DBGMCU_CR_DBG_STANDBYD3*/
1973
1974/**
1975 * @brief Enable the trace port clock
1976 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock
1977 * @retval None
1978 */
1979__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
1980{
1981 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1982}
1983
1984/**
1985 * @brief Disable the trace port clock
1986 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock
1987 * @retval None
1988 */
1989__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
1990{
1991 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1992}
1993
1994/**
1995 * @brief Enable the Domain1/CDomain debug clock enable
1996 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock
1997 * @retval None
1998 */
1999__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
2000{
2001 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
2002}
2003
2004/**
2005 * @brief Disable the Domain1/CDomain debug clock enable
2006 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock
2007 * @retval None
2008 */
2009__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
2010{
2011 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
2012}
2013
2014/**
2015 * @brief Enable the Domain3/SRDomain debug clock enable
2016 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock
2017 * @retval None
2018 */
2019__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
2020{
2021 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2022}
2023
2024/**
2025 * @brief Disable the Domain3/SRDomain debug clock enable
2026 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock
2027 * @retval None
2028 */
2029__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
2030{
2031 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2032}
2033
2034#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
2035#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
2036/**
2037 * @brief Set the direction of the bi-directional trigger pin TRGIO
2038 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n
2039 * @param PinDirection This parameter can be one of the following values:
2040 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
2041 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
2042 * @retval None
2043 */
2044__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
2045{
2046 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
2047}
2048
2049/**
2050 * @brief Get the direction of the bi-directional trigger pin TRGIO
2051 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n
2052 * @retval Returned value can be one of the following values:
2053 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
2054 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
2055 */
2056__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
2057{
2058 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
2059}
2060
2061/**
2062 * @brief Freeze APB1 group1 peripherals
2063 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2064 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2065 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2066 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2067 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2068 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2069 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2070 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2071 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2072 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2073 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2074 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2075 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2076 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*)
2077 * @param Periphs This parameter can be a combination of the following values:
2078 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
2079 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
2080 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
2081 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
2082 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
2083 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
2084 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
2085 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
2086 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
2087 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
2088 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
2089 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
2090 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
2091 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
2092 *
2093 * (*) value not defined in all devices
2094 * @retval None
2095 */
2096__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
2097{
2098 SET_BIT(DBGMCU->APB1LFZ1, Periphs);
2099}
2100
2101/**
2102 * @brief Unfreeze APB1 peripherals (group1 peripherals)
2103 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2104 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2105 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2106 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2107 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2108 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2109 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2110 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2111 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2112 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2113 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2114 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2115 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2116 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2117 * @param Periphs This parameter can be a combination of the following values:
2118 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
2119 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
2120 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
2121 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
2122 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
2123 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
2124 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
2125 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
2126 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
2127 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
2128 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
2129 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
2130 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
2131 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
2132 *
2133 * (*) value not defined in all devices
2134 * @retval None
2135 */
2136__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
2137{
2138 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
2139}
2140
2141#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
2142/**
2143 * @brief Freeze APB1 group2 peripherals
2144 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2145 * @param Periphs This parameter can be a combination of the following values:
2146 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2147 * @retval None
2148 */
2149__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2150{
2151 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2152}
2153
2154/**
2155 * @brief Unfreeze APB1 group2 peripherals
2156 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2157 * @param Periphs This parameter can be a combination of the following values:
2158 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2159 * @retval None
2160 */
2161__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2162{
2163 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2164}
2165#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
2166
2167#if defined(TIM23) || defined(TIM24)
2168/**
2169 * @brief Freeze APB1 group2 peripherals
2170 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2171 * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2172 * @param Periphs This parameter can be a combination of the following values:
2173 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
2174 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
2175 * @retval None
2176 */
2177__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2178{
2179 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2180}
2181
2182/**
2183 * @brief Unfreeze APB1 group2 peripherals
2184 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2185 DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2186 * @param Periphs This parameter can be a combination of the following values:
2187 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
2188 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
2189 * @retval None
2190 */
2191__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2192{
2193 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2194}
2195#endif /* TIM23 || TIM24 */
2196
2197/**
2198 * @brief Freeze APB2 peripherals
2199 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2200 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2201 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2202 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2203 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2204 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2205 * @param Periphs This parameter can be a combination of the following values:
2206 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2207 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2208 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2209 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2210 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2211 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
2212 *
2213 * (*) value not defined in all devices
2214 * @retval None
2215 */
2216__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
2217{
2218 SET_BIT(DBGMCU->APB2FZ1, Periphs);
2219}
2220
2221/**
2222 * @brief Unfreeze APB2 peripherals
2223 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2224 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2225 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2226 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2227 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2228 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2229 * @param Periphs This parameter can be a combination of the following values:
2230 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2231 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2232 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2233 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2234 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2235 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
2236 *
2237 * (*) value not defined in all devices
2238 * @retval None
2239 */
2240__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
2241{
2242 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
2243}
2244
2245/**
2246 * @brief Freeze APB3 peripherals
2247 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
2248 * @param Periphs This parameter can be a combination of the following values:
2249 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2250 * @retval None
2251 */
2252__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
2253{
2254 SET_BIT(DBGMCU->APB3FZ1, Periphs);
2255}
2256
2257/**
2258 * @brief Unfreeze APB3 peripherals
2259 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
2260 * @param Periphs This parameter can be a combination of the following values:
2261 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2262 * @retval None
2263 */
2264__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
2265{
2266 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
2267}
2268
2269/**
2270 * @brief Freeze APB4 peripherals
2271 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2272 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2273 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2274 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2275 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2276 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2277 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2278 * @param Periphs This parameter can be a combination of the following values:
2279 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2280 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2281 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2282 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
2283 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
2284 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2285 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2286 *
2287 * (*) value not defined in all devices
2288 * @retval None
2289 */
2290__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
2291{
2292 SET_BIT(DBGMCU->APB4FZ1, Periphs);
2293}
2294
2295/**
2296 * @brief Unfreeze APB4 peripherals
2297 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2298 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2299 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2300 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2301 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2302 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2303 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2304 * @param Periphs This parameter can be a combination of the following values:
2305 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2306 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2307 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2308 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
2309 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
2310 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2311 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2312 *
2313 * (*) value not defined in all devices
2314 * @retval None
2315 */
2316__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
2317{
2318 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
2319}
2320/**
2321 * @}
2322 */
2323
2324/** @defgroup SYSTEM_LL_EF_FLASH FLASH
2325 * @{
2326 */
2327
2328/**
2329 * @brief Set FLASH Latency
2330 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
2331 * @param Latency This parameter can be one of the following values:
2332 * @arg @ref LL_FLASH_LATENCY_0
2333 * @arg @ref LL_FLASH_LATENCY_1
2334 * @arg @ref LL_FLASH_LATENCY_2
2335 * @arg @ref LL_FLASH_LATENCY_3
2336 * @arg @ref LL_FLASH_LATENCY_4
2337 * @arg @ref LL_FLASH_LATENCY_5
2338 * @arg @ref LL_FLASH_LATENCY_6
2339 * @arg @ref LL_FLASH_LATENCY_7
2340 * @retval None
2341 */
2342__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2343{
2344 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2345}
2346
2347/**
2348 * @brief Get FLASH Latency
2349 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
2350 * @retval Returned value can be one of the following values:
2351 * @arg @ref LL_FLASH_LATENCY_0
2352 * @arg @ref LL_FLASH_LATENCY_1
2353 * @arg @ref LL_FLASH_LATENCY_2
2354 * @arg @ref LL_FLASH_LATENCY_3
2355 * @arg @ref LL_FLASH_LATENCY_4
2356 * @arg @ref LL_FLASH_LATENCY_5
2357 * @arg @ref LL_FLASH_LATENCY_6
2358 * @arg @ref LL_FLASH_LATENCY_7
2359 */
2360__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2361{
2362 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2363}
2364
2365/**
2366 * @}
2367 */
2368
2369#if defined(DUAL_CORE)
2370/** @defgroup SYSTEM_LL_EF_ART ART
2371 * @{
2372 */
2373
2374/**
2375 * @brief Enable the Cortex-M4 ART cache.
2376 * @rmtoll ART_CTR EN LL_ART_Enable
2377 * @retval None
2378 */
2379__STATIC_INLINE void LL_ART_Enable(void)
2380{
2381 SET_BIT(ART->CTR, ART_CTR_EN);
2382}
2383
2384/**
2385 * @brief Disable the Cortex-M4 ART cache.
2386 * @rmtoll ART_CTR EN LL_ART_Disable
2387 * @retval None
2388 */
2389__STATIC_INLINE void LL_ART_Disable(void)
2390{
2391 CLEAR_BIT(ART->CTR, ART_CTR_EN);
2392}
2393
2394/**
2395 * @brief Check if the Cortex-M4 ART cache is enabled
2396 * @rmtoll ART_CTR EN LL_ART_IsEnabled
2397 * @retval State of bit (1 or 0).
2398 */
2399__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
2400{
2401 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
2402}
2403
2404/**
2405 * @brief Set the Cortex-M4 ART cache Base Address.
2406 * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress
2407 * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
2408 from which the ART accelerator loads code to the cache.
2409 * @retval None
2410 */
2411__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
2412{
2413 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
2414}
2415
2416/**
2417 * @brief Get the Cortex-M4 ART cache Base Address.
2418 * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress
2419 * @retval the Base address of 1 Mbyte address page (cacheable page)
2420 from which the ART accelerator loads code to the cache
2421 */
2422__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
2423{
2424 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
2425}
2426#endif /* DUAL_CORE */
2427
2428/**
2429 * @}
2430 */
2431
2432/**
2433 * @}
2434 */
2435
2436/**
2437 * @}
2438 */
2439
2440#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
2441
2442/**
2443 * @}
2444 */
2445
2446#ifdef __cplusplus
2447}
2448#endif
2449
2450#endif /* __STM32H7xx_LL_SYSTEM_H */
2451
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
POSITION_VAL
#define POSITION_VAL(VAL)
Definition stm32h7xx.h:221
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
SYSCFG_CCCSR_READY
#define SYSCFG_CCCSR_READY
I/O compensation cell ready flag.
Definition stm32h723xx.h:19101
DBGMCU_CR_DBG_TRACECKEN
#define DBGMCU_CR_DBG_TRACECKEN
Definition stm32h723xx.h:21738
SYSCFG_CFGR_SRAM4L
#define SYSCFG_CFGR_SRAM4L
SRAM4 double ECC error lock bit.
Definition stm32h723xx.h:19075
SYSCFG_UR5_WRPN_BANK1
#define SYSCFG_UR5_WRPN_BANK1
Write protection for flash bank 1.
Definition stm32h723xx.h:19165
SYSCFG_CCCSR_HSLV
#define SYSCFG_CCCSR_HSLV
High-speed at low-voltage.
Definition stm32h723xx.h:19104
SYSCFG_CCVR_PCV
#define SYSCFG_CCVR_PCV
PMOS compensation value.
Definition stm32h723xx.h:19112
SYSCFG_PMCR_BOOSTEN
#define SYSCFG_PMCR_BOOSTEN
I/O analog switch voltage booster enable.
Definition stm32h723xx.h:18760
SYSCFG_CFGR_BKRAML
#define SYSCFG_CFGR_BKRAML
Backup SRAM double ECC error lock bit.
Definition stm32h723xx.h:19072
SYSCFG_UR12_SECURE
#define SYSCFG_UR12_SECURE
Secure mode status.
Definition stm32h723xx.h:19193
SYSCFG_UR5_MESAD_BANK1
#define SYSCFG_UR5_MESAD_BANK1
Mass erase secured area disabled for bank 1.
Definition stm32h723xx.h:19162
SYSCFG_CCCSR_EN
#define SYSCFG_CCCSR_EN
I/O compensation cell enable.
Definition stm32h723xx.h:19095
SYSCFG_CFGR_DTCML
#define SYSCFG_CFGR_DTCML
DTCM double ECC error lock bit.
Definition stm32h723xx.h:19084
DBGMCU_CR_DBG_STOPD1
#define DBGMCU_CR_DBG_STOPD1
Definition stm32h723xx.h:21726
DBGMCU_CR_DBG_SLEEPD1
#define DBGMCU_CR_DBG_SLEEPD1
Definition stm32h723xx.h:21723
SYSCFG_UR6_PAEND_BANK1
#define SYSCFG_UR6_PAEND_BANK1
Protected area end address for bank 1.
Definition stm32h723xx.h:19173
SYSCFG_UR13_SDRS
#define SYSCFG_UR13_SDRS
Secured DTCM RAM Size.
Definition stm32h723xx.h:19198
SYSCFG_CFGR_AXISRAML
#define SYSCFG_CFGR_AXISRAML
AXISRAM double ECC error lock bit.
Definition stm32h723xx.h:19090
SYSCFG_CCCSR_CS
#define SYSCFG_CCCSR_CS
I/O compensation cell code selection.
Definition stm32h723xx.h:19098
DBGMCU_CR_DBG_CKD1EN
#define DBGMCU_CR_DBG_CKD1EN
Definition stm32h723xx.h:21741
SYSCFG_CFGR_CM7L
#define SYSCFG_CFGR_CM7L
Cortex-M7 LOCKUP (Hardfault) output enable bit.
Definition stm32h723xx.h:19069
DBGMCU_CR_DBG_STANDBYD3
#define DBGMCU_CR_DBG_STANDBYD3
Definition stm32h723xx.h:21735
SYSCFG_UR2_BOOT_ADD0
#define SYSCFG_UR2_BOOT_ADD0
Core Boot Address 0.
Definition stm32h723xx.h:19147
DBGMCU_IDCODE_REV_ID_Pos
#define DBGMCU_IDCODE_REV_ID_Pos
Definition stm32h723xx.h:21716
SYSCFG_UR14_D1STPRST
#define SYSCFG_UR14_D1STPRST
D1 Stop Reset.
Definition stm32h723xx.h:19206
SYSCFG_UR2_BOOT_ADD0_Pos
#define SYSCFG_UR2_BOOT_ADD0_Pos
Definition stm32h723xx.h:19145
SYSCFG_PMCR_EPIS_SEL
#define SYSCFG_PMCR_EPIS_SEL
Ethernet PHY Interface Selection.
Definition stm32h723xx.h:18772
SYSCFG_UR17_IOHSLV
#define SYSCFG_UR17_IOHSLV
I/O high speed / low voltage.
Definition stm32h723xx.h:19224
SYSCFG_CFGR_ITCML
#define SYSCFG_CFGR_ITCML
ITCM double ECC error lock bit.
Definition stm32h723xx.h:19087
SYSCFG_CCCR_NCC
#define SYSCFG_CCCR_NCC
NMOS compensation code.
Definition stm32h723xx.h:19117
DBGMCU_IDCODE_REV_ID
#define DBGMCU_IDCODE_REV_ID
Definition stm32h723xx.h:21718
SYSCFG_UR6_PABEG_BANK1
#define SYSCFG_UR6_PABEG_BANK1
Protected area start address for bank 1.
Definition stm32h723xx.h:19170
SYSCFG_UR18_CPU_FREQ_BOOST
#define SYSCFG_UR18_CPU_FREQ_BOOST
CPU maximum frequency boost enable.
Definition stm32h723xx.h:19232
SYSCFG_CFGR_SRAM2L
#define SYSCFG_CFGR_SRAM2L
SRAM2 double ECC error lock bit.
Definition stm32h723xx.h:19078
SYSCFG_CFGR_FLASHL
#define SYSCFG_CFGR_FLASHL
FLASH double ECC error lock bit.
Definition stm32h723xx.h:19066
SYSCFG_UR0_RDP
#define SYSCFG_UR0_RDP
Readout protection.
Definition stm32h723xx.h:19137
SYSCFG_CFGR_SRAM1L
#define SYSCFG_CFGR_SRAM1L
SRAM1 double ECC error lock bit.
Definition stm32h723xx.h:19081
SYSCFG_CCCR_PCC
#define SYSCFG_CCCR_PCC
PMOS compensation code.
Definition stm32h723xx.h:19120
SYSCFG_UR11_IWDG1M
#define SYSCFG_UR11_IWDG1M
Independent Watchdog 1 mode (SW or HW).
Definition stm32h723xx.h:19187
SYSCFG_UR17_TCM_AXI_CFG
#define SYSCFG_UR17_TCM_AXI_CFG
ITCM-RAM / AXI-SRAM size.
Definition stm32h723xx.h:19227
SYSCFG_UR2_BORH
#define SYSCFG_UR2_BORH
Brown Out Reset High level.
Definition stm32h723xx.h:19142
SYSCFG_UR7_SAEND_BANK1
#define SYSCFG_UR7_SAEND_BANK1
Secured area end address for bank 1.
Definition stm32h723xx.h:19181
SYSCFG_CFGR_PVDL
#define SYSCFG_CFGR_PVDL
PVD lock enable bit.
Definition stm32h723xx.h:19063
SYSCFG_UR3_BOOT_ADD1
#define SYSCFG_UR3_BOOT_ADD1
Core Boot Address 1.
Definition stm32h723xx.h:19151
SYSCFG_CCVR_NCV
#define SYSCFG_CCVR_NCV
NMOS compensation value.
Definition stm32h723xx.h:19109
SYSCFG_UR16_FZIWDGSTP
#define SYSCFG_UR16_FZIWDGSTP
Freeze independent watchdogs in Stop mode.
Definition stm32h723xx.h:19216
SYSCFG_UR4_MEPAD_BANK1
#define SYSCFG_UR4_MEPAD_BANK1
Mass Erase Protected Area Disabled for bank 1.
Definition stm32h723xx.h:19157
DBGMCU_CR_DBG_STOPD3
#define DBGMCU_CR_DBG_STOPD3
Definition stm32h723xx.h:21732
SYSCFG_UR7_SABEG_BANK1
#define SYSCFG_UR7_SABEG_BANK1
Secured area start address for bank 1.
Definition stm32h723xx.h:19178
DBGMCU_CR_DBG_STANDBYD1
#define DBGMCU_CR_DBG_STANDBYD1
Definition stm32h723xx.h:21729
SYSCFG_PKGR_PKG
#define SYSCFG_PKGR_PKG
Package type.
Definition stm32h723xx.h:19132
SYSCFG_UR13_D1SBRST
#define SYSCFG_UR13_D1SBRST
D1 Standby reset.
Definition stm32h723xx.h:19201
FLASH_ACR_LATENCY
#define FLASH_ACR_LATENCY
Read Latency.
Definition stm32h723xx.h:10826
DBGMCU_CR_DBG_CKD3EN
#define DBGMCU_CR_DBG_CKD3EN
Definition stm32h723xx.h:21744
SYSCFG_UR16_PKP
#define SYSCFG_UR16_PKP
Private key programmed.
Definition stm32h723xx.h:19219
DBGMCU_IDCODE_DEV_ID
#define DBGMCU_IDCODE_DEV_ID
Definition stm32h723xx.h:21715
DBGMCU_CR_DBG_TRGOEN
#define DBGMCU_CR_DBG_TRGOEN
Definition stm32h723xx.h:21747
SYSCFG_UR15_FZIWDGSTB
#define SYSCFG_UR15_FZIWDGSTB
Freeze independent watchdogs in Standby mode.
Definition stm32h723xx.h:19211
SYSCFG
#define SYSCFG
Definition stm32h723xx.h:2467
FLASH
#define FLASH
Definition stm32h723xx.h:2512
DBGMCU
#define DBGMCU
Definition stm32h723xx.h:2655
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.