20#ifndef STM32H7xx_LL_USB_H
21#define STM32H7xx_LL_USB_H
30#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
40#ifndef HAL_USB_TIMEOUT
41#define HAL_USB_TIMEOUT 0xF000000U
44#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
45#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
59#if defined (HAL_HCD_MODULE_ENABLED)
98 uint8_t dev_endpoints;
102 uint8_t Host_channels;
120 uint8_t low_power_enable;
124 uint8_t battery_charging_enable;
126 uint8_t vbus_sensing_enable;
128 uint8_t use_dedicated_ep1;
130 uint8_t use_external_vbus;
134#if defined (HAL_PCD_MODULE_ENABLED)
146 uint8_t is_iso_incomplete;
152 uint8_t data_pid_start;
164 uint8_t even_odd_frame;
167 uint16_t tx_fifo_num;
176#if defined (HAL_HCD_MODULE_ENABLED)
201 uint8_t ep_ss_schedule;
202 uint32_t iso_splt_xactPos;
204 uint8_t hub_port_nbr;
237 USB_URBStateTypeDef urb_state;
240 USB_HCStateTypeDef
state;
245typedef USB_ModeTypeDef USB_OTG_ModeTypeDef;
246typedef USB_CfgTypeDef USB_OTG_CfgTypeDef;
248#if defined (HAL_PCD_MODULE_ENABLED)
249typedef USB_EPTypeDef USB_OTG_EPTypeDef;
252#if defined (HAL_HCD_MODULE_ENABLED)
253typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
254typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef;
255typedef USB_HCTypeDef USB_OTG_HCTypeDef;
264#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
268#define USB_OTG_CORE_ID_300A 0x4F54300AU
269#define USB_OTG_CORE_ID_310A 0x4F54310AU
277#define USB_OTG_MODE_DEVICE 0U
278#define USB_OTG_MODE_HOST 1U
279#define USB_OTG_MODE_DRD 2U
287#define USB_OTG_SPEED_HIGH 0U
288#define USB_OTG_SPEED_HIGH_IN_FULL 1U
289#define USB_OTG_SPEED_FULL 3U
297#define USB_OTG_ULPI_PHY 1U
298#define USB_OTG_EMBEDDED_PHY 2U
306#ifndef USBD_HS_TRDT_VALUE
307#define USBD_HS_TRDT_VALUE 9U
309#ifndef USBD_FS_TRDT_VALUE
310#define USBD_FS_TRDT_VALUE 5U
311#define USBD_DEFAULT_TRDT_VALUE 9U
320#define USB_OTG_HS_MAX_PACKET_SIZE 512U
321#define USB_OTG_FS_MAX_PACKET_SIZE 64U
322#define USB_OTG_MAX_EP0_SIZE 64U
330#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0UL << 1)
331#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1UL << 1)
332#define DSTS_ENUMSPD_FS_PHY_48MHZ (3UL << 1)
340#define DCFG_FRAME_INTERVAL_80 0U
341#define DCFG_FRAME_INTERVAL_85 1U
342#define DCFG_FRAME_INTERVAL_90 2U
343#define DCFG_FRAME_INTERVAL_95 3U
362#define EP_TYPE_CTRL 0U
363#define EP_TYPE_ISOC 1U
364#define EP_TYPE_BULK 2U
365#define EP_TYPE_INTR 3U
366#define EP_TYPE_MSK 3U
374#define EP_SPEED_LOW 0U
375#define EP_SPEED_FULL 1U
376#define EP_SPEED_HIGH 2U
384#define HC_PID_DATA0 0U
385#define HC_PID_DATA2 1U
386#define HC_PID_DATA1 2U
387#define HC_PID_SETUP 3U
395#define USBD_HS_SPEED 0U
396#define USBD_HSINFS_SPEED 1U
397#define USBH_HS_SPEED 0U
398#define USBD_FS_SPEED 2U
399#define USBH_FSLS_SPEED 1U
404#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
408#define STS_GOUT_NAK 1U
409#define STS_DATA_UPDT 2U
410#define STS_XFER_COMP 3U
411#define STS_SETUP_COMP 4U
412#define STS_SETUP_UPDT 6U
420#define HCFG_30_60_MHZ 0U
421#define HCFG_48_MHZ 1U
430#define HFIR_6_MHZ 6000U
431#define HFIR_60_MHZ 60000U
432#define HFIR_48_MHZ 48000U
440#define HPRT0_PRTSPD_HIGH_SPEED 0UL
441#define HPRT0_PRTSPD_FULL_SPEED 1UL
442#define HPRT0_PRTSPD_LOW_SPEED 2UL
447#define HCCHAR_CTRL 0U
448#define HCCHAR_ISOC 1U
449#define HCCHAR_BULK 2U
450#define HCCHAR_INTR 3U
452#define GRXSTS_PKTSTS_IN 2U
453#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
454#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
455#define GRXSTS_PKTSTS_CH_HALTED 7U
457#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
459#define HC_MAX_PKT_CNT 256U
460#define ISO_SPLT_MPS 188U
462#define HCSPLT_BEGIN 1U
463#define HCSPLT_MIDDLE 2U
465#define HCSPLT_FULL 4U
469#define TEST_SE0_NAK 3U
470#define TEST_PACKET 4U
471#define TEST_FORCE_EN 5U
473#define USB_OTG_GAHBCFG_HBSTLEN_SINGLE (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
474#define USB_OTG_GAHBCFG_HBSTLEN_INCR (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
475#define USB_OTG_GAHBCFG_HBSTLEN_INCR4 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
476#define USB_OTG_GAHBCFG_HBSTLEN_INCR8 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
477#define USB_OTG_GAHBCFG_HBSTLEN_INCR16 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
479#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
480#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
482#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
483#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
484 + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
486#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
487 + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
489#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
491#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
492#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
493 + USB_OTG_HOST_CHANNEL_BASE\
494 + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
497#define EP_ADDR_MSK 0xFU
507#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
508#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
509#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
511#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
512#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
522#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
533#if defined (HAL_PCD_MODULE_ENABLED)
545 uint8_t ch_ep_num, uint16_t len, uint8_t dma);
574#if defined (HAL_HCD_MODULE_ENABLED)
576 uint8_t epnum, uint8_t dev_address, uint8_t speed,
577 uint8_t ep_type, uint16_t mps);
579 USB_OTG_HCTypeDef *hc, uint8_t dma);
static ActuatorControllerState state
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.