|
STAR
Cal STAR — firmware, DAQ server, and engine design
|
Go to the source code of this file.
Macros | |
| #define | ARM_CACHEL1_ARMV7_H |
Functions | |
| __STATIC_FORCEINLINE void | SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) |
| I-Cache Invalidate by address. | |
| __STATIC_FORCEINLINE void | SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) |
| D-Cache Invalidate by address. | |
| __STATIC_FORCEINLINE void | SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) |
| D-Cache Clean by address. | |
| __STATIC_FORCEINLINE void | SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) |
| D-Cache Clean and Invalidate by address. | |
| #define | CCSIDR_WAYS(x) |
| #define | CCSIDR_SETS(x) |
| #define | __SCB_DCACHE_LINE_SIZE 32U |
| Cortex-M7 cache line size is fixed to 32 bytes (8 words). | |
| #define | __SCB_ICACHE_LINE_SIZE 32U |
| Cortex-M7 cache line size is fixed to 32 bytes (8 words). | |
| __STATIC_FORCEINLINE void | SCB_EnableICache (void) |
| Enable I-Cache. | |
| __STATIC_FORCEINLINE void | SCB_DisableICache (void) |
| Disable I-Cache. | |
| __STATIC_FORCEINLINE void | SCB_InvalidateICache (void) |
| Invalidate I-Cache. | |
| __STATIC_FORCEINLINE void | SCB_EnableDCache (void) |
| Enable D-Cache. | |
| __STATIC_FORCEINLINE void | SCB_DisableDCache (void) |
| Disable D-Cache. | |
| __STATIC_FORCEINLINE void | SCB_InvalidateDCache (void) |
| Invalidate D-Cache. | |
| __STATIC_FORCEINLINE void | SCB_CleanDCache (void) |
| Clean D-Cache. | |
| __STATIC_FORCEINLINE void | SCB_CleanInvalidateDCache (void) |
| Clean & Invalidate D-Cache. | |
| #define ARM_CACHEL1_ARMV7_H |
Definition at line 32 of file cachel1_armv7.h.