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ADC Private Macros
Collaboration diagram for ADC Private Macros:

Macros

#define IS_ADC_CONVERSIONDATAMGT(DATA)
 Verify the ADC data conversion setting.
#define ADC_GET_RESOLUTION(__HANDLE__)
 Return resolution bits in CFGR register RES[1:0] field.
#define ADC_CLEAR_ERRORCODE(__HANDLE__)
 Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define ADC_IS_ENABLE(__HANDLE__)
 Verification of ADC state: enabled or disabled.
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)
 Check if conversion is on going on regular group.
#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)
 Check if ADC clock mode is synchronous.
#define ADC_STATE_CLR_SET   MODIFY_REG
 Simultaneously clear and set specific bits of the handle State.
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)
 Verify that a given value is aligned with the ADC resolution range.
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__)
 Verify the length of the scheduled regular conversions group.
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER)
 Verify the number of scheduled regular conversions in discontinuous mode.
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
 Verify the ADC clock setting.
#define IS_ADC_RESOLUTION(__RESOLUTION__)
 Verify the ADC resolution setting.
#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__)
 Verify the ADC resolution setting when limited to 8 bits.
#define IS_ADC_SCAN_MODE(__SCAN_MODE__)
 Verify the ADC scan mode.
#define IS_ADC_EXTTRIG_EDGE(__EDGE__)
 Verify the ADC edge trigger setting for regular group.
#define IS_ADC_EXTTRIG(__REGTRIG__)
 Verify the ADC regular conversions external trigger.
#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
 Verify the ADC regular conversions check for converted data availability.
#define IS_ADC_OVERRUN(__OVR__)
 Verify the ADC regular conversions overrun handling.
#define IS_ADC_SAMPLE_TIME(__TIME__)
 Verify the ADC conversions sampling time.
#define IS_ADC_REGULAR_RANK(__CHANNEL__)
 Verify the ADC regular channel setting.

Detailed Description

Macro Definition Documentation

◆ ADC_CLEAR_ERRORCODE

#define ADC_CLEAR_ERRORCODE ( __HANDLE__)
Value:
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
#define HAL_ADC_ERROR_NONE
No error.

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters
__HANDLE__ADC handle
Return values
None

Definition at line 954 of file stm32h7xx_hal_adc.h.

◆ ADC_GET_RESOLUTION

#define ADC_GET_RESOLUTION ( __HANDLE__)
Value:
(LL_ADC_GetResolution((__HANDLE__)->Instance))

Return resolution bits in CFGR register RES[1:0] field.

Parameters
__HANDLE__ADC handle
Return values
Valueof bitfield RES in CFGR register.

Definition at line 946 of file stm32h7xx_hal_adc.h.

◆ ADC_IS_CONVERSION_ONGOING_REGULAR

#define ADC_IS_CONVERSION_ONGOING_REGULAR ( __HANDLE__)
Value:
(LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))

Check if conversion is on going on regular group.

Parameters
__HANDLE__ADC handle
Return values
Value"0" (no conversion is on going) or value "1" (conversion is on going)

Definition at line 971 of file stm32h7xx_hal_adc.h.

◆ ADC_IS_ENABLE

#define ADC_IS_ENABLE ( __HANDLE__)
Value:
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
) ? SET : RESET)
#define ADC_FLAG_RDY
ADC Ready flag.
@ RESET
Definition stm32h7xx.h:182
@ SET
Definition stm32h7xx.h:183
#define ADC_CR_ADEN
ADC Enable control.
#define ADC_CR_ADDIS
ADC Disable command.

Verification of ADC state: enabled or disabled.

Parameters
__HANDLE__ADC handle
Return values
SET(ADC enabled) or RESET (ADC disabled)

Definition at line 961 of file stm32h7xx_hal_adc.h.

◆ ADC_IS_SYNCHRONOUS_CLOCK_MODE

#define ADC_IS_SYNCHRONOUS_CLOCK_MODE ( __HANDLE__)
Value:
((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
#define ADC_CCR_CKMODE
ADC clock mode.
#define ADC12_COMMON

Check if ADC clock mode is synchronous.

Parameters
__HANDLE__ADC handle
Return values
SET(clock mode is synchronous) or RESET (clock mode is asynchronous)

Definition at line 985 of file stm32h7xx_hal_adc.h.

◆ ADC_STATE_CLR_SET

#define ADC_STATE_CLR_SET   MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values
None

Definition at line 996 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_CLOCKPRESCALER

#define IS_ADC_CLOCKPRESCALER ( __ADC_CLOCK__)
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
#define ADC_CLOCK_ASYNC_DIV10
ADC asynchronous clock with prescaler division by 10.
#define ADC_CLOCK_ASYNC_DIV1
ADC asynchronous clock without prescaler.
#define ADC_CLOCK_SYNC_PCLK_DIV4
ADC synchronous clock derived from AHB clock with prescaler division by 4.
#define ADC_CLOCK_ASYNC_DIV12
ADC asynchronous clock with prescaler division by 12.
#define ADC_CLOCK_ASYNC_DIV256
ADC asynchronous clock with prescaler division by 256.
#define ADC_CLOCK_ASYNC_DIV6
ADC asynchronous clock with prescaler division by 6.
#define ADC_CLOCK_ASYNC_DIV4
ADC asynchronous clock with prescaler division by 4.
#define ADC_CLOCK_SYNC_PCLK_DIV2
ADC synchronous clock derived from AHB clock with prescaler division by 2.
#define ADC_CLOCK_ASYNC_DIV8
ADC asynchronous clock with prescaler division by 8.
#define ADC_CLOCK_SYNC_PCLK_DIV1
ADC synchronous clock derived from AHB clock without prescaler.
#define ADC_CLOCK_ASYNC_DIV128
ADC asynchronous clock with prescaler division by 128.
#define ADC_CLOCK_ASYNC_DIV16
ADC asynchronous clock with prescaler division by 16.
#define ADC_CLOCK_ASYNC_DIV2
ADC asynchronous clock with prescaler division by 2.
#define ADC_CLOCK_ASYNC_DIV64
ADC asynchronous clock with prescaler division by 64.
#define ADC_CLOCK_ASYNC_DIV32
ADC asynchronous clock with prescaler division by 32.

Verify the ADC clock setting.

Parameters
__ADC_CLOCK__programmed ADC clock.
Return values
SET(ADC_CLOCK is a valid value) or RESET (ADC_CLOCK is invalid)

Definition at line 1038 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_CONVERSIONDATAMGT

#define IS_ADC_CONVERSIONDATAMGT ( DATA)
Value:
((((DATA) == ADC_CONVERSIONDATA_DR)) || \
(((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \
(((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
#define ADC_CONVERSIONDATA_DMA_CIRCULAR
DMA circular mode selected.
#define ADC_CONVERSIONDATA_DFSDM
DFSDM mode selected.
#define ADC_CONVERSIONDATA_DMA_ONESHOT
DMA one shot mode selected.
#define ADC_CONVERSIONDATA_DR
Regular Conversion data stored in DR register only.

Verify the ADC data conversion setting.

Parameters
DATA: programmed DATA conversion mode.
Return values
SET(DATA is a valid value) or RESET (DATA is invalid)

Definition at line 935 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_EOC_SELECTION

#define IS_ADC_EOC_SELECTION ( __EOC_SELECTION__)
Value:
(((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
#define ADC_EOC_SINGLE_CONV
End of unitary conversion flag.
#define ADC_EOC_SEQ_CONV
End of sequence conversions flag.

Verify the ADC regular conversions check for converted data availability.

Parameters
__EOC_SELECTION__converted data availability check.
Return values
SET(EOC_SELECTION is a valid value) or RESET (EOC_SELECTION is invalid)

Definition at line 1188 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_EXTTRIG

#define IS_ADC_EXTTRIG ( __REGTRIG__)
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#define ADC_EXTERNALTRIG_T1_CC3
ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare:...
#define ADC_EXTERNALTRIG_T8_TRGO
ADC group regular conversion trigger from external peripheral: TIM8 TRGO event.
#define ADC_EXTERNALTRIG_T8_TRGO2
ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event.
#define ADC_EXTERNALTRIG_T15_TRGO
ADC group regular conversion trigger from external peripheral: TIM15 TRGO event.
#define ADC_EXTERNALTRIG_HR1_ADCTRG3
ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event.
#define ADC_SOFTWARE_START
ADC group regular conversion trigger internal: SW start.
#define ADC_EXTERNALTRIG_LPTIM1_OUT
ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event.
#define ADC_EXTERNALTRIG_T1_TRGO
ADC group regular conversion trigger from external peripheral: TIM1 TRGO event.
#define ADC_EXTERNALTRIG_T1_CC2
ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare:...
#define ADC_EXTERNALTRIG_T1_CC1
ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare:...
#define ADC_EXTERNALTRIG_T3_TRGO
ADC group regular conversion trigger from external peripheral: TIM3 TRGO event.
#define ADC_EXTERNALTRIG_EXT_IT11
ADC group regular conversion trigger from external peripheral: external interrupt line 11 event.
#define ADC_EXTERNALTRIG_T6_TRGO
ADC group regular conversion trigger from external peripheral: TIM6 TRGO event.
#define ADC_EXTERNALTRIG_T1_TRGO2
ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event.
#define ADC_EXTERNALTRIG_LPTIM3_OUT
ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT.
#define ADC_EXTERNALTRIG_T4_CC4
ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare:...
#define ADC_EXTERNALTRIG_T2_TRGO
ADC group regular conversion trigger from external peripheral: TIM2 TRGO event.
#define ADC_EXTERNALTRIG_T3_CC4
ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare:...
#define ADC_EXTERNALTRIG_T2_CC2
ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare:...
#define ADC_EXTERNALTRIG_T4_TRGO
ADC group regular conversion trigger from external peripheral: TIM4 TRGO event.
#define ADC_EXTERNALTRIG_HR1_ADCTRG1
ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event.
#define ADC_EXTERNALTRIG_LPTIM2_OUT
ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event.

Verify the ADC regular conversions external trigger.

Parameters
__REGTRIG__programmed ADC regular conversions external trigger.
Return values
SET(REGTRIG is a valid value) or RESET (REGTRIG is invalid)

Definition at line 1158 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_EXTTRIG_EDGE

#define IS_ADC_EXTTRIG_EDGE ( __EDGE__)
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
#define ADC_EXTERNALTRIGCONVEDGE_RISING
ADC group regular conversion trigger polarity set to rising edge.
#define ADC_EXTERNALTRIGCONVEDGE_FALLING
ADC group regular conversion trigger polarity set to falling edge.
#define ADC_EXTERNALTRIGCONVEDGE_NONE
Regular conversions hardware trigger detection disabled.
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
ADC group regular conversion trigger polarity set to both rising and falling edges.

Verify the ADC edge trigger setting for regular group.

Parameters
__EDGE__programmed ADC edge trigger setting.
Return values
SET(EDGE is a valid value) or RESET (EDGE is invalid)

Definition at line 1122 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_OVERRUN

#define IS_ADC_OVERRUN ( __OVR__)
Value:
(((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
#define ADC_OVR_DATA_PRESERVED
ADC group regular behavior in case of overrun: data preserved.
#define ADC_OVR_DATA_OVERWRITTEN
ADC group regular behavior in case of overrun: data overwritten.

Verify the ADC regular conversions overrun handling.

Parameters
__OVR__ADC regular conversions overrun handling.
Return values
SET(OVR is a valid value) or RESET (OVR is invalid)

Definition at line 1196 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_RANGE

#define IS_ADC_RANGE ( __RESOLUTION__,
__ADC_VALUE__ )
Value:
((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

Verify that a given value is aligned with the ADC resolution range.

Parameters
__RESOLUTION__ADC resolution (16, 14, 12, 10 or 8 bits).
__ADC_VALUE__value checked against the resolution.
Return values
SET(ADC_VALUE in line with RESOLUTION) or RESET (ADC_VALUE not in line with RESOLUTION)

Definition at line 1004 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_REGULAR_DISCONT_NUMBER

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER)
Value:
(((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters
NUMBERnumber of scheduled regular conversions in discontinuous mode.
Return values
SET(NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)

Definition at line 1030 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_REGULAR_NB_CONV

#define IS_ADC_REGULAR_NB_CONV ( __LENGTH__)
Value:
(((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

Verify the length of the scheduled regular conversions group.

Parameters
__LENGTH__number of programmed conversions.
Return values
SET(LENGTH is within the maximum number of possible programmable regular conversions) or RESET (LENGTH is null or too large)

Definition at line 1022 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_REGULAR_RANK

#define IS_ADC_REGULAR_RANK ( __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
#define ADC_REGULAR_RANK_12
ADC group regular sequencer rank 12.
#define ADC_REGULAR_RANK_2
ADC group regular sequencer rank 2.
#define ADC_REGULAR_RANK_5
ADC group regular sequencer rank 5.
#define ADC_REGULAR_RANK_9
ADC group regular sequencer rank 9.
#define ADC_REGULAR_RANK_15
ADC group regular sequencer rank 15.
#define ADC_REGULAR_RANK_7
ADC group regular sequencer rank 7.
#define ADC_REGULAR_RANK_6
ADC group regular sequencer rank 6.
#define ADC_REGULAR_RANK_16
ADC group regular sequencer rank 16.
#define ADC_REGULAR_RANK_14
ADC group regular sequencer rank 14.
#define ADC_REGULAR_RANK_8
ADC group regular sequencer rank 8.
#define ADC_REGULAR_RANK_10
ADC group regular sequencer rank 10.
#define ADC_REGULAR_RANK_11
ADC group regular sequencer rank 11.
#define ADC_REGULAR_RANK_3
ADC group regular sequencer rank 3.
#define ADC_REGULAR_RANK_1
ADC group regular sequencer rank 1.
#define ADC_REGULAR_RANK_4
ADC group regular sequencer rank 4.
#define ADC_REGULAR_RANK_13
ADC group regular sequencer rank 13.

Verify the ADC regular channel setting.

Parameters
__CHANNEL__programmed ADC regular channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

Definition at line 1218 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_RESOLUTION

#define IS_ADC_RESOLUTION ( __RESOLUTION__)
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
((__RESOLUTION__) == ADC_RESOLUTION_8B) )
#define ADC_RESOLUTION_14B
ADC resolution 14 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instanc...
#define ADC_RESOLUTION_8B
ADC resolution 8 bits.
#define ADC_RESOLUTION_12B
ADC resolution 12 bits.
#define ADC_RESOLUTION_16B
ADC resolution 16 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instanc...
#define ADC_RESOLUTION_10B
ADC resolution 10 bits.

Verify the ADC resolution setting.

Parameters
__RESOLUTION__programmed ADC resolution.
Return values
SET(RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)

Definition at line 1075 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_RESOLUTION_8_BITS

#define IS_ADC_RESOLUTION_8_BITS ( __RESOLUTION__)
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_8B))

Verify the ADC resolution setting when limited to 8 bits.

Parameters
__RESOLUTION__programmed ADC resolution when limited to 8 bits.
Return values
SET(RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)

Definition at line 1087 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_SAMPLE_TIME

#define IS_ADC_SAMPLE_TIME ( __TIME__)
Value:
(((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) )
#define ADC_SAMPLETIME_1CYCLE_5
Sampling time 1.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on...
#define ADC_SAMPLETIME_64CYCLES_5
Sampling time 64.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only o...
#define ADC_SAMPLETIME_8CYCLES_5
Sampling time 8.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on...
#define ADC_SAMPLETIME_810CYCLES_5
Sampling time 810.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only ...
#define ADC_SAMPLETIME_16CYCLES_5
Sampling time 16.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only o...
#define ADC_SAMPLETIME_32CYCLES_5
Sampling time 32.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only o...
#define ADC_SAMPLETIME_2CYCLES_5
Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on...
#define ADC_SAMPLETIME_387CYCLES_5
Sampling time 387.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only ...

Verify the ADC conversions sampling time.

Parameters
__TIME__ADC conversions sampling time.
Return values
SET(TIME is a valid value) or RESET (TIME is invalid)

Definition at line 1204 of file stm32h7xx_hal_adc.h.

◆ IS_ADC_SCAN_MODE

#define IS_ADC_SCAN_MODE ( __SCAN_MODE__)
Value:
(((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
#define ADC_SCAN_ENABLE
Scan mode enabled.
#define ADC_SCAN_DISABLE
Scan mode disabled.

Verify the ADC scan mode.

Parameters
__SCAN_MODE__programmed ADC scan mode.
Return values
SET(SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)

Definition at line 1114 of file stm32h7xx_hal_adc.h.