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stm32h7xx_hal_adc.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_hal_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_ADC_H
21#define STM32H7xx_HAL_ADC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
30/* Include low level driver */
31#include "stm32h7xx_ll_adc.h"
32
33/** @addtogroup STM32H7xx_HAL_Driver
34 * @{
35 */
36
37/** @addtogroup ADC
38 * @{
39 */
40
41/* Exported types ------------------------------------------------------------*/
42/** @defgroup ADC_Exported_Types ADC Exported Types
43 * @{
44 */
45
46/**
47 * @brief ADC group regular oversampling structure definition
48 */
49typedef struct
50{
51 uint32_t Ratio; /*!< Configures the oversampling ratio. */
52#if defined(ADC_VER_V5_V90)
53 /* On devices STM32H72xx and STM32H73xx, this parameter can be a value from 1 to 1023 for ADC1/2 or a value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/
54#else
55 /*This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
56#endif
57
58 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
59 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
60
61 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
62 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
63
64 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
65 The oversampling is either temporary stopped or reset upon an injected
66 sequence interruption.
67 If oversampling is enabled on both regular and injected groups, this parameter
68 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
69 (the oversampling buffer is zeroed during injection sequence).
70 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
71
72} ADC_OversamplingTypeDef;
73
74/**
75 * @brief Structure definition of ADC instance and ADC group regular.
76 * @note Parameters of this structure are shared within 2 scopes:
77 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
78 * ScanConvMode, EOCSelection, LowPowerAutoWait.
79 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
80 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
81 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
82 * ADC state can be either:
83 * - For all parameters: ADC disabled
84 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
85 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
86 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
87 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
88 * (which fulfills the ADC state condition) on the fly).
89 */
90typedef struct
91{
92 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
93 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
94 Note: The ADC clock configuration is common to all ADC instances.
95 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
96 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
97 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
98 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
99 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
100 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
101 Note: This parameter can be modified only if all ADC instances are disabled. */
102
103 uint32_t Resolution; /*!< Configure the ADC resolution.
104 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
105
106#if defined(ADC_VER_V5_V90)
107 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
108 Refer to reference manual for alignments formats versus resolutions.
109 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN
110 This parameter is reserved for ADC3 on devices STM32H72xx and STM32H73xx*/
111#endif
112
113 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
114 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
115 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
116 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
117 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
118 Scan direction is upward: from rank 1 to rank 'n'.
119 This parameter can be a value of @ref ADC_Scan_mode */
120
121 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
122 This parameter can be a value of @ref ADC_EOCSelection. */
123
124 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
125 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
126 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
127 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
128 for low frequency applications.
129 This parameter can be set to ENABLE or DISABLE.
130 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
131 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
132 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
133 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,
134 use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
135
136 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
137 after the first ADC conversion start trigger occurred (software start or external trigger).
138 This parameter can be set to ENABLE or DISABLE. */
139
140 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
141 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
142 This parameter must be a number between Min_Data = 1 and Max_Data = 16.
143 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
144 continuous mode or external trigger that could launch a conversion). */
145
146 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
147 (main sequence subdivided in successive parts).
148 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
149 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
150 This parameter can be set to ENABLE or DISABLE. */
151
152 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
153 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
154 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
155
156 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
157 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
158 This parameter can be a value of @ref ADC_regular_external_trigger_source.
159 Caution: external trigger source is common to all ADC instances. */
160
161 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
162 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
163 This parameter can be a value of @ref ADC_regular_external_trigger_edge */
164
165 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register.
166 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
167 This parameter can be a value of @ref ADC_ConversionDataManagement.
168 Note: This parameter must be modified when no conversion is on going on both regular and injected groups
169 (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).*/
170#if defined(ADC_VER_V5_V90)
171 /*Note: On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */
172
173 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
174 This parameter can be a value of @ref ADC_regular_sampling_mode.
175 Note:
176 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */
177
178 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
179 or in continuous mode (DMA transfer unlimited, whatever number of conversions).
180 This parameter can be set to ENABLE or DISABLE.
181 Notes:
182 - In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
183 - Specific to ADC3 only on devices STM32H72xx and STM32H73xx */
184#endif
185
186 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
187 This parameter applies to ADC group regular only.
188 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
189 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
190 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
191 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
192 Note: Error reporting with respect to the conversion mode:
193 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
194 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
195 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
196
197 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
198 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
199 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
200 This parameter can be set to ENABLE or DISABLE.
201 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
202
203 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
204 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
205
206} ADC_InitTypeDef;
207
208/**
209 * @brief Structure definition of ADC channel for regular group
210 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
211 * ADC state can be either:
212 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
213 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
214 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
215 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
216 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
217 * on the fly).
218 */
219typedef struct
220{
221 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
222 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
223 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
224
225 uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
226 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
227 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
228 the new channel setting (or parameter number of conversions adjusted) */
229
230 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
231 Unit: ADC clock cycles
232 Conversion time is the addition of sampling time and processing time
233 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
234 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
235 Caution: This parameter applies to a channel that can be used into regular and/or injected group.
236 It overwrites the last setting.
237 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
238 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
239 Refer to device datasheet for timings values. */
240
241 uint32_t SingleDiff; /*!< Select single-ended or differential input.
242 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
243 Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
244 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
245 Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
246 It overwrites the last setting.
247 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
248 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
249 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
250 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
251 of another parameter update on the fly) */
252
253 uint32_t OffsetNumber; /*!< Select the offset number
254 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
255 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
256
257 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
258 Offset value must be a positive number.
259 Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used).
260 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024).
261 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
262 without continuous mode or external trigger that could launch a conversion). */
263
264 FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
265 This parameter is applied only for 16-bit or 8-bit resolution.
266 This parameter can be set to ENABLE or DISABLE.*/
267#if defined(ADC_VER_V5_V90)
268 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
269 This parameter can be a value of @ref ADCEx_OffsetSign.
270 Note:
271 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
272 without continuous mode or external trigger that could launch a conversion).
273 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
274 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
275 This parameter value can be ENABLE or DISABLE.
276 Note:
277 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
278 without continuous mode or external trigger that could launch a conversion).
279 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
280#endif
281 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
282 This parameter is applied only for 16-bit or 8-bit resolution.
283 This parameter can be set to ENABLE or DISABLE. */
284
285} ADC_ChannelConfTypeDef;
286
287/**
288 * @brief Structure definition of ADC analog watchdog
289 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
290 * ADC state can be either:
291 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
292 */
293typedef struct
294{
295 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
296 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
297 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
298 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
299
300 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
301 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
302 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
303 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
304
305 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
306 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
307 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
308 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
309
310 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
311 This parameter can be set to ENABLE or DISABLE */
312
313 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
314 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
315 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
316 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
317 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
318 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
319 impacted: the comparison of analog watchdog thresholds is done
320 on oversampling intermediate computation (after ratio, before shift
321 application): intermediate register bitfield [32:7] (26 most significant bits). */
322
323 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
324 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
325 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
326 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
327 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
328 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
329 impacted: the comparison of analog watchdog thresholds is done
330 on oversampling intermediate computation (after ratio, before shift
331 application): intermediate register bitfield [32:7] (26 most significant bits). */
332#if defined(ADC_VER_V5_V90)
333 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
334 Before setting flag or raising interrupt, analog watchdog can wait to have several
335 consecutive out-of-window samples. This parameter allows to configure this number.
336 This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE.
337 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. */
338#endif
339} ADC_AnalogWDGConfTypeDef;
340
341/**
342 * @brief ADC group injected contexts queue configuration
343 * @note Structure intended to be used only through structure "ADC_HandleTypeDef"
344 */
345typedef struct
346{
347 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
348 HAL_ADCEx_InjectedConfigChannel() call to finally initialize
349 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
350
351 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
352} ADC_InjectionConfigTypeDef;
353
354/** @defgroup ADC_States ADC States
355 * @{
356 */
357
358/**
359 * @brief HAL ADC state machine: ADC states definition (bitfields)
360 * @note ADC state machine is managed by bitfields, state must be compared
361 * with bit by bit.
362 * For example:
363 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
364 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
365 */
366/* States of ADC global scope */
367#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
368#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
369#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
370#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
371
372/* States of ADC errors */
373#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
374#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
375#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
376
377/* States of ADC group regular */
378#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
379 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
380#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
381#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
382#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
383
384/* States of ADC group injected */
385#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
386 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
387#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
388#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
389
390/* States of ADC analog watchdogs */
391#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
392#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
393#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
394
395/* States of ADC multi-mode */
396#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
397
398/**
399 * @}
400 */
401
402/**
403 * @brief ADC handle Structure definition
404 */
405#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
406typedef struct __ADC_HandleTypeDef
407#else
408typedef struct
409#endif
410{
411 ADC_TypeDef *Instance; /*!< Register base address */
412 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
413 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
414 HAL_LockTypeDef Lock; /*!< ADC locking object */
415 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
416 __IO uint32_t ErrorCode; /*!< ADC Error code */
417 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
418#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
419 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
420 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
421 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
422 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
423 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
424 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
425 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
426 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
427 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
428 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
429 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
430#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
431} ADC_HandleTypeDef;
432
433#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
434/**
435 * @brief HAL ADC Callback ID enumeration definition
436 */
437typedef enum
438{
439 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
440 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
441 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
442 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
443 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
444 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
445 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
446 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
447 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
448 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
449 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
450} HAL_ADC_CallbackIDTypeDef;
451
452/**
453 * @brief HAL ADC Callback pointer definition
454 */
455typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
456
457#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
458
459/**
460 * @}
461 */
462
463
464/* Exported constants --------------------------------------------------------*/
465
466/** @defgroup ADC_Exported_Constants ADC Exported Constants
467 * @{
468 */
469
470/** @defgroup ADC_Error_Code ADC Error Code
471 * @{
472 */
473#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
474#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
475 enable/disable, erroneous state, ...) */
476#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
477#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
478#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
479#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
480#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
481#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
482/**
483 * @}
484 */
485
486/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
487 * @{
488 */
489#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
490#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
491#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
492
493#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
494#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
495#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
496#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
497#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
498#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
499#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
500#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
501#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
502#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
503#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
504#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
505/**
506 * @}
507 */
508
509/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
510 * @{
511 */
512#define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
513#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
514#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
515#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
516#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
517
518#if defined (ADC_VER_V5_X)
519#define ADC_RESOLUTION_14B_OPT (LL_ADC_RESOLUTION_14B_OPT) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */
520#define ADC_RESOLUTION_12B_OPT (LL_ADC_RESOLUTION_12B_OPT) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */
521#endif
522
523#if defined(ADC_VER_V5_V90)
524#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
525#endif /* ADC_VER_V5_V90 */
526/**
527 * @}
528 */
529
530#if defined(ADC_VER_V5_V90)
531/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
532 * @{
533 */
534#define ADC3_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
535#define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
536/**
537 * @}
538 */
539#endif
540
541/** @defgroup ADC_Scan_mode ADC sequencer scan mode
542 * @{
543 */
544#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
545#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
546/**
547 * @}
548 */
549
550/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
551 * @{
552 */
553/* ADC group regular trigger sources for all ADC instances */
554#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
555#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
556#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
557#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
558#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
559#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
560#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
561#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
562#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
563#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
564#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
565#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
566#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
567#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
568#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
569#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
570#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
571#define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
572#define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */
573#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
574#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
575#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
576#if defined(TIM23)
577#define ADC_EXTERNALTRIG_T23_TRGO (LL_ADC_REG_TRIG_EXT_TIM23_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
578#endif /*TIM23*/
579#if defined(TIM24)
580#define ADC_EXTERNALTRIG_T24_TRGO (LL_ADC_REG_TRIG_EXT_TIM24_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
581#endif /*TIM24*/
582/**
583 * @}
584 */
585
586/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
587 * @{
588 */
589#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
590#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
591#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
592#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
593/**
594 * @}
595 */
596#if defined(ADC_VER_V5_V90)
597/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
598 * @{
599 */
600#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
601#define ADC_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
602 Notes:
603 - First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME)
604 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
605#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
606 Trigger rising edge = start sampling
607 Trigger falling edge = stop sampling and start conversion
608 Note: Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
609/**
610 * @}
611 */
612#endif
613
614/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
615 * @{
616 */
617#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
618#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
619/**
620 * @}
621 */
622
623/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
624 * @{
625 */
626#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
627#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
628/**
629 * @}
630 */
631
632/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
633 * @{
634 */
635#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
636#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
637#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
638#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
639#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
640#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
641#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
642#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
643#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
644#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
645#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
646#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
647#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
648#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
649#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
650#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
651/**
652 * @}
653 */
654
655/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
656 * @{
657 */
658#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
659#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
660#define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
661#define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
662#define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
663#define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
664#define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
665#define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
666/**
667 * @}
668 */
669#if defined(ADC_VER_V5_V90)
670/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
671 * @{
672 */
673#define ADC3_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
674#define ADC3_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
675#define ADC3_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
676#define ADC3_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
677#define ADC3_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
678#define ADC3_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
679#define ADC3_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
680#define ADC3_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
681#define ADC3_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously.
682 On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
683/**
684 * @}
685 */
686#endif
687
688/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
689 * @{
690 */
691#define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
692#define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)
693/**
694 * @}
695 */
696
697/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
698 * @{
699 */
700/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
701/* all ADC instances (refer to Reference Manual). */
702#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
703#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
704#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
705#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
706#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
707#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
708#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
709#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
710#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
711#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
712#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
713#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
714#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
715#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
716#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
717#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
718#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
719#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
720#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
721#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
722#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */
723#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */
724#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */
725#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
726#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
727#if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2)
728#define ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
729#endif
730/**
731 * @}
732 */
733
734/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
735 * @{
736 */
737#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */
738#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
739#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
740#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
741/**
742 * @}
743 */
744/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
745 * @{
746 */
747#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
748#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
749#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
750/**
751 * @}
752 */
753
754#if defined(ADC_VER_V5_V90)
755/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
756 * @{
757 */
758#define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
759#define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
760#define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
761#define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
762#define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
763#define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
764#define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
765#define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
766/**
767 * @}
768 */
769#endif
770
771/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
772 * @{
773 */
774#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
775#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
776#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
777#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
778#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
779#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
780#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
781/**
782 * @}
783 */
784#if defined(ADC_VER_V5_V90)
785/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
786 * @{
787 */
788#define ADC3_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
789#define ADC3_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
790#define ADC3_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
791#define ADC3_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
792#define ADC3_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
793#define ADC3_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
794#define ADC3_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
795#define ADC3_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
796#define ADC3_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
797#define ADC3_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
798/**
799 * @}
800 */
801#endif
802
803/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
804 * @{
805 */
806#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
807#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
808#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
809#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
810#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
811#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
812#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
813#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
814#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
815#define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
816#define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
817#define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
818/**
819 * @}
820 */
821
822/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift
823 * @{
824 */
825#define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */
826#define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */
827#define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */
828#define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */
829#define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */
830#define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */
831#define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */
832#define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */
833#define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */
834#define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */
835#define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */
836#define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */
837#define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */
838#define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */
839#define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */
840#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */
841/**
842 * @}
843 */
844
845/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
846 * @{
847 */
848#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
849#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
850/**
851 * @}
852 */
853
854/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
855 * @{
856 */
857#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
858#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
859/**
860 * @}
861 */
862
863
864/** @defgroup ADC_Event_type ADC Event type
865 * @{
866 */
867#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
868#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
869#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
870#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
871#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
872#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
873/**
874 * @}
875 */
876#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
877
878/** @defgroup ADC_interrupts_definition ADC interrupts definition
879 * @{
880 */
881#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
882#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
883#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
884#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
885#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
886#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
887#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
888#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
889#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
890#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
891#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
892
893#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
894
895/**
896 * @}
897 */
898
899/** @defgroup ADC_flags_definition ADC flags definition
900 * @{
901 */
902#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
903#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
904#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
905#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
906#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
907#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
908#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
909#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
910#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
911#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
912#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
913#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC LDO output voltage ready bit */
914/**
915 * @}
916 */
917
918/**
919 * @}
920 */
921
922/* Private macro -------------------------------------------------------------*/
923
924/** @defgroup ADC_Private_Macros ADC Private Macros
925 * @{
926 */
927/* Macro reserved for internal HAL driver usage, not intended to be used in */
928/* code of final user. */
929
930/**
931 * @brief Verify the ADC data conversion setting.
932 * @param DATA : programmed DATA conversion mode.
933 * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
934 */
935#define IS_ADC_CONVERSIONDATAMGT(DATA) \
936 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \
937 (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \
938 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
939 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
940
941/**
942 * @brief Return resolution bits in CFGR register RES[1:0] field.
943 * @param __HANDLE__ ADC handle
944 * @retval Value of bitfield RES in CFGR register.
945 */
946#define ADC_GET_RESOLUTION(__HANDLE__) \
947 (LL_ADC_GetResolution((__HANDLE__)->Instance))
948
949/**
950 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
951 * @param __HANDLE__ ADC handle
952 * @retval None
953 */
954#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
955
956/**
957 * @brief Verification of ADC state: enabled or disabled.
958 * @param __HANDLE__ ADC handle
959 * @retval SET (ADC enabled) or RESET (ADC disabled)
960 */
961#define ADC_IS_ENABLE(__HANDLE__) \
962 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
963 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
964 ) ? SET : RESET)
965
966/**
967 * @brief Check if conversion is on going on regular group.
968 * @param __HANDLE__ ADC handle
969 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
970 */
971#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
972 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
973
974/**
975 * @brief Check if ADC clock mode is synchronous
976 * @param __HANDLE__: ADC handle
977 * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)
978 */
979#if defined (ADC3)
980#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \
981 (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \
982 ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) \
983 :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL))
984#else
985#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
986
987#endif
988
989/**
990 * @brief Simultaneously clear and set specific bits of the handle State.
991 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
992 * the first parameter is the ADC handle State, the second parameter is the
993 * bit field to clear, the third and last parameter is the bit field to set.
994 * @retval None
995 */
996#define ADC_STATE_CLR_SET MODIFY_REG
997
998/**
999 * @brief Verify that a given value is aligned with the ADC resolution range.
1000 * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits).
1001 * @param __ADC_VALUE__ value checked against the resolution.
1002 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
1003 */
1004#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
1005 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
1006
1007#if defined(ADC_VER_V5_V90)
1008/**
1009 * @brief Verify that a given value is aligned with the ADC resolution range. Applicable for ADC3 on devices STM32H72xx and STM32H73xx.
1010 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
1011 * @param __ADC_VALUE__ value checked against the resolution.
1012 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
1013 */
1014#define IS_ADC3_RANGE(__RESOLUTION__, __ADC_VALUE__) \
1015 ((__ADC_VALUE__) <= __LL_ADC3_DIGITAL_SCALE(__RESOLUTION__))
1016#endif
1017/**
1018 * @brief Verify the length of the scheduled regular conversions group.
1019 * @param __LENGTH__ number of programmed conversions.
1020 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
1021 */
1022#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
1023
1024
1025/**
1026 * @brief Verify the number of scheduled regular conversions in discontinuous mode.
1027 * @param NUMBER number of scheduled regular conversions in discontinuous mode.
1028 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
1029 */
1030#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
1031
1032
1033/**
1034 * @brief Verify the ADC clock setting.
1035 * @param __ADC_CLOCK__ programmed ADC clock.
1036 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
1037 */
1038#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
1039 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
1040 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
1041 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
1042 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
1043 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
1044 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
1045 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
1046 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
1047 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
1048 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
1049 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
1050 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
1051 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
1052 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
1053
1054/**
1055 * @brief Verify the ADC resolution setting.
1056 * @param __RESOLUTION__ programmed ADC resolution.
1057 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
1058 */
1059#if defined(ADC_VER_V5_V90)
1060#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
1061 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
1062 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
1063 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
1064 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
1065 ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
1066#elif defined (ADC_VER_V5_X)
1067#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
1068 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
1069 ((__RESOLUTION__) == ADC_RESOLUTION_14B_OPT) || \
1070 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
1071 ((__RESOLUTION__) == ADC_RESOLUTION_12B_OPT) || \
1072 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
1073 ((__RESOLUTION__) == ADC_RESOLUTION_8B) )
1074#else /* ADC_VER_V5_3 */
1075#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
1076 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
1077 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
1078 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
1079 ((__RESOLUTION__) == ADC_RESOLUTION_8B) )
1080#endif /* ADC_VER_V5_V90*/
1081
1082/**
1083 * @brief Verify the ADC resolution setting when limited to 8 bits.
1084 * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.
1085 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
1086 */
1087#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
1088
1089#if defined(ADC_VER_V5_V90)
1090/**
1091 * @brief Verify the ADC converted data alignment. Applicable for ADC3 on devices STM32H72xx and STM32H73xx.
1092 * @param __ALIGN__ programmed ADC converted data alignment.
1093 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
1094 */
1095#define IS_ADC3_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC3_DATAALIGN_RIGHT) || \
1096 ((__ALIGN__) == ADC3_DATAALIGN_LEFT) )
1097
1098/**
1099 * @brief Verify the ADC regular conversions external trigger.
1100 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
1101 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
1102 */
1103#define IS_ADC3_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
1104 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
1105 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) )
1106
1107#endif
1108
1109/**
1110 * @brief Verify the ADC scan mode.
1111 * @param __SCAN_MODE__ programmed ADC scan mode.
1112 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
1113 */
1114#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
1115 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
1116
1117/**
1118 * @brief Verify the ADC edge trigger setting for regular group.
1119 * @param __EDGE__ programmed ADC edge trigger setting.
1120 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
1121 */
1122#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
1123 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
1124 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
1125 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
1126
1127/**
1128 * @brief Verify the ADC regular conversions external trigger.
1129 * @param __REGTRIG__ programmed ADC regular conversions external trigger.
1130 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
1131 */
1132#if defined(ADC_VER_V5_V90)
1133#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
1134 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
1135 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
1136 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
1137 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
1138 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
1139 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
1140 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
1141 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
1142 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
1143 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
1144 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
1145 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
1146 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
1147 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
1148 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
1149 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
1150 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
1151 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
1152 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
1153 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
1154 ((__REGTRIG__) == ADC_EXTERNALTRIG_T23_TRGO) || \
1155 ((__REGTRIG__) == ADC_EXTERNALTRIG_T24_TRGO) || \
1156 ((__REGTRIG__) == ADC_SOFTWARE_START) )
1157#else
1158#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
1159 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
1160 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
1161 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
1162 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
1163 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
1164 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
1165 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
1166 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
1167 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
1168 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
1169 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
1170 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
1171 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
1172 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
1173 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
1174 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
1175 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
1176 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
1177 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
1178 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
1179 ((__REGTRIG__) == ADC_SOFTWARE_START) )
1180#endif /* ADC_VER_V5_V90*/
1181
1182
1183/**
1184 * @brief Verify the ADC regular conversions check for converted data availability.
1185 * @param __EOC_SELECTION__ converted data availability check.
1186 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
1187 */
1188#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
1189 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
1190
1191/**
1192 * @brief Verify the ADC regular conversions overrun handling.
1193 * @param __OVR__ ADC regular conversions overrun handling.
1194 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
1195 */
1196#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
1197 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
1198
1199/**
1200 * @brief Verify the ADC conversions sampling time.
1201 * @param __TIME__ ADC conversions sampling time.
1202 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
1203 */
1204#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
1205 ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
1206 ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \
1207 ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \
1208 ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \
1209 ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \
1210 ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
1211 ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) )
1212
1213/**
1214 * @brief Verify the ADC regular channel setting.
1215 * @param __CHANNEL__ programmed ADC regular channel.
1216 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
1217 */
1218#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
1219 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
1220 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
1221 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
1222 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
1223 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
1224 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
1225 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
1226 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
1227 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
1228 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
1229 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
1230 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
1231 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
1232 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
1233 ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
1234
1235/**
1236 * @}
1237 */
1238
1239
1240/* Private constants ---------------------------------------------------------*/
1241
1242/** @defgroup ADC_Private_Constants ADC Private Constants
1243 * @{
1244 */
1245
1246/* Fixed timeout values for ADC conversion (including sampling time) */
1247/* Maximum sampling time is 810.5 ADC clock cycle */
1248/* Maximum conversion time is 16.5 + Maximum sampling time */
1249/* or 16.5 + 810.5 = 827 ADC clock cycles */
1250/* Minimum ADC Clock frequency is 0.35 MHz */
1251/* Maximum conversion time is */
1252/* 827 / 0.35 MHz = 2.36 ms */
1253
1254#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
1255
1256/* Delay for temperature sensor stabilization time. */
1257/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
1258/* Unit: us */
1259#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
1260
1261/* Delay for ADC voltage regulator startup time */
1262/* Maximum delay is 10 microseconds */
1263/* (refer device RM, parameter Tadcvreg_stup). */
1264#define ADC_STAB_DELAY_US (10UL) /*!< ADC voltage regulator startup time */
1265
1266/**
1267 * @}
1268 */
1269
1270/* Exported macro ------------------------------------------------------------*/
1271
1272/** @defgroup ADC_Exported_Macros ADC Exported Macros
1273 * @{
1274 */
1275/* Macro for internal HAL driver usage, and possibly can be used into code of */
1276/* final user. */
1277
1278/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
1279 * @{
1280 */
1281
1282/** @brief Reset ADC handle state.
1283 * @param __HANDLE__ ADC handle
1284 * @retval None
1285 */
1286#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1287#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1288 do{ \
1289 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
1290 (__HANDLE__)->MspInitCallback = NULL; \
1291 (__HANDLE__)->MspDeInitCallback = NULL; \
1292 } while(0)
1293#else
1294#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1295 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
1296#endif
1297
1298/**
1299 * @brief Enable ADC interrupt.
1300 * @param __HANDLE__ ADC handle
1301 * @param __INTERRUPT__ ADC Interrupt
1302 * This parameter can be one of the following values:
1303 * @arg @ref ADC_IT_RDY ADC Ready interrupt source
1304 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1305 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1306 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1307 * @arg @ref ADC_IT_OVR ADC overrun interrupt source
1308 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
1309 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
1310 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1311 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1312 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1313 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
1314 * @retval None
1315 */
1316#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1317 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
1318
1319/**
1320 * @brief Disable ADC interrupt.
1321 * @param __HANDLE__ ADC handle
1322 * @param __INTERRUPT__ ADC Interrupt
1323 * This parameter can be one of the following values:
1324 * @arg @ref ADC_IT_RDY ADC Ready interrupt source
1325 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1326 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1327 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1328 * @arg @ref ADC_IT_OVR ADC overrun interrupt source
1329 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
1330 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
1331 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1332 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1333 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1334 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
1335 * @retval None
1336 */
1337#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
1338 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
1339
1340/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
1341 * @param __HANDLE__ ADC handle
1342 * @param __INTERRUPT__ ADC interrupt source to check
1343 * This parameter can be one of the following values:
1344 * @arg @ref ADC_IT_RDY ADC Ready interrupt source
1345 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1346 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1347 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1348 * @arg @ref ADC_IT_OVR ADC overrun interrupt source
1349 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
1350 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
1351 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1352 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1353 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1354 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
1355 * @retval State of interruption (SET or RESET)
1356 */
1357#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
1358 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
1359
1360/**
1361 * @brief Check whether the specified ADC flag is set or not.
1362 * @param __HANDLE__ ADC handle
1363 * @param __FLAG__ ADC flag
1364 * This parameter can be one of the following values:
1365 * @arg @ref ADC_FLAG_RDY ADC Ready flag
1366 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
1367 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
1368 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
1369 * @arg @ref ADC_FLAG_OVR ADC overrun flag
1370 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
1371 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
1372 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
1373 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
1374 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
1375 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
1376 * @arg @ref ADC_FLAG_LDORDY ADC LDO output voltage ready bit.
1377 * @retval State of flag (TRUE or FALSE).
1378 */
1379#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
1380 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
1381
1382/**
1383 * @brief Clear the specified ADC flag.
1384 * @param __HANDLE__ ADC handle
1385 * @param __FLAG__ ADC flag
1386 * This parameter can be one of the following values:
1387 * @arg @ref ADC_FLAG_RDY ADC Ready flag
1388 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
1389 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
1390 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
1391 * @arg @ref ADC_FLAG_OVR ADC overrun flag
1392 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
1393 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
1394 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
1395 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
1396 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
1397 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
1398 * @retval None
1399 */
1400/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
1401#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1402 (((__HANDLE__)->Instance->ISR) = (__FLAG__))
1403
1404/**
1405 * @}
1406 */
1407
1408/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
1409 * @{
1410 */
1411
1412/**
1413 * @brief Helper macro to get ADC channel number in decimal format
1414 * from literals ADC_CHANNEL_x.
1415 * @note Example:
1416 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
1417 * will return decimal number "4".
1418 * @note The input can be a value from functions where a channel
1419 * number is returned, either defined with number
1420 * or with bitfield (only one bit must be set).
1421 * @param __CHANNEL__ This parameter can be one of the following values:
1422 * @arg @ref ADC_CHANNEL_0 (3)
1423 * @arg @ref ADC_CHANNEL_1 (3)
1424 * @arg @ref ADC_CHANNEL_2 (3)
1425 * @arg @ref ADC_CHANNEL_3 (3)
1426 * @arg @ref ADC_CHANNEL_4 (3)
1427 * @arg @ref ADC_CHANNEL_5 (3)
1428 * @arg @ref ADC_CHANNEL_6
1429 * @arg @ref ADC_CHANNEL_7
1430 * @arg @ref ADC_CHANNEL_8
1431 * @arg @ref ADC_CHANNEL_9
1432 * @arg @ref ADC_CHANNEL_10
1433 * @arg @ref ADC_CHANNEL_11
1434 * @arg @ref ADC_CHANNEL_12
1435 * @arg @ref ADC_CHANNEL_13
1436 * @arg @ref ADC_CHANNEL_14
1437 * @arg @ref ADC_CHANNEL_15
1438 * @arg @ref ADC_CHANNEL_16
1439 * @arg @ref ADC_CHANNEL_17
1440 * @arg @ref ADC_CHANNEL_18
1441 * @arg @ref ADC_CHANNEL_VREFINT (1)
1442 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
1443 * @arg @ref ADC_CHANNEL_VBAT (1)
1444 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
1445 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
1446 *
1447 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1448 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1449 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1450 * Other channels are slow channels (conversion rate: refer to reference manual).
1451 * @retval Value between Min_Data=0 and Max_Data=18
1452 */
1453#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1454 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
1455
1456/**
1457 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
1458 * from number in decimal format.
1459 * @note Example:
1460 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1461 * will return a data equivalent to "ADC_CHANNEL_4".
1462 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1463 * @retval Returned value can be one of the following values:
1464 * @arg @ref ADC_CHANNEL_0 (3)
1465 * @arg @ref ADC_CHANNEL_1 (3)
1466 * @arg @ref ADC_CHANNEL_2 (3)
1467 * @arg @ref ADC_CHANNEL_3 (3)
1468 * @arg @ref ADC_CHANNEL_4 (3)
1469 * @arg @ref ADC_CHANNEL_5 (3)
1470 * @arg @ref ADC_CHANNEL_6
1471 * @arg @ref ADC_CHANNEL_7
1472 * @arg @ref ADC_CHANNEL_8
1473 * @arg @ref ADC_CHANNEL_9
1474 * @arg @ref ADC_CHANNEL_10
1475 * @arg @ref ADC_CHANNEL_11
1476 * @arg @ref ADC_CHANNEL_12
1477 * @arg @ref ADC_CHANNEL_13
1478 * @arg @ref ADC_CHANNEL_14
1479 * @arg @ref ADC_CHANNEL_15
1480 * @arg @ref ADC_CHANNEL_16
1481 * @arg @ref ADC_CHANNEL_17
1482 * @arg @ref ADC_CHANNEL_18
1483 * @arg @ref ADC_CHANNEL_VREFINT (1)
1484 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
1485 * @arg @ref ADC_CHANNEL_VBAT (1)
1486 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
1487 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
1488 *
1489 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1490 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1491 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1492 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1493 * (1, 2) For ADC channel read back from ADC register,
1494 * comparison with internal channel parameter to be done
1495 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1496 */
1497#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1498 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
1499
1500/**
1501 * @brief Helper macro to determine whether the selected channel
1502 * corresponds to literal definitions of driver.
1503 * @note The different literal definitions of ADC channels are:
1504 * - ADC internal channel:
1505 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
1506 * - ADC external channel (channel connected to a GPIO pin):
1507 * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
1508 * @note The channel parameter must be a value defined from literal
1509 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1510 * ADC_CHANNEL_TEMPSENSOR, ...),
1511 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
1512 * must not be a value from functions where a channel number is
1513 * returned from ADC registers,
1514 * because internal and external channels share the same channel
1515 * number in ADC registers. The differentiation is made only with
1516 * parameters definitions of driver.
1517 * @param __CHANNEL__ This parameter can be one of the following values:
1518 * @arg @ref ADC_CHANNEL_0 (3)
1519 * @arg @ref ADC_CHANNEL_1 (3)
1520 * @arg @ref ADC_CHANNEL_2 (3)
1521 * @arg @ref ADC_CHANNEL_3 (3)
1522 * @arg @ref ADC_CHANNEL_4 (3)
1523 * @arg @ref ADC_CHANNEL_5 (3)
1524 * @arg @ref ADC_CHANNEL_6
1525 * @arg @ref ADC_CHANNEL_7
1526 * @arg @ref ADC_CHANNEL_8
1527 * @arg @ref ADC_CHANNEL_9
1528 * @arg @ref ADC_CHANNEL_10
1529 * @arg @ref ADC_CHANNEL_11
1530 * @arg @ref ADC_CHANNEL_12
1531 * @arg @ref ADC_CHANNEL_13
1532 * @arg @ref ADC_CHANNEL_14
1533 * @arg @ref ADC_CHANNEL_15
1534 * @arg @ref ADC_CHANNEL_16
1535 * @arg @ref ADC_CHANNEL_17
1536 * @arg @ref ADC_CHANNEL_18
1537 * @arg @ref ADC_CHANNEL_VREFINT (1)
1538 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
1539 * @arg @ref ADC_CHANNEL_VBAT (1)
1540 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
1541 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
1542 *
1543 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1544 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1545 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1546 * Other channels are slow channels (conversion rate: refer to reference manual).
1547 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1548 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1549 */
1550#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1551 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
1552
1553/**
1554 * @brief Helper macro to convert a channel defined from parameter
1555 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1556 * ADC_CHANNEL_TEMPSENSOR, ...),
1557 * to its equivalent parameter definition of a ADC external channel
1558 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
1559 * @note The channel parameter can be, additionally to a value
1560 * defined from parameter definition of a ADC internal channel
1561 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
1562 * a value defined from parameter definition of
1563 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
1564 * or a value from functions where a channel number is returned
1565 * from ADC registers.
1566 * @param __CHANNEL__ This parameter can be one of the following values:
1567 * @arg @ref ADC_CHANNEL_0 (3)
1568 * @arg @ref ADC_CHANNEL_1 (3)
1569 * @arg @ref ADC_CHANNEL_2 (3)
1570 * @arg @ref ADC_CHANNEL_3 (3)
1571 * @arg @ref ADC_CHANNEL_4 (3)
1572 * @arg @ref ADC_CHANNEL_5 (3)
1573 * @arg @ref ADC_CHANNEL_6
1574 * @arg @ref ADC_CHANNEL_7
1575 * @arg @ref ADC_CHANNEL_8
1576 * @arg @ref ADC_CHANNEL_9
1577 * @arg @ref ADC_CHANNEL_10
1578 * @arg @ref ADC_CHANNEL_11
1579 * @arg @ref ADC_CHANNEL_12
1580 * @arg @ref ADC_CHANNEL_13
1581 * @arg @ref ADC_CHANNEL_14
1582 * @arg @ref ADC_CHANNEL_15
1583 * @arg @ref ADC_CHANNEL_16
1584 * @arg @ref ADC_CHANNEL_17
1585 * @arg @ref ADC_CHANNEL_18
1586 * @arg @ref ADC_CHANNEL_VREFINT (1)
1587 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
1588 * @arg @ref ADC_CHANNEL_VBAT (1)
1589 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
1590 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
1591 *
1592 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1593 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1594 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1595 * Other channels are slow channels (conversion rate: refer to reference manual).
1596 * @retval Returned value can be one of the following values:
1597 * @arg @ref ADC_CHANNEL_0
1598 * @arg @ref ADC_CHANNEL_1
1599 * @arg @ref ADC_CHANNEL_2
1600 * @arg @ref ADC_CHANNEL_3
1601 * @arg @ref ADC_CHANNEL_4
1602 * @arg @ref ADC_CHANNEL_5
1603 * @arg @ref ADC_CHANNEL_6
1604 * @arg @ref ADC_CHANNEL_7
1605 * @arg @ref ADC_CHANNEL_8
1606 * @arg @ref ADC_CHANNEL_9
1607 * @arg @ref ADC_CHANNEL_10
1608 * @arg @ref ADC_CHANNEL_11
1609 * @arg @ref ADC_CHANNEL_12
1610 * @arg @ref ADC_CHANNEL_13
1611 * @arg @ref ADC_CHANNEL_14
1612 * @arg @ref ADC_CHANNEL_15
1613 * @arg @ref ADC_CHANNEL_16
1614 * @arg @ref ADC_CHANNEL_17
1615 * @arg @ref ADC_CHANNEL_18
1616 */
1617#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1618 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
1619
1620/**
1621 * @brief Helper macro to determine whether the internal channel
1622 * selected is available on the ADC instance selected.
1623 * @note The channel parameter must be a value defined from parameter
1624 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1625 * ADC_CHANNEL_TEMPSENSOR, ...),
1626 * must not be a value defined from parameter definition of
1627 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
1628 * or a value from functions where a channel number is
1629 * returned from ADC registers,
1630 * because internal and external channels share the same channel
1631 * number in ADC registers. The differentiation is made only with
1632 * parameters definitions of driver.
1633 * @param __ADC_INSTANCE__ ADC instance
1634 * @param __CHANNEL__ This parameter can be one of the following values:
1635 * @arg @ref ADC_CHANNEL_VREFINT (1)
1636 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
1637 * @arg @ref ADC_CHANNEL_VBAT (1)
1638 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
1639 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
1640 *
1641 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1642 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
1643 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1644 * Value "1" if the internal channel selected is available on the ADC instance selected.
1645 */
1646#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1647 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
1648
1649/**
1650 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1651 * or ADC slave from raw value with both ADC conversion data concatenated.
1652 * @note This macro is intended to be used when multimode transfer by DMA
1653 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1654 * In this case the transferred data need to processed with this macro
1655 * to separate the conversion data of ADC master and ADC slave.
1656 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1657 * @arg @ref LL_ADC_MULTI_MASTER
1658 * @arg @ref LL_ADC_MULTI_SLAVE
1659 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1660 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1661 */
1662#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1663 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
1664
1665/**
1666 * @brief Helper macro to select the ADC common instance
1667 * to which is belonging the selected ADC instance.
1668 * @note ADC common register instance can be used for:
1669 * - Set parameters common to several ADC instances
1670 * - Multimode (for devices with several ADC instances)
1671 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1672 * @param __ADCx__ ADC instance
1673 * @retval ADC common register instance
1674 */
1675#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
1676 __LL_ADC_COMMON_INSTANCE((__ADCx__))
1677
1678/**
1679 * @brief Helper macro to check if all ADC instances sharing the same
1680 * ADC common instance are disabled.
1681 * @note This check is required by functions with setting conditioned to
1682 * ADC state:
1683 * All ADC instances of the ADC common group must be disabled.
1684 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1685 * @note On devices with only 1 ADC common instance, parameter of this macro
1686 * is useless and can be ignored (parameter kept for compatibility
1687 * with devices featuring several ADC common instances).
1688 * @param __ADCXY_COMMON__ ADC common instance
1689 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1690 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1691 * are disabled.
1692 * Value "1" if at least one ADC instance sharing the same ADC common instance
1693 * is enabled.
1694 */
1695#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1696 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
1697
1698/**
1699 * @brief Helper macro to define the ADC conversion data full-scale digital
1700 * value corresponding to the selected ADC resolution.
1701 * @note ADC conversion data full-scale corresponds to voltage range
1702 * determined by analog voltage references Vref+ and Vref-
1703 * (refer to reference manual).
1704 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1705 * @arg @ref ADC_RESOLUTION_16B
1706 * @arg @ref ADC_RESOLUTION_14B
1707 * @arg @ref ADC_RESOLUTION_12B
1708 * @arg @ref ADC_RESOLUTION_10B
1709 * @arg @ref ADC_RESOLUTION_8B
1710 * @retval ADC conversion data full-scale digital value
1711 */
1712#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1713 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
1714
1715/**
1716 * @brief Helper macro to convert the ADC conversion data from
1717 * a resolution to another resolution.
1718 * @param __DATA__ ADC conversion data to be converted
1719 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1720 * This parameter can be one of the following values:
1721 * @arg @ref ADC_RESOLUTION_16B
1722 * @arg @ref ADC_RESOLUTION_14B
1723 * @arg @ref ADC_RESOLUTION_12B
1724 * @arg @ref ADC_RESOLUTION_10B
1725 * @arg @ref ADC_RESOLUTION_8B
1726 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1727 * This parameter can be one of the following values:
1728 * @arg @ref ADC_RESOLUTION_16B
1729 * @arg @ref ADC_RESOLUTION_14B
1730 * @arg @ref ADC_RESOLUTION_12B
1731 * @arg @ref ADC_RESOLUTION_10B
1732 * @arg @ref ADC_RESOLUTION_8B
1733 * @retval ADC conversion data to the requested resolution
1734 */
1735#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1736 __ADC_RESOLUTION_CURRENT__,\
1737 __ADC_RESOLUTION_TARGET__) \
1738 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
1739 (__ADC_RESOLUTION_CURRENT__),\
1740 (__ADC_RESOLUTION_TARGET__))
1741
1742/**
1743 * @brief Helper macro to calculate the voltage (unit: mVolt)
1744 * corresponding to a ADC conversion data (unit: digital value).
1745 * @note Analog reference voltage (Vref+) must be either known from
1746 * user board environment or can be calculated using ADC measurement
1747 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1748 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1749 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1750 * (unit: digital value).
1751 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1752 * @arg @ref ADC_RESOLUTION_16B
1753 * @arg @ref ADC_RESOLUTION_14B
1754 * @arg @ref ADC_RESOLUTION_12B
1755 * @arg @ref ADC_RESOLUTION_10B
1756 * @arg @ref ADC_RESOLUTION_8B
1757 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1758 */
1759#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1760 __ADC_DATA__,\
1761 __ADC_RESOLUTION__) \
1762 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
1763 (__ADC_DATA__),\
1764 (__ADC_RESOLUTION__))
1765
1766/**
1767 * @brief Helper macro to calculate analog reference voltage (Vref+)
1768 * (unit: mVolt) from ADC conversion data of internal voltage
1769 * reference VrefInt.
1770 * @note Computation is using VrefInt calibration value
1771 * stored in system memory for each device during production.
1772 * @note This voltage depends on user board environment: voltage level
1773 * connected to pin Vref+.
1774 * On devices with small package, the pin Vref+ is not present
1775 * and internally bonded to pin Vdda.
1776 * @note On this STM32 series, calibration data of internal voltage reference
1777 * VrefInt corresponds to a resolution of 12 bits,
1778 * this is the recommended ADC resolution to convert voltage of
1779 * internal voltage reference VrefInt.
1780 * Otherwise, this macro performs the processing to scale
1781 * ADC conversion data to 12 bits.
1782 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1783 * of internal voltage reference VrefInt (unit: digital value).
1784 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1785 * @arg @ref ADC_RESOLUTION_16B
1786 * @arg @ref ADC_RESOLUTION_14B
1787 * @arg @ref ADC_RESOLUTION_12B
1788 * @arg @ref ADC_RESOLUTION_10B
1789 * @arg @ref ADC_RESOLUTION_8B
1790 * @retval Analog reference voltage (unit: mV)
1791 */
1792#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1793 __ADC_RESOLUTION__) \
1794 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
1795 (__ADC_RESOLUTION__))
1796
1797/**
1798 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1799 * from ADC conversion data of internal temperature sensor.
1800 * @note Computation is using temperature sensor calibration values
1801 * stored in system memory for each device during production.
1802 * @note Calculation formula:
1803 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1804 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1805 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1806 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1807 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1808 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1809 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1810 * TEMP_DEGC_CAL1 (calibrated in factory)
1811 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1812 * TEMP_DEGC_CAL2 (calibrated in factory)
1813 * Caution: Calculation relevancy under reserve that calibration
1814 * parameters are correct (address and data).
1815 * To calculate temperature using temperature sensor
1816 * datasheet typical values (generic values less, therefore
1817 * less accurate than calibrated values),
1818 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1819 * @note As calculation input, the analog reference voltage (Vref+) must be
1820 * defined as it impacts the ADC LSB equivalent voltage.
1821 * @note Analog reference voltage (Vref+) must be either known from
1822 * user board environment or can be calculated using ADC measurement
1823 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1824 * @note On this STM32 series, calibration data of temperature sensor
1825 * corresponds to a resolution of 12 bits,
1826 * this is the recommended ADC resolution to convert voltage of
1827 * temperature sensor.
1828 * Otherwise, this macro performs the processing to scale
1829 * ADC conversion data to 12 bits.
1830 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1831 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1832 * temperature sensor (unit: digital value).
1833 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1834 * sensor voltage has been measured.
1835 * This parameter can be one of the following values:
1836 * @arg @ref ADC_RESOLUTION_16B
1837 * @arg @ref ADC_RESOLUTION_14B
1838 * @arg @ref ADC_RESOLUTION_12B
1839 * @arg @ref ADC_RESOLUTION_10B
1840 * @arg @ref ADC_RESOLUTION_8B
1841 * @retval Temperature (unit: degree Celsius)
1842 */
1843#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1844 __TEMPSENSOR_ADC_DATA__,\
1845 __ADC_RESOLUTION__) \
1846 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
1847 (__TEMPSENSOR_ADC_DATA__),\
1848 (__ADC_RESOLUTION__))
1849
1850/**
1851 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1852 * from ADC conversion data of internal temperature sensor.
1853 * @note Computation is using temperature sensor typical values
1854 * (refer to device datasheet).
1855 * @note Calculation formula:
1856 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1857 * / Avg_Slope + CALx_TEMP
1858 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1859 * (unit: digital value)
1860 * Avg_Slope = temperature sensor slope
1861 * (unit: uV/Degree Celsius)
1862 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1863 * temperature CALx_TEMP (unit: mV)
1864 * Caution: Calculation relevancy under reserve the temperature sensor
1865 * of the current device has characteristics in line with
1866 * datasheet typical values.
1867 * If temperature sensor calibration values are available on
1868 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1869 * temperature calculation will be more accurate using
1870 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1871 * @note As calculation input, the analog reference voltage (Vref+) must be
1872 * defined as it impacts the ADC LSB equivalent voltage.
1873 * @note Analog reference voltage (Vref+) must be either known from
1874 * user board environment or can be calculated using ADC measurement
1875 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1876 * @note ADC measurement data must correspond to a resolution of 12bits
1877 * (full scale digital value 4095). If not the case, the data must be
1878 * preliminarily rescaled to an equivalent resolution of 12 bits.
1879 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1880 * On STM32H7, refer to device datasheet parameter "Avg_Slope".
1881 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1882 * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
1883 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1884 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1885 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1886 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1887 * This parameter can be one of the following values:
1888 * @arg @ref ADC_RESOLUTION_16B
1889 * @arg @ref ADC_RESOLUTION_14B
1890 * @arg @ref ADC_RESOLUTION_12B
1891 * @arg @ref ADC_RESOLUTION_10B
1892 * @arg @ref ADC_RESOLUTION_8B
1893 * @retval Temperature (unit: degree Celsius)
1894 */
1895#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1896 __TEMPSENSOR_TYP_CALX_V__,\
1897 __TEMPSENSOR_CALX_TEMP__,\
1898 __VREFANALOG_VOLTAGE__,\
1899 __TEMPSENSOR_ADC_DATA__,\
1900 __ADC_RESOLUTION__) \
1901 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
1902 (__TEMPSENSOR_TYP_CALX_V__),\
1903 (__TEMPSENSOR_CALX_TEMP__),\
1904 (__VREFANALOG_VOLTAGE__),\
1905 (__TEMPSENSOR_ADC_DATA__),\
1906 (__ADC_RESOLUTION__))
1907
1908/**
1909 * @}
1910 */
1911
1912/**
1913 * @}
1914 */
1915
1916/* Include ADC HAL Extended module */
1917#include "stm32h7xx_hal_adc_ex.h"
1918
1919/* Exported functions --------------------------------------------------------*/
1920/** @addtogroup ADC_Exported_Functions
1921 * @{
1922 */
1923
1924/** @addtogroup ADC_Exported_Functions_Group1
1925 * @brief Initialization and Configuration functions
1926 * @{
1927 */
1928/* Initialization and de-initialization functions ****************************/
1929HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
1930HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
1931void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
1932void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
1933
1934
1935#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1936/* Callbacks Register/UnRegister functions ***********************************/
1937HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
1938HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
1939#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1940/**
1941 * @}
1942 */
1943
1944/** @addtogroup ADC_Exported_Functions_Group2
1945 * @brief IO operation functions
1946 * @{
1947 */
1948/* IO operation functions *****************************************************/
1949
1950/* Blocking mode: Polling */
1951HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
1952HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
1953HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
1954HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
1955
1956/* Non-blocking mode: Interruption */
1957HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
1958HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
1959
1960/* Non-blocking mode: DMA */
1961HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
1962HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
1963
1964/* ADC retrieve conversion value intended to be used with polling or interruption */
1965uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
1966
1967/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
1968void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
1969void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
1970void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
1971void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
1972void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
1973/**
1974 * @}
1975 */
1976
1977/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
1978 * @brief Peripheral Control functions
1979 * @{
1980 */
1981/* Peripheral Control functions ***********************************************/
1982HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
1983HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
1984
1985/**
1986 * @}
1987 */
1988
1989/* Peripheral State functions *************************************************/
1990/** @addtogroup ADC_Exported_Functions_Group4
1991 * @{
1992 */
1993uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
1994uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
1995
1996/**
1997 * @}
1998 */
1999
2000/**
2001 * @}
2002 */
2003
2004/* Private functions -----------------------------------------------------------*/
2005/** @addtogroup ADC_Private_Functions ADC Private Functions
2006 * @{
2007 */
2008HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
2009HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
2010HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
2011void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
2012void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
2013void ADC_DMAError(DMA_HandleTypeDef *hdma);
2014void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
2015
2016/**
2017 * @}
2018 */
2019
2020/**
2021 * @}
2022 */
2023
2024/**
2025 * @}
2026 */
2027
2028#ifdef __cplusplus
2029}
2030#endif
2031
2032
2033#endif /* STM32H7xx_HAL_ADC_H */
2034
__IO
#define __IO
Defines 'read / write' permissions.
Definition core_armv81mml.h:290
HAL_ADC_DeInit
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
HAL_ADC_Init
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
HAL_ADC_MspDeInit
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
ADC MSP De-Initialization This function freeze the hardware resources used in this example.
Definition stm32h7xx_hal_msp.c:154
HAL_ADC_MspInit
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
ADC MSP Initialization This function configures the hardware resources used in this example.
Definition stm32h7xx_hal_msp.c:88
HAL_ADC_PollForEvent
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
HAL_ADC_Start
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
HAL_ADC_Stop
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
HAL_ADC_IRQHandler
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
HAL_ADC_GetValue
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
HAL_ADC_Start_DMA
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
HAL_ADC_LevelOutOfWindowCallback
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
HAL_ADC_ConvHalfCpltCallback
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
HAL_ADC_PollForConversion
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
HAL_ADC_ErrorCallback
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
HAL_ADC_Stop_DMA
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
HAL_ADC_Stop_IT
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
HAL_ADC_Start_IT
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
HAL_ADC_ConvCpltCallback
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
HAL_ADC_ConfigChannel
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
HAL_ADC_AnalogWDGConfig
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
HAL_ADC_GetError
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
HAL_ADC_GetState
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
ADC_Enable
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
ADC_DMAConvCplt
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
ADC_DMAHalfConvCplt
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
ADC_ConversionStop
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
ADC_ConfigureBoostMode
void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
ADC_DMAError
void ADC_DMAError(DMA_HandleTypeDef *hdma)
ADC_Disable
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
FunctionalState
FunctionalState
Definition stm32h7xx.h:187
stm32h7xx_hal_adc_ex.h
Header file of ADC HAL extended module.
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32h7xx_hal_def.h:40
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition stm32h7xx_hal_def.h:51
stm32h7xx_ll_adc.h
Header file of ADC LL module.
ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog.
Definition stm32h7xx_hal_adc.h:294
ADC_AnalogWDGConfTypeDef::WatchdogNumber
uint32_t WatchdogNumber
Select which ADC analog watchdog is monitoring the selected channel.
Definition stm32h7xx_hal_adc.h:295
ADC_AnalogWDGConfTypeDef::ITMode
FunctionalState ITMode
Specify whether the analog watchdog is configured in interrupt or polling mode.
Definition stm32h7xx_hal_adc.h:310
ADC_AnalogWDGConfTypeDef::LowThreshold
uint32_t LowThreshold
Configures the ADC analog watchdog Low threshold value.
Definition stm32h7xx_hal_adc.h:323
ADC_AnalogWDGConfTypeDef::HighThreshold
uint32_t HighThreshold
Configure the ADC analog watchdog High threshold value.
Definition stm32h7xx_hal_adc.h:313
ADC_AnalogWDGConfTypeDef::Channel
uint32_t Channel
Select which ADC channel to monitor by analog watchdog.
Definition stm32h7xx_hal_adc.h:305
ADC_AnalogWDGConfTypeDef::WatchdogMode
uint32_t WatchdogMode
Configure the ADC analog watchdog mode: single/all/none channels.
Definition stm32h7xx_hal_adc.h:300
ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group.
Definition stm32h7xx_hal_adc.h:220
ADC_ChannelConfTypeDef::Rank
uint32_t Rank
Specify the rank in the regular group sequencer.
Definition stm32h7xx_hal_adc.h:225
ADC_ChannelConfTypeDef::SingleDiff
uint32_t SingleDiff
Select single-ended or differential input.
Definition stm32h7xx_hal_adc.h:241
ADC_ChannelConfTypeDef::Offset
uint32_t Offset
Define the offset to be subtracted from the raw converted data.
Definition stm32h7xx_hal_adc.h:257
ADC_ChannelConfTypeDef::OffsetRightShift
FunctionalState OffsetRightShift
Define the Right-shift data after Offset correction.
Definition stm32h7xx_hal_adc.h:264
ADC_ChannelConfTypeDef::Channel
uint32_t Channel
Specify the channel to configure into ADC regular group.
Definition stm32h7xx_hal_adc.h:221
ADC_ChannelConfTypeDef::OffsetSignedSaturation
FunctionalState OffsetSignedSaturation
Specify whether the Signed saturation feature is used or not.
Definition stm32h7xx_hal_adc.h:281
ADC_ChannelConfTypeDef::SamplingTime
uint32_t SamplingTime
Sampling time value to be set for the selected channel.
Definition stm32h7xx_hal_adc.h:230
ADC_ChannelConfTypeDef::OffsetNumber
uint32_t OffsetNumber
Select the offset number This parameter can be a value of ADC instance - Offset number Caution: Only ...
Definition stm32h7xx_hal_adc.h:253
ADC_HandleTypeDef
ADC handle Structure definition.
Definition stm32h7xx_hal_adc.h:410
ADC_HandleTypeDef::InjectionConfig
ADC_InjectionConfigTypeDef InjectionConfig
ADC injected channel configuration build-up structure.
Definition stm32h7xx_hal_adc.h:417
ADC_HandleTypeDef::DMA_Handle
DMA_HandleTypeDef * DMA_Handle
Pointer DMA Handler.
Definition stm32h7xx_hal_adc.h:413
ADC_HandleTypeDef::Instance
ADC_TypeDef * Instance
Register base address.
Definition stm32h7xx_hal_adc.h:411
ADC_HandleTypeDef::Init
ADC_InitTypeDef Init
ADC initialization parameters and regular conversions setting.
Definition stm32h7xx_hal_adc.h:412
ADC_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
ADC Error code.
Definition stm32h7xx_hal_adc.h:416
ADC_HandleTypeDef::Lock
HAL_LockTypeDef Lock
ADC locking object.
Definition stm32h7xx_hal_adc.h:414
ADC_HandleTypeDef::State
__IO uint32_t State
ADC communication state (bitmap of ADC states).
Definition stm32h7xx_hal_adc.h:415
ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular.
Definition stm32h7xx_hal_adc.h:91
ADC_InitTypeDef::ContinuousConvMode
FunctionalState ContinuousConvMode
Specify whether the conversion is performed in single mode (one conversion) or continuous mode for AD...
Definition stm32h7xx_hal_adc.h:136
ADC_InitTypeDef::ExternalTrigConv
uint32_t ExternalTrigConv
Select the external event source used to trigger ADC group regular conversion start.
Definition stm32h7xx_hal_adc.h:156
ADC_InitTypeDef::ScanConvMode
uint32_t ScanConvMode
Configure the sequencer of ADC groups regular and injected.
Definition stm32h7xx_hal_adc.h:113
ADC_InitTypeDef::ConversionDataManagement
uint32_t ConversionDataManagement
Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular),...
Definition stm32h7xx_hal_adc.h:165
ADC_InitTypeDef::NbrOfDiscConversion
uint32_t NbrOfDiscConversion
Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (pa...
Definition stm32h7xx_hal_adc.h:152
ADC_InitTypeDef::Overrun
uint32_t Overrun
Select the behavior in case of overrun: data overwritten or preserved (default).
Definition stm32h7xx_hal_adc.h:186
ADC_InitTypeDef::OversamplingMode
FunctionalState OversamplingMode
Specify whether the oversampling feature is enabled or disabled.
Definition stm32h7xx_hal_adc.h:199
ADC_InitTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ...
Definition stm32h7xx_hal_adc.h:92
ADC_InitTypeDef::LeftBitShift
uint32_t LeftBitShift
Configures the left shifting applied to the final result with or without oversampling.
Definition stm32h7xx_hal_adc.h:197
ADC_InitTypeDef::NbrOfConversion
uint32_t NbrOfConversion
Specify the number of ranks that will be converted within the regular group sequencer.
Definition stm32h7xx_hal_adc.h:140
ADC_InitTypeDef::Resolution
uint32_t Resolution
Configure the ADC resolution.
Definition stm32h7xx_hal_adc.h:103
ADC_InitTypeDef::EOCSelection
uint32_t EOCSelection
Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of...
Definition stm32h7xx_hal_adc.h:121
ADC_InitTypeDef::ExternalTrigConvEdge
uint32_t ExternalTrigConvEdge
Select the external event edge used to trigger ADC group regular conversion start.
Definition stm32h7xx_hal_adc.h:161
ADC_InitTypeDef::Oversampling
ADC_OversamplingTypeDef Oversampling
Specify the Oversampling parameters.
Definition stm32h7xx_hal_adc.h:203
ADC_InitTypeDef::DiscontinuousConvMode
FunctionalState DiscontinuousConvMode
Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Disco...
Definition stm32h7xx_hal_adc.h:146
ADC_InitTypeDef::LowPowerAutoWait
FunctionalState LowPowerAutoWait
Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ...
Definition stm32h7xx_hal_adc.h:124
ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration.
Definition stm32h7xx_hal_adc.h:346
ADC_InjectionConfigTypeDef::ChannelCount
uint32_t ChannelCount
Number of channels in the injected sequence.
Definition stm32h7xx_hal_adc.h:351
ADC_InjectionConfigTypeDef::ContextQueue
uint32_t ContextQueue
Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to ...
Definition stm32h7xx_hal_adc.h:347
ADC_OversamplingTypeDef
ADC group regular oversampling structure definition.
Definition stm32h7xx_hal_adc.h:50
ADC_OversamplingTypeDef::Ratio
uint32_t Ratio
Configures the oversampling ratio.
Definition stm32h7xx_hal_adc.h:51
ADC_OversamplingTypeDef::RightBitShift
uint32_t RightBitShift
Configures the division coefficient for the Oversampler.
Definition stm32h7xx_hal_adc.h:58
ADC_OversamplingTypeDef::OversamplingStopReset
uint32_t OversamplingStopReset
Selects the regular oversampling mode.
Definition stm32h7xx_hal_adc.h:64
ADC_OversamplingTypeDef::TriggeredMode
uint32_t TriggeredMode
Selects the regular triggered oversampling mode.
Definition stm32h7xx_hal_adc.h:61
ADC_TypeDef
Analog to Digital Converter.
Definition stm32h723xx.h:242