SYSCFG Exported Macros

Collaboration diagram for SYSCFG Exported Macros:

Macros
#define	__HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()
	SYSCFG Break AXIRAM double ECC lock.
#define	__HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()
	SYSCFG Break ITCM double ECC lock.
#define	__HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()
	SYSCFG Break DTCM double ECC lock.
#define	__HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()
	SYSCFG Break SRAM1 double ECC lock.
#define	__HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()
	SYSCFG Break SRAM2 double ECC lock.
#define	__HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()
	SYSCFG Break SRAM3 double ECC lock.
#define	__HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()
	SYSCFG Break SRAM4 double ECC lock.
#define	__HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()
	SYSCFG Break Backup SRAM double ECC lock.
#define	__HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()
	SYSCFG Break Cortex-M7 Lockup lock.
#define	__HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()
	SYSCFG Break FLASH double ECC lock.
#define	__HAL_SYSCFG_BREAK_PVD_LOCK()
	SYSCFG Break PVD lock.
#define	__HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
	Fast-mode Plus driving capability enable/disable macros.
#define	__HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)

Detailed Description

Macro Definition Documentation

__HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)

SYSCFG Break AXIRAM double ECC lock.

Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 755 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)

SYSCFG Break Backup SRAM double ECC lock.

Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 804 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK

#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)

SYSCFG Break Cortex-M7 Lockup lock.

Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 811 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)

SYSCFG Break DTCM double ECC lock.

Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 769 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)

SYSCFG Break FLASH double ECC lock.

Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 818 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)

SYSCFG Break ITCM double ECC lock.

Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 762 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_PVD_LOCK

#define __HAL_SYSCFG_BREAK_PVD_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)

SYSCFG Break PVD lock.

Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 825 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)

SYSCFG Break SRAM1 double ECC lock.

Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 776 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)

SYSCFG Break SRAM2 double ECC lock.

Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 783 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)

SYSCFG Break SRAM3 double ECC lock.

Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 790 of file stm32h7xx_hal.h.

__HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK

#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK

(

)

Value:

SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)

SYSCFG Break SRAM4 double ECC lock.

Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

Note

The selected configuration is locked and can be unlocked only by system reset. This feature is available on STM32H7 rev.B and above.

Definition at line 797 of file stm32h7xx_hal.h.

__HAL_SYSCFG_FASTMODEPLUS_DISABLE

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE

(

__FASTMODEPLUS__

)

Value:

                                                                do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
                                                               }while(0)

Definition at line 848 of file stm32h7xx_hal.h.

__HAL_SYSCFG_FASTMODEPLUS_ENABLE

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE

(

__FASTMODEPLUS__

)

Value:

                                                                do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
                                                               }while(0)

Fast-mode Plus driving capability enable/disable macros.

Parameters

__FASTMODEPLUS__

This parameter can be a value of : SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9

Definition at line 844 of file stm32h7xx_hal.h.