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TIM Break System
STM32H7xx_HAL_Driver » TIM » TIM Exported Constants
Collaboration diagram for TIM Break System:

Macros

#define TIM_BREAK_SYSTEM_ECC   SYSCFG_CFGR2_ECCL
 Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17.
#define TIM_BREAK_SYSTEM_PVD   SYSCFG_CFGR2_PVDL
 Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface.
#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL
 Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17.
#define TIM_BREAK_SYSTEM_LOCKUP   SYSCFG_CFGR2_CLL
 Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17.

Detailed Description

Macro Definition Documentation

◆ TIM_BREAK_SYSTEM_ECC

#define TIM_BREAK_SYSTEM_ECC   SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17.

Definition at line 1156 of file stm32h7xx_hal_tim.h.

◆ TIM_BREAK_SYSTEM_LOCKUP

#define TIM_BREAK_SYSTEM_LOCKUP   SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17.

Definition at line 1159 of file stm32h7xx_hal_tim.h.

◆ TIM_BREAK_SYSTEM_PVD

#define TIM_BREAK_SYSTEM_PVD   SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface.

Definition at line 1157 of file stm32h7xx_hal_tim.h.

◆ TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR

#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17.

Definition at line 1158 of file stm32h7xx_hal_tim.h.