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stm32h7xx_hal_tim.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_hal_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_TIM_H
21#define STM32H7xx_HAL_TIM_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
30/** @addtogroup STM32H7xx_HAL_Driver
31 * @{
32 */
33
34/** @addtogroup TIM
35 * @{
36 */
37
38/* Exported types ------------------------------------------------------------*/
39/** @defgroup TIM_Exported_Types TIM Exported Types
40 * @{
41 */
42
43/**
44 * @brief TIM Time base Configuration Structure definition
45 */
46typedef struct
47{
48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
50
51 uint32_t CounterMode; /*!< Specifies the counter mode.
52 This parameter can be a value of @ref TIM_Counter_Mode */
53
54 uint32_t Period; /*!< Specifies the period value to be loaded into the active
55 Auto-Reload Register at the next update event.
56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
57
58 uint32_t ClockDivision; /*!< Specifies the clock division.
59 This parameter can be a value of @ref TIM_ClockDivision */
60
61 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
62 reaches zero, an update event is generated and counting restarts
63 from the RCR value (N).
64 This means in PWM mode that (N+1) corresponds to:
65 - the number of PWM periods in edge-aligned mode
66 - the number of half PWM period in center-aligned mode
67 GP timers: this parameter must be a number between Min_Data = 0x00 and
68 Max_Data = 0xFF.
69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
70 Max_Data = 0xFFFF. */
71
72 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
73 This parameter can be a value of @ref TIM_AutoReloadPreload */
74} TIM_Base_InitTypeDef;
75
76/**
77 * @brief TIM Output Compare Configuration Structure definition
78 */
79typedef struct
80{
81 uint32_t OCMode; /*!< Specifies the TIM mode.
82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
83
84 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
85 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
86
87 uint32_t OCPolarity; /*!< Specifies the output polarity.
88 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
89
90 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
91 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
92 @note This parameter is valid only for timer instances supporting break feature. */
93
94 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
95 This parameter can be a value of @ref TIM_Output_Fast_State
96 @note This parameter is valid only in PWM1 and PWM2 mode. */
97
98
99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
101 @note This parameter is valid only for timer instances supporting break feature. */
102
103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
105 @note This parameter is valid only for timer instances supporting break feature. */
106} TIM_OC_InitTypeDef;
107
108/**
109 * @brief TIM One Pulse Mode Configuration Structure definition
110 */
111typedef struct
112{
113 uint32_t OCMode; /*!< Specifies the TIM mode.
114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
115
116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
118
119 uint32_t OCPolarity; /*!< Specifies the output polarity.
120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
121
122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
124 @note This parameter is valid only for timer instances supporting break feature. */
125
126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
128 @note This parameter is valid only for timer instances supporting break feature. */
129
130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
132 @note This parameter is valid only for timer instances supporting break feature. */
133
134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
136
137 uint32_t ICSelection; /*!< Specifies the input.
138 This parameter can be a value of @ref TIM_Input_Capture_Selection */
139
140 uint32_t ICFilter; /*!< Specifies the input capture filter.
141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
142} TIM_OnePulse_InitTypeDef;
143
144/**
145 * @brief TIM Input Capture Configuration Structure definition
146 */
147typedef struct
148{
149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
151
152 uint32_t ICSelection; /*!< Specifies the input.
153 This parameter can be a value of @ref TIM_Input_Capture_Selection */
154
155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
157
158 uint32_t ICFilter; /*!< Specifies the input capture filter.
159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
160} TIM_IC_InitTypeDef;
161
162/**
163 * @brief TIM Encoder Configuration Structure definition
164 */
165typedef struct
166{
167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
168 This parameter can be a value of @ref TIM_Encoder_Mode */
169
170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
171 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
172
173 uint32_t IC1Selection; /*!< Specifies the input.
174 This parameter can be a value of @ref TIM_Input_Capture_Selection */
175
176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
178
179 uint32_t IC1Filter; /*!< Specifies the input capture filter.
180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
181
182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
183 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
184
185 uint32_t IC2Selection; /*!< Specifies the input.
186 This parameter can be a value of @ref TIM_Input_Capture_Selection */
187
188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
190
191 uint32_t IC2Filter; /*!< Specifies the input capture filter.
192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
193} TIM_Encoder_InitTypeDef;
194
195/**
196 * @brief Clock Configuration Handle Structure definition
197 */
198typedef struct
199{
200 uint32_t ClockSource; /*!< TIM clock sources
201 This parameter can be a value of @ref TIM_Clock_Source */
202 uint32_t ClockPolarity; /*!< TIM clock polarity
203 This parameter can be a value of @ref TIM_Clock_Polarity */
204 uint32_t ClockPrescaler; /*!< TIM clock prescaler
205 This parameter can be a value of @ref TIM_Clock_Prescaler */
206 uint32_t ClockFilter; /*!< TIM clock filter
207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208} TIM_ClockConfigTypeDef;
209
210/**
211 * @brief TIM Clear Input Configuration Handle Structure definition
212 */
213typedef struct
214{
215 uint32_t ClearInputState; /*!< TIM clear Input state
216 This parameter can be ENABLE or DISABLE */
217 uint32_t ClearInputSource; /*!< TIM clear Input sources
218 This parameter can be a value of @ref TIM_ClearInput_Source */
219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
220 This parameter can be a value of @ref TIM_ClearInput_Polarity */
221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
222 This parameter must be 0: When OCRef clear feature is used with ETR source,
223 ETR prescaler must be off */
224 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
226} TIM_ClearInputConfigTypeDef;
227
228/**
229 * @brief TIM Master configuration Structure definition
230 * @note Advanced timers provide TRGO2 internal line which is redirected
231 * to the ADC
232 */
233typedef struct
234{
235 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
236 This parameter can be a value of @ref TIM_Master_Mode_Selection */
237 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
238 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
239 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
240 This parameter can be a value of @ref TIM_Master_Slave_Mode
241 @note When the Master/slave mode is enabled, the effect of
242 an event on the trigger input (TRGI) is delayed to allow a
243 perfect synchronization between the current timer and its
244 slaves (through TRGO). It is not mandatory in case of timer
245 synchronization mode. */
246} TIM_MasterConfigTypeDef;
247
248/**
249 * @brief TIM Slave configuration Structure definition
250 */
251typedef struct
252{
253 uint32_t SlaveMode; /*!< Slave mode selection
254 This parameter can be a value of @ref TIM_Slave_Mode */
255 uint32_t InputTrigger; /*!< Input Trigger source
256 This parameter can be a value of @ref TIM_Trigger_Selection */
257 uint32_t TriggerPolarity; /*!< Input Trigger polarity
258 This parameter can be a value of @ref TIM_Trigger_Polarity */
259 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
260 This parameter can be a value of @ref TIM_Trigger_Prescaler */
261 uint32_t TriggerFilter; /*!< Input trigger filter
262 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
263
264} TIM_SlaveConfigTypeDef;
265
266/**
267 * @brief TIM Break input(s) and Dead time configuration Structure definition
268 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
269 * filter and polarity.
270 */
271typedef struct
272{
273 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
274
275 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
276
277 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
278
279 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
280
281 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
282
283 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
284
285 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
286
287#if defined(TIM_BDTR_BKBID)
288 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
289
290#endif /* TIM_BDTR_BKBID */
291 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
292
293 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
294
295 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
296
297#if defined(TIM_BDTR_BKBID)
298 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
299#endif /* TIM_BDTR_BKBID */
300
301 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
302
303} TIM_BreakDeadTimeConfigTypeDef;
304
305/**
306 * @brief HAL State structures definition
307 */
308typedef enum
309{
310 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
311 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
312 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
313 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
314 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
315} HAL_TIM_StateTypeDef;
316
317/**
318 * @brief TIM Channel States definition
319 */
320typedef enum
321{
322 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
323 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
324 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
325} HAL_TIM_ChannelStateTypeDef;
326
327/**
328 * @brief DMA Burst States definition
329 */
330typedef enum
331{
332 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
333 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
334 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
335} HAL_TIM_DMABurstStateTypeDef;
336
337/**
338 * @brief HAL Active channel structures definition
339 */
340typedef enum
341{
342 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
343 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
344 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
345 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
346 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
347 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
348 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
349} HAL_TIM_ActiveChannel;
350
351/**
352 * @brief TIM Time Base Handle Structure definition
353 */
354#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
355typedef struct __TIM_HandleTypeDef
356#else
357typedef struct
358#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
359{
360 TIM_TypeDef *Instance; /*!< Register base address */
361 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
362 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
363 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
364 This array is accessed by a @ref DMA_Handle_index */
365 HAL_LockTypeDef Lock; /*!< Locking object */
366 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
367 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
368 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
369 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
370
371#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
372 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
373 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
374 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
375 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
376 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
377 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
378 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
379 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
380 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
381 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
382 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
383 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
384 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
385 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
386 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
387 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
388 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
389 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
390 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
391 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
392 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
393 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
394 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
395 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
396 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
397 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
398 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
399 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
400#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
401} TIM_HandleTypeDef;
402
403#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
404/**
405 * @brief HAL TIM Callback ID enumeration definition
406 */
407typedef enum
408{
409 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
410 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
411 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
412 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
413 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
414 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
415 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
416 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
417 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
418 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
419 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
420 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
421 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
422 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
423 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
424 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
425 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
426 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
427 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
428 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
429 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
430 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
431 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
432 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
433 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
434 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
435 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
436 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
437} HAL_TIM_CallbackIDTypeDef;
438
439/**
440 * @brief HAL TIM Callback pointer definition
441 */
442typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
443
444#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
445
446/**
447 * @}
448 */
449/* End of exported types -----------------------------------------------------*/
450
451/* Exported constants --------------------------------------------------------*/
452/** @defgroup TIM_Exported_Constants TIM Exported Constants
453 * @{
454 */
455
456/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
457 * @{
458 */
459#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
460#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
461/**
462 * @}
463 */
464
465/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
466 * @{
467 */
468#define TIM_DMABASE_CR1 0x00000000U
469#define TIM_DMABASE_CR2 0x00000001U
470#define TIM_DMABASE_SMCR 0x00000002U
471#define TIM_DMABASE_DIER 0x00000003U
472#define TIM_DMABASE_SR 0x00000004U
473#define TIM_DMABASE_EGR 0x00000005U
474#define TIM_DMABASE_CCMR1 0x00000006U
475#define TIM_DMABASE_CCMR2 0x00000007U
476#define TIM_DMABASE_CCER 0x00000008U
477#define TIM_DMABASE_CNT 0x00000009U
478#define TIM_DMABASE_PSC 0x0000000AU
479#define TIM_DMABASE_ARR 0x0000000BU
480#define TIM_DMABASE_RCR 0x0000000CU
481#define TIM_DMABASE_CCR1 0x0000000DU
482#define TIM_DMABASE_CCR2 0x0000000EU
483#define TIM_DMABASE_CCR3 0x0000000FU
484#define TIM_DMABASE_CCR4 0x00000010U
485#define TIM_DMABASE_BDTR 0x00000011U
486#define TIM_DMABASE_DCR 0x00000012U
487#define TIM_DMABASE_DMAR 0x00000013U
488#define TIM_DMABASE_CCMR3 0x00000015U
489#define TIM_DMABASE_CCR5 0x00000016U
490#define TIM_DMABASE_CCR6 0x00000017U
491#if defined(TIM_BREAK_INPUT_SUPPORT)
492#define TIM_DMABASE_AF1 0x00000018U
493#define TIM_DMABASE_AF2 0x00000019U
494#endif /* TIM_BREAK_INPUT_SUPPORT */
495#define TIM_DMABASE_TISEL 0x0000001AU
496/**
497 * @}
498 */
499
500/** @defgroup TIM_Event_Source TIM Event Source
501 * @{
502 */
503#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
504#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
505#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
506#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
507#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
508#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
509#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
510#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
511#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
512/**
513 * @}
514 */
515
516/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
517 * @{
518 */
519#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
520#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
521#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
522/**
523 * @}
524 */
525
526/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
527 * @{
528 */
529#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
530#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
531/**
532 * @}
533 */
534
535/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
536 * @{
537 */
538#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
539#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
540#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
541#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
542/**
543 * @}
544 */
545
546/** @defgroup TIM_Counter_Mode TIM Counter Mode
547 * @{
548 */
549#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
550#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
551#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
552#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
553#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
554/**
555 * @}
556 */
557
558/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
559 * @{
560 */
561#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
562#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
563/**
564 * @}
565 */
566
567/** @defgroup TIM_ClockDivision TIM Clock Division
568 * @{
569 */
570#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
571#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
572#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
573/**
574 * @}
575 */
576
577/** @defgroup TIM_Output_Compare_State TIM Output Compare State
578 * @{
579 */
580#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
581#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
582/**
583 * @}
584 */
585
586/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
587 * @{
588 */
589#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
590#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
591
592/**
593 * @}
594 */
595
596/** @defgroup TIM_Output_Fast_State TIM Output Fast State
597 * @{
598 */
599#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
600#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
601/**
602 * @}
603 */
604
605/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
606 * @{
607 */
608#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
609#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
610/**
611 * @}
612 */
613
614/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
615 * @{
616 */
617#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
618#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
619/**
620 * @}
621 */
622
623/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
624 * @{
625 */
626#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
627#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
628/**
629 * @}
630 */
631
632/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
633 * @{
634 */
635#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
636#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
637/**
638 * @}
639 */
640
641/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
642 * @{
643 */
644#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
645#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
646/**
647 * @}
648 */
649
650/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
651 * @{
652 */
653#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
654#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
655#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
656/**
657 * @}
658 */
659
660/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
661 * @{
662 */
663#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
664#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
665/**
666 * @}
667 */
668
669/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
670 * @{
671 */
672#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
673#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
674#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
675/**
676 * @}
677 */
678
679/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
680 * @{
681 */
682#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
683#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
684#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
685#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
686/**
687 * @}
688 */
689
690/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
691 * @{
692 */
693#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
694#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
695/**
696 * @}
697 */
698
699/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
700 * @{
701 */
702#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
703#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
704#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
705/**
706 * @}
707 */
708
709/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
710 * @{
711 */
712#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
713#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
714#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
715#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
716#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
717#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
718#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
719#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
720/**
721 * @}
722 */
723
724/** @defgroup TIM_Commutation_Source TIM Commutation Source
725 * @{
726 */
727#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
728#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
729/**
730 * @}
731 */
732
733/** @defgroup TIM_DMA_sources TIM DMA Sources
734 * @{
735 */
736#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
737#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
738#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
739#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
740#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
741#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
742#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
743/**
744 * @}
745 */
746
747/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
748 * @{
749 */
750#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
751#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
752/**
753 * @}
754 */
755
756/** @defgroup TIM_Flag_definition TIM Flag Definition
757 * @{
758 */
759#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
760#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
761#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
762#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
763#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
764#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
765#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
766#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
767#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
768#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
769#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
770#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
771#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
772#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
773#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
774#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
775/**
776 * @}
777 */
778
779/** @defgroup TIM_Channel TIM Channel
780 * @{
781 */
782#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
783#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
784#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
785#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
786#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
787#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
788#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
789/**
790 * @}
791 */
792
793/** @defgroup TIM_Clock_Source TIM Clock Source
794 * @{
795 */
796#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
797#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
798#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
799#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
800#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
801#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
802#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
803#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
804#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
805#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
806#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
807#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
808#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
809#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
810#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
811/**
812 * @}
813 */
814
815/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
816 * @{
817 */
818#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
819#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
820#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
821#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
822#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
823/**
824 * @}
825 */
826
827/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
828 * @{
829 */
830#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
831#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
832#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
833#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
834/**
835 * @}
836 */
837
838/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
839 * @{
840 */
841#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
842#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
843/**
844 * @}
845 */
846
847/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
848 * @{
849 */
850#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
851#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
852#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
853#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
854/**
855 * @}
856 */
857
858/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
859 * @{
860 */
861#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
862#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
863/**
864 * @}
865 */
866
867/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
868 * @{
869 */
870#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
871#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
872/**
873 * @}
874 */
875/** @defgroup TIM_Lock_level TIM Lock level
876 * @{
877 */
878#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
879#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
880#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
881#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
882/**
883 * @}
884 */
885
886/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
887 * @{
888 */
889#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
890#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
891/**
892 * @}
893 */
894
895/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
896 * @{
897 */
898#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
899#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
900/**
901 * @}
902 */
903#if defined(TIM_BDTR_BKBID)
904
905/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
906 * @{
907 */
908#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
909#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
910/**
911 * @}
912 */
913#endif /*TIM_BDTR_BKBID */
914
915/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
916 * @{
917 */
918#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
919#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
920/**
921 * @}
922 */
923
924/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
925 * @{
926 */
927#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
928#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
929/**
930 * @}
931 */
932#if defined(TIM_BDTR_BKBID)
933
934/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
935 * @{
936 */
937#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
938#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
939/**
940 * @}
941 */
942#endif /* TIM_BDTR_BKBID */
943
944/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
945 * @{
946 */
947#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
948#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
949/**
950 * @}
951 */
952
953/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
954 * @{
955 */
956#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
957#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
958#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
959#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
960/**
961 * @}
962 */
963
964/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
965 * @{
966 */
967#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
968#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
969#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
970#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
971#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
972#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
973#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
974#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
975/**
976 * @}
977 */
978
979/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
980 * @{
981 */
982#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
983#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
984#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
985#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
986#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
987#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
988#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
989#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
990#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
991#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
992#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
993#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
994#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
995#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
996#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
997#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
998/**
999 * @}
1000 */
1001
1002/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
1003 * @{
1004 */
1005#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
1006#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
1007/**
1008 * @}
1009 */
1010
1011/** @defgroup TIM_Slave_Mode TIM Slave mode
1012 * @{
1013 */
1014#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
1015#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
1016#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
1017#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
1018#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
1019#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
1020/**
1021 * @}
1022 */
1023
1024/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
1025 * @{
1026 */
1027#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
1028#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
1029#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
1030#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
1031#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
1032#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
1033#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
1034#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
1035#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
1036#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
1037#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
1038#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
1039#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
1040#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
1041/**
1042 * @}
1043 */
1044
1045/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
1046 * @{
1047 */
1048#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
1049#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
1050#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
1051#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
1052#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */
1053#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
1054#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
1055#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
1056#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
1057#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
1058#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
1059#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
1060#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */
1061#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */
1062#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
1063#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
1064#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
1065#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
1066#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
1067/**
1068 * @}
1069 */
1070
1071/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
1072 * @{
1073 */
1074#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
1075#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
1076#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1077#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1078#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1079/**
1080 * @}
1081 */
1082
1083/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
1084 * @{
1085 */
1086#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
1087#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
1088#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
1089#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
1090/**
1091 * @}
1092 */
1093
1094/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1095 * @{
1096 */
1097#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
1098#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
1099/**
1100 * @}
1101 */
1102
1103/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1104 * @{
1105 */
1106#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
1107#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1108#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1109#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1110#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1111#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1112#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1113#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1114#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1115#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1116#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1117#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1118#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1119#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1120#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1121#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1122#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1123#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1124/**
1125 * @}
1126 */
1127
1128/** @defgroup DMA_Handle_index TIM DMA Handle Index
1129 * @{
1130 */
1131#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
1132#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1133#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1134#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1135#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1136#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
1137#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
1138/**
1139 * @}
1140 */
1141
1142/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1143 * @{
1144 */
1145#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
1146#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
1147#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
1148#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
1149/**
1150 * @}
1151 */
1152
1153/** @defgroup TIM_Break_System TIM Break System
1154 * @{
1155 */
1156#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
1157#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
1158#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
1159#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
1160/**
1161 * @}
1162 */
1163
1164/**
1165 * @}
1166 */
1167/* End of exported constants -------------------------------------------------*/
1168
1169/* Exported macros -----------------------------------------------------------*/
1170/** @defgroup TIM_Exported_Macros TIM Exported Macros
1171 * @{
1172 */
1173
1174/** @brief Reset TIM handle state.
1175 * @param __HANDLE__ TIM handle.
1176 * @retval None
1177 */
1178#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1179#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1180 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1181 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1182 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1183 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1184 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1185 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1186 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1187 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1188 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1189 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1190 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1191 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1192 (__HANDLE__)->Base_MspInitCallback = NULL; \
1193 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1194 (__HANDLE__)->IC_MspInitCallback = NULL; \
1195 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1196 (__HANDLE__)->OC_MspInitCallback = NULL; \
1197 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1198 (__HANDLE__)->PWM_MspInitCallback = NULL; \
1199 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1200 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1201 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1202 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1203 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1204 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1205 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1206 } while(0)
1207#else
1208#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1209 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1210 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1211 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1212 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1213 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1214 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1215 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1216 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1217 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1218 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1219 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1220 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1221 } while(0)
1222#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1223
1224/**
1225 * @brief Enable the TIM peripheral.
1226 * @param __HANDLE__ TIM handle
1227 * @retval None
1228 */
1229#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1230
1231/**
1232 * @brief Enable the TIM main Output.
1233 * @param __HANDLE__ TIM handle
1234 * @retval None
1235 */
1236#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1237
1238/**
1239 * @brief Disable the TIM peripheral.
1240 * @param __HANDLE__ TIM handle
1241 * @retval None
1242 */
1243#define __HAL_TIM_DISABLE(__HANDLE__) \
1244 do { \
1245 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1246 { \
1247 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1248 { \
1249 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1250 } \
1251 } \
1252 } while(0)
1253
1254/**
1255 * @brief Disable the TIM main Output.
1256 * @param __HANDLE__ TIM handle
1257 * @retval None
1258 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
1259 * disabled
1260 */
1261#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1262 do { \
1263 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1264 { \
1265 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1266 { \
1267 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1268 } \
1269 } \
1270 } while(0)
1271
1272/**
1273 * @brief Disable the TIM main Output.
1274 * @param __HANDLE__ TIM handle
1275 * @retval None
1276 * @note The Main Output Enable of a timer instance is disabled unconditionally
1277 */
1278#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1279
1280/** @brief Enable the specified TIM interrupt.
1281 * @param __HANDLE__ specifies the TIM Handle.
1282 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
1283 * This parameter can be one of the following values:
1284 * @arg TIM_IT_UPDATE: Update interrupt
1285 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1286 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1287 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1288 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1289 * @arg TIM_IT_COM: Commutation interrupt
1290 * @arg TIM_IT_TRIGGER: Trigger interrupt
1291 * @arg TIM_IT_BREAK: Break interrupt
1292 * @retval None
1293 */
1294#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1295
1296/** @brief Disable the specified TIM interrupt.
1297 * @param __HANDLE__ specifies the TIM Handle.
1298 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
1299 * This parameter can be one of the following values:
1300 * @arg TIM_IT_UPDATE: Update interrupt
1301 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1302 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1303 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1304 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1305 * @arg TIM_IT_COM: Commutation interrupt
1306 * @arg TIM_IT_TRIGGER: Trigger interrupt
1307 * @arg TIM_IT_BREAK: Break interrupt
1308 * @retval None
1309 */
1310#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1311
1312/** @brief Enable the specified DMA request.
1313 * @param __HANDLE__ specifies the TIM Handle.
1314 * @param __DMA__ specifies the TIM DMA request to enable.
1315 * This parameter can be one of the following values:
1316 * @arg TIM_DMA_UPDATE: Update DMA request
1317 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1318 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1319 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1320 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1321 * @arg TIM_DMA_COM: Commutation DMA request
1322 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1323 * @retval None
1324 */
1325#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1326
1327/** @brief Disable the specified DMA request.
1328 * @param __HANDLE__ specifies the TIM Handle.
1329 * @param __DMA__ specifies the TIM DMA request to disable.
1330 * This parameter can be one of the following values:
1331 * @arg TIM_DMA_UPDATE: Update DMA request
1332 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1333 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1334 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1335 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1336 * @arg TIM_DMA_COM: Commutation DMA request
1337 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1338 * @retval None
1339 */
1340#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1341
1342/** @brief Check whether the specified TIM interrupt flag is set or not.
1343 * @param __HANDLE__ specifies the TIM Handle.
1344 * @param __FLAG__ specifies the TIM interrupt flag to check.
1345 * This parameter can be one of the following values:
1346 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1347 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1348 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1349 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1350 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1351 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1352 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1353 * @arg TIM_FLAG_COM: Commutation interrupt flag
1354 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1355 * @arg TIM_FLAG_BREAK: Break interrupt flag
1356 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1357 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1358 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1359 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1360 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1361 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1362 * @retval The new state of __FLAG__ (TRUE or FALSE).
1363 */
1364#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1365
1366/** @brief Clear the specified TIM interrupt flag.
1367 * @param __HANDLE__ specifies the TIM Handle.
1368 * @param __FLAG__ specifies the TIM interrupt flag to clear.
1369 * This parameter can be one of the following values:
1370 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1371 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1372 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1373 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1374 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1375 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1376 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1377 * @arg TIM_FLAG_COM: Commutation interrupt flag
1378 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1379 * @arg TIM_FLAG_BREAK: Break interrupt flag
1380 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1381 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1382 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1383 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1384 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1385 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1386 * @retval The new state of __FLAG__ (TRUE or FALSE).
1387 */
1388#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1389
1390/**
1391 * @brief Check whether the specified TIM interrupt source is enabled or not.
1392 * @param __HANDLE__ TIM handle
1393 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
1394 * This parameter can be one of the following values:
1395 * @arg TIM_IT_UPDATE: Update interrupt
1396 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1397 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1398 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1399 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1400 * @arg TIM_IT_COM: Commutation interrupt
1401 * @arg TIM_IT_TRIGGER: Trigger interrupt
1402 * @arg TIM_IT_BREAK: Break interrupt
1403 * @retval The state of TIM_IT (SET or RESET).
1404 */
1405#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1406 == (__INTERRUPT__)) ? SET : RESET)
1407
1408/** @brief Clear the TIM interrupt pending bits.
1409 * @param __HANDLE__ TIM handle
1410 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1411 * This parameter can be one of the following values:
1412 * @arg TIM_IT_UPDATE: Update interrupt
1413 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1414 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1415 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1416 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1417 * @arg TIM_IT_COM: Commutation interrupt
1418 * @arg TIM_IT_TRIGGER: Trigger interrupt
1419 * @arg TIM_IT_BREAK: Break interrupt
1420 * @retval None
1421 */
1422#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1423
1424/**
1425 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1426 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1427 * in an atomic way.
1428 * @param __HANDLE__ TIM handle.
1429 * @retval None
1430mode.
1431 */
1432#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
1433
1434/**
1435 * @brief Disable update interrupt flag (UIF) remapping.
1436 * @param __HANDLE__ TIM handle.
1437 * @retval None
1438mode.
1439 */
1440#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1441
1442/**
1443 * @brief Get update interrupt flag (UIF) copy status.
1444 * @param __COUNTER__ Counter value.
1445 * @retval The state of UIFCPY (TRUE or FALSE).
1446mode.
1447 */
1448#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1449
1450/**
1451 * @brief Indicates whether or not the TIM Counter is used as downcounter.
1452 * @param __HANDLE__ TIM handle.
1453 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1454 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
1455 * or Encoder mode.
1456 */
1457#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1458
1459/**
1460 * @brief Set the TIM Prescaler on runtime.
1461 * @param __HANDLE__ TIM handle.
1462 * @param __PRESC__ specifies the Prescaler new value.
1463 * @retval None
1464 */
1465#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1466
1467/**
1468 * @brief Set the TIM Counter Register value on runtime.
1469 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
1470 * case of 32 bits counter TIM instance.
1471 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
1472 * @param __HANDLE__ TIM handle.
1473 * @param __COUNTER__ specifies the Counter register new value.
1474 * @retval None
1475 */
1476#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1477
1478/**
1479 * @brief Get the TIM Counter Register value on runtime.
1480 * @param __HANDLE__ TIM handle.
1481 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1482 */
1483#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1484
1485/**
1486 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1487 * @param __HANDLE__ TIM handle.
1488 * @param __AUTORELOAD__ specifies the Counter register new value.
1489 * @retval None
1490 */
1491#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1492 do{ \
1493 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1494 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1495 } while(0)
1496
1497/**
1498 * @brief Get the TIM Autoreload Register value on runtime.
1499 * @param __HANDLE__ TIM handle.
1500 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1501 */
1502#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1503
1504/**
1505 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
1506 * @param __HANDLE__ TIM handle.
1507 * @param __CKD__ specifies the clock division value.
1508 * This parameter can be one of the following value:
1509 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1510 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1511 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1512 * @retval None
1513 */
1514#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1515 do{ \
1516 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1517 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1518 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1519 } while(0)
1520
1521/**
1522 * @brief Get the TIM Clock Division value on runtime.
1523 * @param __HANDLE__ TIM handle.
1524 * @retval The clock division can be one of the following values:
1525 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1526 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1527 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1528 */
1529#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1530
1531/**
1532 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
1533 * function.
1534 * @param __HANDLE__ TIM handle.
1535 * @param __CHANNEL__ TIM Channels to be configured.
1536 * This parameter can be one of the following values:
1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1541 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
1542 * This parameter can be one of the following values:
1543 * @arg TIM_ICPSC_DIV1: no prescaler
1544 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1545 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1546 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1547 * @retval None
1548 */
1549#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1550 do{ \
1551 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1552 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1553 } while(0)
1554
1555/**
1556 * @brief Get the TIM Input Capture prescaler on runtime.
1557 * @param __HANDLE__ TIM handle.
1558 * @param __CHANNEL__ TIM Channels to be configured.
1559 * This parameter can be one of the following values:
1560 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1561 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1562 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1563 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1564 * @retval The input capture prescaler can be one of the following values:
1565 * @arg TIM_ICPSC_DIV1: no prescaler
1566 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1567 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1568 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1569 */
1570#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1571 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1572 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1573 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1574 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1575
1576/**
1577 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1578 * @param __HANDLE__ TIM handle.
1579 * @param __CHANNEL__ TIM Channels to be configured.
1580 * This parameter can be one of the following values:
1581 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1582 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1583 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1584 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1585 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1586 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1587 * @param __COMPARE__ specifies the Capture Compare register new value.
1588 * @retval None
1589 */
1590#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1591 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1592 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1593 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1594 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1595 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1596 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1597
1598/**
1599 * @brief Get the TIM Capture Compare Register value on runtime.
1600 * @param __HANDLE__ TIM handle.
1601 * @param __CHANNEL__ TIM Channel associated with the capture compare register
1602 * This parameter can be one of the following values:
1603 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1604 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1605 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1606 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1607 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
1608 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
1609 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1610 */
1611#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1612 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1613 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1614 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1615 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1616 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1617 ((__HANDLE__)->Instance->CCR6))
1618
1619/**
1620 * @brief Set the TIM Output compare preload.
1621 * @param __HANDLE__ TIM handle.
1622 * @param __CHANNEL__ TIM Channels to be configured.
1623 * This parameter can be one of the following values:
1624 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1625 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1626 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1627 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1628 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1629 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1630 * @retval None
1631 */
1632#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1633 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1634 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1635 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1636 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1637 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1638 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1639
1640/**
1641 * @brief Reset the TIM Output compare preload.
1642 * @param __HANDLE__ TIM handle.
1643 * @param __CHANNEL__ TIM Channels to be configured.
1644 * This parameter can be one of the following values:
1645 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1646 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1647 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1648 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1649 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1650 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1651 * @retval None
1652 */
1653#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1654 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1655 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1656 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1657 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1658 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1659 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1660
1661/**
1662 * @brief Enable fast mode for a given channel.
1663 * @param __HANDLE__ TIM handle.
1664 * @param __CHANNEL__ TIM Channels to be configured.
1665 * This parameter can be one of the following values:
1666 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1667 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1668 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1669 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1670 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1671 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1672 * @note When fast mode is enabled an active edge on the trigger input acts
1673 * like a compare match on CCx output. Delay to sample the trigger
1674 * input and to activate CCx output is reduced to 3 clock cycles.
1675 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
1676 * @retval None
1677 */
1678#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1679 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1680 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1681 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1682 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
1683 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
1684 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
1685
1686/**
1687 * @brief Disable fast mode for a given channel.
1688 * @param __HANDLE__ TIM handle.
1689 * @param __CHANNEL__ TIM Channels to be configured.
1690 * This parameter can be one of the following values:
1691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1693 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1694 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1695 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1696 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1697 * @note When fast mode is disabled CCx output behaves normally depending
1698 * on counter and CCRx values even when the trigger is ON. The minimum
1699 * delay to activate CCx output when an active edge occurs on the
1700 * trigger input is 5 clock cycles.
1701 * @retval None
1702 */
1703#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1704 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1705 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1706 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1707 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1708 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1709 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1710
1711/**
1712 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1713 * @param __HANDLE__ TIM handle.
1714 * @note When the URS bit of the TIMx_CR1 register is set, only counter
1715 * overflow/underflow generates an update interrupt or DMA request (if
1716 * enabled)
1717 * @retval None
1718 */
1719#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1720
1721/**
1722 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1723 * @param __HANDLE__ TIM handle.
1724 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
1725 * following events generate an update interrupt or DMA request (if
1726 * enabled):
1727 * _ Counter overflow underflow
1728 * _ Setting the UG bit
1729 * _ Update generation through the slave mode controller
1730 * @retval None
1731 */
1732#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1733
1734/**
1735 * @brief Set the TIM Capture x input polarity on runtime.
1736 * @param __HANDLE__ TIM handle.
1737 * @param __CHANNEL__ TIM Channels to be configured.
1738 * This parameter can be one of the following values:
1739 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1740 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1741 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1742 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1743 * @param __POLARITY__ Polarity for TIx source
1744 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1745 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1746 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1747 * @retval None
1748 */
1749#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1750 do{ \
1751 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1752 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1753 }while(0)
1754
1755/** @brief Select the Capture/compare DMA request source.
1756 * @param __HANDLE__ specifies the TIM Handle.
1757 * @param __CCDMA__ specifies Capture/compare DMA request source
1758 * This parameter can be one of the following values:
1759 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
1760 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
1761 * @retval None
1762 */
1763#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
1764 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
1765
1766/**
1767 * @}
1768 */
1769/* End of exported macros ----------------------------------------------------*/
1770
1771/* Private constants ---------------------------------------------------------*/
1772/** @defgroup TIM_Private_Constants TIM Private Constants
1773 * @{
1774 */
1775/* The counter of a timer instance is disabled only if all the CCx and CCxN
1776 channels have been disabled */
1777#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \
1778 TIM_CCER_CC5E | TIM_CCER_CC6E))
1779#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1780/**
1781 * @}
1782 */
1783/* End of private constants --------------------------------------------------*/
1784
1785/* Private macros ------------------------------------------------------------*/
1786/** @defgroup TIM_Private_Macros TIM Private Macros
1787 * @{
1788 */
1789#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1790 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1791
1792#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1793 ((__BASE__) == TIM_DMABASE_CR2) || \
1794 ((__BASE__) == TIM_DMABASE_SMCR) || \
1795 ((__BASE__) == TIM_DMABASE_DIER) || \
1796 ((__BASE__) == TIM_DMABASE_SR) || \
1797 ((__BASE__) == TIM_DMABASE_EGR) || \
1798 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1799 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1800 ((__BASE__) == TIM_DMABASE_CCER) || \
1801 ((__BASE__) == TIM_DMABASE_CNT) || \
1802 ((__BASE__) == TIM_DMABASE_PSC) || \
1803 ((__BASE__) == TIM_DMABASE_ARR) || \
1804 ((__BASE__) == TIM_DMABASE_RCR) || \
1805 ((__BASE__) == TIM_DMABASE_CCR1) || \
1806 ((__BASE__) == TIM_DMABASE_CCR2) || \
1807 ((__BASE__) == TIM_DMABASE_CCR3) || \
1808 ((__BASE__) == TIM_DMABASE_CCR4) || \
1809 ((__BASE__) == TIM_DMABASE_BDTR) || \
1810 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1811 ((__BASE__) == TIM_DMABASE_CCR5) || \
1812 ((__BASE__) == TIM_DMABASE_CCR6) || \
1813 ((__BASE__) == TIM_DMABASE_AF1) || \
1814 ((__BASE__) == TIM_DMABASE_AF2) || \
1815 ((__BASE__) == TIM_DMABASE_TISEL))
1816
1817
1818#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1819
1820#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1821 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1822 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1823 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1824 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1825
1826#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
1827 ((__MODE__) == TIM_UIFREMAP_ENABLE))
1828
1829#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1830 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1831 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1832
1833#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1834 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1835
1836#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1837 ((__STATE__) == TIM_OCFAST_ENABLE))
1838
1839#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1840 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1841
1842#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1843 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1844
1845#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1846 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1847
1848#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1849 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1850
1851#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1852 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1853
1854#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1855 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1856 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1857
1858#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1859 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1860 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1861
1862#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1863 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1864 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1865 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1866
1867#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
1868 ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
1869 ((__CHANNEL__) != (TIM_CHANNEL_6)))
1870
1871#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1872 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1873
1874#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1875 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1876 ((__MODE__) == TIM_ENCODERMODE_TI12))
1877
1878#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1879
1880#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1881 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1882 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1883 ((__CHANNEL__) == TIM_CHANNEL_4) || \
1884 ((__CHANNEL__) == TIM_CHANNEL_5) || \
1885 ((__CHANNEL__) == TIM_CHANNEL_6) || \
1886 ((__CHANNEL__) == TIM_CHANNEL_ALL))
1887
1888#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1889 ((__CHANNEL__) == TIM_CHANNEL_2))
1890
1891#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
1892 (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
1893 ((__PERIOD__) > 0U))
1894
1895#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1896 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1897 ((__CHANNEL__) == TIM_CHANNEL_3))
1898
1899#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1900 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1901 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1902 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1903 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1904 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1905 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1906 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1907 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1908 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
1909
1910#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1911 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1912 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1913 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1914 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1915
1916#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1917 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1918 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1919 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1920
1921#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1922
1923#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1924 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1925
1926#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1927 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1928 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1929 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1930
1931#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1932
1933#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1934 ((__STATE__) == TIM_OSSR_DISABLE))
1935
1936#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1937 ((__STATE__) == TIM_OSSI_DISABLE))
1938
1939#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1940 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1941 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1942 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1943
1944#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1945
1946#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1947 ((__STATE__) == TIM_BREAK_DISABLE))
1948
1949#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1950 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1951#if defined(TIM_BDTR_BKBID)
1952
1953#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
1954 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
1955
1956#endif /* TIM_BDTR_BKBID */
1957
1958#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1959 ((__STATE__) == TIM_BREAK2_DISABLE))
1960
1961#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1962 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1963#if defined(TIM_BDTR_BKBID)
1964
1965#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
1966 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
1967
1968#endif /* TIM_BDTR_BKBID */
1969
1970#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1971 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1972
1973#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1974
1975#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1976 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1977 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1978 ((__SOURCE__) == TIM_TRGO_OC1) || \
1979 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1980 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1981 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1982 ((__SOURCE__) == TIM_TRGO_OC4REF))
1983
1984#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1985 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1986 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1987 ((__SOURCE__) == TIM_TRGO2_OC1) || \
1988 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1989 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1990 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1991 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1992 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1993 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1994 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1995 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1996 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1997 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1998 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1999 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
2000 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
2001
2002#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
2003 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
2004
2005#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
2006 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
2007 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
2008 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
2009 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
2010 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2011
2012#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
2013 ((__MODE__) == TIM_OCMODE_PWM2) || \
2014 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
2015 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
2016 ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
2017 ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
2018
2019#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
2020 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
2021 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
2022 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
2023 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
2024 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
2025 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
2026 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
2027
2028#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2029 ((__SELECTION__) == TIM_TS_ITR1) || \
2030 ((__SELECTION__) == TIM_TS_ITR2) || \
2031 ((__SELECTION__) == TIM_TS_ITR3) || \
2032 ((__SELECTION__) == TIM_TS_ITR4) || \
2033 ((__SELECTION__) == TIM_TS_ITR5) || \
2034 ((__SELECTION__) == TIM_TS_ITR6) || \
2035 ((__SELECTION__) == TIM_TS_ITR7) || \
2036 ((__SELECTION__) == TIM_TS_ITR8) || \
2037 ((__SELECTION__) == TIM_TS_ITR12) || \
2038 ((__SELECTION__) == TIM_TS_ITR13) || \
2039 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
2040 ((__SELECTION__) == TIM_TS_TI1FP1) || \
2041 ((__SELECTION__) == TIM_TS_TI2FP2) || \
2042 ((__SELECTION__) == TIM_TS_ETRF))
2043
2044#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2045 ((__SELECTION__) == TIM_TS_ITR1) || \
2046 ((__SELECTION__) == TIM_TS_ITR2) || \
2047 ((__SELECTION__) == TIM_TS_ITR3) || \
2048 ((__SELECTION__) == TIM_TS_ITR4) || \
2049 ((__SELECTION__) == TIM_TS_ITR5) || \
2050 ((__SELECTION__) == TIM_TS_ITR6) || \
2051 ((__SELECTION__) == TIM_TS_ITR7) || \
2052 ((__SELECTION__) == TIM_TS_ITR8) || \
2053 ((__SELECTION__) == TIM_TS_ITR12) || \
2054 ((__SELECTION__) == TIM_TS_ITR13) || \
2055 ((__SELECTION__) == TIM_TS_NONE))
2056
2057#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
2058 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
2059 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
2060 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
2061 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
2062
2063#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
2064 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
2065 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
2066 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
2067
2068#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2069
2070#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
2071 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2072
2073#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
2074 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
2075 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
2076 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
2077 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
2078 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
2079 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
2080 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
2081 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
2082 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
2083 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
2084 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
2085 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
2086 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
2087 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
2088 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
2089 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
2090 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
2091
2092#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2093
2094#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2095
2096#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
2097
2098#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
2099 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
2100 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
2101 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2102
2103#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
2104 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2105
2106#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2107 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
2108 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
2109 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
2110 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
2111
2112#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2113 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
2114 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
2115 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
2116 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
2117
2118#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2119 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
2120 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
2121 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
2122 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
2123
2124#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2125 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2126 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2127 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2128 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2129
2130#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
2131 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
2132 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
2133 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
2134 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
2135 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
2136 (__HANDLE__)->ChannelState[5])
2137
2138#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2139 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
2140 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
2141 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
2142 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
2143 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
2144 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
2145
2146#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\
2147 do {\
2148 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
2149 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
2150 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
2151 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
2152 (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
2153 (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
2154 } while(0)
2155
2156#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
2157 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
2158 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
2159 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
2160 (__HANDLE__)->ChannelNState[3])
2161
2162#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2163 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
2164 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
2165 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
2166 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
2167
2168#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\
2169 do {\
2170 (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
2171 (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
2172 (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
2173 (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
2174 } while(0)
2175
2176/**
2177 * @}
2178 */
2179/* End of private macros -----------------------------------------------------*/
2180
2181/* Include TIM HAL Extended module */
2182#include "stm32h7xx_hal_tim_ex.h"
2183
2184/* Exported functions --------------------------------------------------------*/
2185/** @addtogroup TIM_Exported_Functions TIM Exported Functions
2186 * @{
2187 */
2188
2189/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
2190 * @brief Time Base functions
2191 * @{
2192 */
2193/* Time Base functions ********************************************************/
2194HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2195HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2196void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2197void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2198/* Blocking mode: Polling */
2199HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2200HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2201/* Non-Blocking mode: Interrupt */
2202HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2203HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2204/* Non-Blocking mode: DMA */
2205HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
2206HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2207/**
2208 * @}
2209 */
2210
2211/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
2212 * @brief TIM Output Compare functions
2213 * @{
2214 */
2215/* Timer Output Compare functions *********************************************/
2216HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2217HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2218void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2219void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2220/* Blocking mode: Polling */
2221HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2222HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2223/* Non-Blocking mode: Interrupt */
2224HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2225HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2226/* Non-Blocking mode: DMA */
2227HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
2228 uint16_t Length);
2229HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2230/**
2231 * @}
2232 */
2233
2234/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
2235 * @brief TIM PWM functions
2236 * @{
2237 */
2238/* Timer PWM functions ********************************************************/
2239HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2240HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2241void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2242void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2243/* Blocking mode: Polling */
2244HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2245HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2246/* Non-Blocking mode: Interrupt */
2247HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2248HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2249/* Non-Blocking mode: DMA */
2250HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
2251 uint16_t Length);
2252HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2253/**
2254 * @}
2255 */
2256
2257/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
2258 * @brief TIM Input Capture functions
2259 * @{
2260 */
2261/* Timer Input Capture functions **********************************************/
2262HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2263HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2264void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2265void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2266/* Blocking mode: Polling */
2267HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2268HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2269/* Non-Blocking mode: Interrupt */
2270HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2271HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2272/* Non-Blocking mode: DMA */
2273HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2274HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2275/**
2276 * @}
2277 */
2278
2279/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2280 * @brief TIM One Pulse functions
2281 * @{
2282 */
2283/* Timer One Pulse functions **************************************************/
2284HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2285HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2286void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2287void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2288/* Blocking mode: Polling */
2289HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2290HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2291/* Non-Blocking mode: Interrupt */
2292HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2293HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2294/**
2295 * @}
2296 */
2297
2298/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2299 * @brief TIM Encoder functions
2300 * @{
2301 */
2302/* Timer Encoder functions ****************************************************/
2303HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
2304HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2305void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2306void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2307/* Blocking mode: Polling */
2308HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2309HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2310/* Non-Blocking mode: Interrupt */
2311HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2312HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2313/* Non-Blocking mode: DMA */
2314HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2315 uint32_t *pData2, uint16_t Length);
2316HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2317/**
2318 * @}
2319 */
2320
2321/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2322 * @brief IRQ handler management
2323 * @{
2324 */
2325/* Interrupt Handler functions ***********************************************/
2326void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2327/**
2328 * @}
2329 */
2330
2331/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2332 * @brief Peripheral Control functions
2333 * @{
2334 */
2335/* Control functions *********************************************************/
2336HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
2337 uint32_t Channel);
2338HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
2339 uint32_t Channel);
2340HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
2341 uint32_t Channel);
2342HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2343 uint32_t OutputChannel, uint32_t InputChannel);
2344HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
2345 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
2346 uint32_t Channel);
2347HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
2348HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2349HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
2350HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
2351HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2352 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2353 uint32_t BurstLength);
2354HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2355 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2356 uint32_t BurstLength, uint32_t DataLength);
2357HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2358HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2359 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2360HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2361 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
2362 uint32_t BurstLength, uint32_t DataLength);
2363HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2364HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2365uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
2366/**
2367 * @}
2368 */
2369
2370/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2371 * @brief TIM Callbacks functions
2372 * @{
2373 */
2374/* Callback in non blocking modes (Interrupt and DMA) *************************/
2375void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2376void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2377void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2378void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2379void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2380void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2381void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2382void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2383void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2384void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2385
2386/* Callbacks Register/UnRegister functions ***********************************/
2387#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2388HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2389 pTIM_CallbackTypeDef pCallback);
2390HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2391#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2392
2393/**
2394 * @}
2395 */
2396
2397/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2398 * @brief Peripheral State functions
2399 * @{
2400 */
2401/* Peripheral State functions ************************************************/
2402HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
2403HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
2404HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
2405HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
2406HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
2407HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
2408
2409/* Peripheral Channel state functions ************************************************/
2410HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
2411HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel);
2412HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
2413/**
2414 * @}
2415 */
2416
2417/**
2418 * @}
2419 */
2420/* End of exported functions -------------------------------------------------*/
2421
2422/* Private functions----------------------------------------------------------*/
2423/** @defgroup TIM_Private_Functions TIM Private Functions
2424 * @{
2425 */
2426void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
2427void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2428void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
2429void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2430 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2431
2432void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2433void TIM_DMAError(DMA_HandleTypeDef *hdma);
2434void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2435void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2436void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2437
2438#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2439void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2440#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2441
2442/**
2443 * @}
2444 */
2445/* End of private functions --------------------------------------------------*/
2446
2447/**
2448 * @}
2449 */
2450
2451/**
2452 * @}
2453 */
2454
2455#ifdef __cplusplus
2456}
2457#endif
2458
2459#endif /* STM32H7xx_HAL_TIM_H */
__IO
#define __IO
Defines 'read / write' permissions.
Definition core_armv81mml.h:290
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_TIM_OnePulse_GetState
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
HAL_TIM_IC_GetState
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
HAL_TIM_GetChannelState
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Base_GetState
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_GetState
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
HAL_TIM_PWM_GetState
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
HAL_TIM_GetActiveChannel
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
HAL_TIM_DMABurstState
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
HAL_TIM_OC_GetState
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
HAL_TIM_Base_MspDeInit
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
TIM_Base MSP De-Initialization This function freeze the hardware resources used in this example.
Definition stm32h7xx_hal_msp.c:849
HAL_TIM_Base_Stop_IT
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Init
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start_DMA
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
HAL_TIM_Base_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Stop
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
HAL_TIM_Base_MspInit
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
TIM_Base MSP Initialization This function configures the hardware resources used in this example.
Definition stm32h7xx_hal_msp.c:730
HAL_TIM_Base_DeInit
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start_IT
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Start_DMA
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
HAL_TIM_OC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OC_MspDeInit
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Start
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OC_Init
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
HAL_TIM_OC_DeInit
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Stop
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OC_MspInit
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Stop_IT
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OC_Start_IT
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Stop_IT
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Start
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Init
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Start_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
HAL_TIM_PWM_MspDeInit
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
TIM_PWM MSP De-Initialization This function freeze the hardware resources used in this example.
Definition stm32h7xx_hal_msp.c:816
HAL_TIM_PWM_DeInit
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Start_IT
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Stop_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Stop
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_MspInit
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
TIM_PWM MSP Initialization This function configures the hardware resources used in this example.
Definition stm32h7xx_hal_msp.c:697
HAL_TIM_IC_Stop
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IC_MspInit
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_IC_DeInit
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_IC_Init
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
HAL_TIM_IC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IC_Start
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IC_Start_IT
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IC_Start_DMA
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_TIM_IC_MspDeInit
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_IC_Stop_IT
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OnePulse_Start
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_OnePulse_Init
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
HAL_TIM_OnePulse_MspInit
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_OnePulse_Stop_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_OnePulse_MspDeInit
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_OnePulse_Stop
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_OnePulse_DeInit
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_OnePulse_Start_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_Encoder_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_MspInit
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_Stop
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Start
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_MspDeInit
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_Start_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
HAL_TIM_Encoder_Start_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_DeInit
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_Init
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
HAL_TIM_Encoder_Stop_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IRQHandler
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
HAL_TIM_IC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
HAL_TIM_DMABurst_MultiWriteStart
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
HAL_TIM_PWM_ConfigChannel
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
HAL_TIM_DMABurst_WriteStart
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_TIM_DMABurst_ReadStart
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_TIM_DMABurst_ReadStop
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_TIM_SlaveConfigSynchro
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
HAL_TIM_SlaveConfigSynchro_IT
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
HAL_TIM_ReadCapturedValue
uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_DMABurst_MultiReadStart
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
HAL_TIM_ConfigTI1Input
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
HAL_TIM_DMABurst_WriteStop
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_TIM_OC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
HAL_TIM_ConfigClockSource
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
HAL_TIM_GenerateEvent
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
HAL_TIM_ConfigOCrefClear
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
HAL_TIM_OnePulse_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
HAL_TIM_PWM_PulseFinishedCallback
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
HAL_TIM_TriggerCallback
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
HAL_TIM_PeriodElapsedHalfCpltCallback
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_OC_DelayElapsedCallback
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
HAL_TIM_IC_CaptureHalfCpltCallback
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_ErrorCallback
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
HAL_TIM_TriggerHalfCpltCallback
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_IC_CaptureCallback
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
Definition board_time.c:50
HAL_TIM_PeriodElapsedCallback
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
Definition main.c:1127
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_ChannelStateTypeDef
HAL_TIM_ChannelStateTypeDef
TIM Channel States definition.
Definition stm32h7xx_hal_tim.h:321
HAL_TIM_DMABurstStateTypeDef
HAL_TIM_DMABurstStateTypeDef
DMA Burst States definition.
Definition stm32h7xx_hal_tim.h:331
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition stm32h7xx_hal_tim.h:341
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition stm32h7xx_hal_tim.h:309
HAL_TIM_CHANNEL_STATE_READY
@ HAL_TIM_CHANNEL_STATE_READY
TIM Channel ready for use.
Definition stm32h7xx_hal_tim.h:323
HAL_TIM_CHANNEL_STATE_RESET
@ HAL_TIM_CHANNEL_STATE_RESET
TIM Channel initial state.
Definition stm32h7xx_hal_tim.h:322
HAL_TIM_CHANNEL_STATE_BUSY
@ HAL_TIM_CHANNEL_STATE_BUSY
An internal process is ongoing on the TIM channel.
Definition stm32h7xx_hal_tim.h:324
HAL_DMA_BURST_STATE_BUSY
@ HAL_DMA_BURST_STATE_BUSY
Ongoing DMA Burst.
Definition stm32h7xx_hal_tim.h:334
HAL_DMA_BURST_STATE_READY
@ HAL_DMA_BURST_STATE_READY
DMA Burst ready for use.
Definition stm32h7xx_hal_tim.h:333
HAL_DMA_BURST_STATE_RESET
@ HAL_DMA_BURST_STATE_RESET
DMA Burst initial state.
Definition stm32h7xx_hal_tim.h:332
HAL_TIM_ACTIVE_CHANNEL_1
@ HAL_TIM_ACTIVE_CHANNEL_1
The active channel is 1.
Definition stm32h7xx_hal_tim.h:342
HAL_TIM_ACTIVE_CHANNEL_6
@ HAL_TIM_ACTIVE_CHANNEL_6
The active channel is 6.
Definition stm32h7xx_hal_tim.h:347
HAL_TIM_ACTIVE_CHANNEL_5
@ HAL_TIM_ACTIVE_CHANNEL_5
The active channel is 5.
Definition stm32h7xx_hal_tim.h:346
HAL_TIM_ACTIVE_CHANNEL_CLEARED
@ HAL_TIM_ACTIVE_CHANNEL_CLEARED
All active channels cleared.
Definition stm32h7xx_hal_tim.h:348
HAL_TIM_ACTIVE_CHANNEL_4
@ HAL_TIM_ACTIVE_CHANNEL_4
The active channel is 4.
Definition stm32h7xx_hal_tim.h:345
HAL_TIM_ACTIVE_CHANNEL_3
@ HAL_TIM_ACTIVE_CHANNEL_3
The active channel is 3.
Definition stm32h7xx_hal_tim.h:344
HAL_TIM_ACTIVE_CHANNEL_2
@ HAL_TIM_ACTIVE_CHANNEL_2
The active channel is 2.
Definition stm32h7xx_hal_tim.h:343
HAL_TIM_STATE_TIMEOUT
@ HAL_TIM_STATE_TIMEOUT
Timeout state.
Definition stm32h7xx_hal_tim.h:313
HAL_TIM_STATE_BUSY
@ HAL_TIM_STATE_BUSY
An internal process is ongoing.
Definition stm32h7xx_hal_tim.h:312
HAL_TIM_STATE_RESET
@ HAL_TIM_STATE_RESET
Peripheral not yet initialized or disabled.
Definition stm32h7xx_hal_tim.h:310
HAL_TIM_STATE_ERROR
@ HAL_TIM_STATE_ERROR
Reception process is ongoing.
Definition stm32h7xx_hal_tim.h:314
HAL_TIM_STATE_READY
@ HAL_TIM_STATE_READY
Peripheral Initialized and ready for use.
Definition stm32h7xx_hal_tim.h:311
TIM_ETR_SetConfig
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
TIM_DMACaptureHalfCplt
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
TIM_OC2_SetConfig
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
TIM_DMACaptureCplt
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
TIM_CCxChannelCmd
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
TIM_TI1_SetConfig
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
TIM_DMADelayPulseHalfCplt
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
TIM_DMAError
void TIM_DMAError(DMA_HandleTypeDef *hdma)
TIM_Base_SetConfig
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32h7xx_hal_def.h:40
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition stm32h7xx_hal_def.h:51
stm32h7xx_hal_tim_ex.h
Header file of TIM HAL Extended module.
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition stm32h7xx_hal_tim.h:47
TIM_Base_InitTypeDef::CounterMode
uint32_t CounterMode
Specifies the counter mode.
Definition stm32h7xx_hal_tim.h:51
TIM_Base_InitTypeDef::AutoReloadPreload
uint32_t AutoReloadPreload
Specifies the auto-reload preload.
Definition stm32h7xx_hal_tim.h:72
TIM_Base_InitTypeDef::Period
uint32_t Period
Specifies the period value to be loaded into the active Auto-Reload Register at the next update event...
Definition stm32h7xx_hal_tim.h:54
TIM_Base_InitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Specifies the repetition counter value.
Definition stm32h7xx_hal_tim.h:61
TIM_Base_InitTypeDef::ClockDivision
uint32_t ClockDivision
Specifies the clock division.
Definition stm32h7xx_hal_tim.h:58
TIM_Base_InitTypeDef::Prescaler
uint32_t Prescaler
Specifies the prescaler value used to divide the TIM clock.
Definition stm32h7xx_hal_tim.h:48
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition stm32h7xx_hal_tim.h:272
TIM_BreakDeadTimeConfigTypeDef::Break2Filter
uint32_t Break2Filter
TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF.
Definition stm32h7xx_hal_tim.h:295
TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode
uint32_t OffStateIDLEMode
TIM off state in IDLE mode, This parameter can be a value of TIM OSSI OffState Selection for Idle mod...
Definition stm32h7xx_hal_tim.h:275
TIM_BreakDeadTimeConfigTypeDef::DeadTime
uint32_t DeadTime
TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Definition stm32h7xx_hal_tim.h:279
TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode
uint32_t OffStateRunMode
TIM off state in run mode, This parameter can be a value of TIM OSSR OffState Selection for Run mode ...
Definition stm32h7xx_hal_tim.h:273
TIM_BreakDeadTimeConfigTypeDef::BreakState
uint32_t BreakState
TIM Break State, This parameter can be a value of TIM Break Input Enable.
Definition stm32h7xx_hal_tim.h:281
TIM_BreakDeadTimeConfigTypeDef::BreakFilter
uint32_t BreakFilter
Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data =...
Definition stm32h7xx_hal_tim.h:285
TIM_BreakDeadTimeConfigTypeDef::LockLevel
uint32_t LockLevel
TIM Lock level, This parameter can be a value of TIM Lock level.
Definition stm32h7xx_hal_tim.h:277
TIM_BreakDeadTimeConfigTypeDef::Break2State
uint32_t Break2State
TIM Break2 State, This parameter can be a value of TIM Break input 2 Enable.
Definition stm32h7xx_hal_tim.h:291
TIM_BreakDeadTimeConfigTypeDef::BreakPolarity
uint32_t BreakPolarity
TIM Break input polarity, This parameter can be a value of TIM Break Input Polarity.
Definition stm32h7xx_hal_tim.h:283
TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput
uint32_t AutomaticOutput
TIM Automatic Output Enable state, This parameter can be a value of TIM Automatic Output Enable.
Definition stm32h7xx_hal_tim.h:301
TIM_BreakDeadTimeConfigTypeDef::Break2Polarity
uint32_t Break2Polarity
TIM Break2 input polarity, This parameter can be a value of TIM Break Input 2 Polarity.
Definition stm32h7xx_hal_tim.h:293
TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition.
Definition stm32h7xx_hal_tim.h:214
TIM_ClearInputConfigTypeDef::ClearInputState
uint32_t ClearInputState
TIM clear Input state This parameter can be ENABLE or DISABLE.
Definition stm32h7xx_hal_tim.h:215
TIM_ClearInputConfigTypeDef::ClearInputPolarity
uint32_t ClearInputPolarity
TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity.
Definition stm32h7xx_hal_tim.h:219
TIM_ClearInputConfigTypeDef::ClearInputPrescaler
uint32_t ClearInputPrescaler
TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source,...
Definition stm32h7xx_hal_tim.h:221
TIM_ClearInputConfigTypeDef::ClearInputFilter
uint32_t ClearInputFilter
TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF.
Definition stm32h7xx_hal_tim.h:224
TIM_ClearInputConfigTypeDef::ClearInputSource
uint32_t ClearInputSource
TIM clear Input sources This parameter can be a value of TIM Clear Input Source.
Definition stm32h7xx_hal_tim.h:217
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition stm32h7xx_hal_tim.h:199
TIM_ClockConfigTypeDef::ClockSource
uint32_t ClockSource
TIM clock sources This parameter can be a value of TIM Clock Source.
Definition stm32h7xx_hal_tim.h:200
TIM_ClockConfigTypeDef::ClockPolarity
uint32_t ClockPolarity
TIM clock polarity This parameter can be a value of TIM Clock Polarity.
Definition stm32h7xx_hal_tim.h:202
TIM_ClockConfigTypeDef::ClockFilter
uint32_t ClockFilter
TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF.
Definition stm32h7xx_hal_tim.h:206
TIM_ClockConfigTypeDef::ClockPrescaler
uint32_t ClockPrescaler
TIM clock prescaler This parameter can be a value of TIM Clock Prescaler.
Definition stm32h7xx_hal_tim.h:204
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition stm32h7xx_hal_tim.h:166
TIM_Encoder_InitTypeDef::IC2Filter
uint32_t IC2Filter
Specifies the input capture filter.
Definition stm32h7xx_hal_tim.h:191
TIM_Encoder_InitTypeDef::IC1Polarity
uint32_t IC1Polarity
Specifies the active edge of the input signal.
Definition stm32h7xx_hal_tim.h:170
TIM_Encoder_InitTypeDef::IC1Filter
uint32_t IC1Filter
Specifies the input capture filter.
Definition stm32h7xx_hal_tim.h:179
TIM_Encoder_InitTypeDef::IC1Prescaler
uint32_t IC1Prescaler
Specifies the Input Capture Prescaler.
Definition stm32h7xx_hal_tim.h:176
TIM_Encoder_InitTypeDef::IC2Selection
uint32_t IC2Selection
Specifies the input.
Definition stm32h7xx_hal_tim.h:185
TIM_Encoder_InitTypeDef::IC1Selection
uint32_t IC1Selection
Specifies the input.
Definition stm32h7xx_hal_tim.h:173
TIM_Encoder_InitTypeDef::EncoderMode
uint32_t EncoderMode
Specifies the active edge of the input signal.
Definition stm32h7xx_hal_tim.h:167
TIM_Encoder_InitTypeDef::IC2Polarity
uint32_t IC2Polarity
Specifies the active edge of the input signal.
Definition stm32h7xx_hal_tim.h:182
TIM_Encoder_InitTypeDef::IC2Prescaler
uint32_t IC2Prescaler
Specifies the Input Capture Prescaler.
Definition stm32h7xx_hal_tim.h:188
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition stm32h7xx_hal_tim.h:359
TIM_HandleTypeDef::hdma
DMA_HandleTypeDef * hdma[7]
DMA Handlers array This array is accessed by a TIM DMA Handle Index.
Definition stm32h7xx_hal_tim.h:363
TIM_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Locking object.
Definition stm32h7xx_hal_tim.h:365
TIM_HandleTypeDef::State
__IO HAL_TIM_StateTypeDef State
TIM operation state.
Definition stm32h7xx_hal_tim.h:366
TIM_HandleTypeDef::Init
TIM_Base_InitTypeDef Init
TIM Time Base required parameters.
Definition stm32h7xx_hal_tim.h:361
TIM_HandleTypeDef::ChannelState
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]
TIM channel operation state.
Definition stm32h7xx_hal_tim.h:367
TIM_HandleTypeDef::DMABurstState
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState
DMA burst operation state.
Definition stm32h7xx_hal_tim.h:369
TIM_HandleTypeDef::ChannelNState
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]
TIM complementary channel operation state.
Definition stm32h7xx_hal_tim.h:368
TIM_HandleTypeDef::Instance
TIM_TypeDef * Instance
Register base address.
Definition stm32h7xx_hal_tim.h:360
TIM_HandleTypeDef::Channel
HAL_TIM_ActiveChannel Channel
Active channel.
Definition stm32h7xx_hal_tim.h:362
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition stm32h7xx_hal_tim.h:148
TIM_IC_InitTypeDef::ICPrescaler
uint32_t ICPrescaler
Specifies the Input Capture Prescaler.
Definition stm32h7xx_hal_tim.h:155
TIM_IC_InitTypeDef::ICSelection
uint32_t ICSelection
Specifies the input.
Definition stm32h7xx_hal_tim.h:152
TIM_IC_InitTypeDef::ICPolarity
uint32_t ICPolarity
Specifies the active edge of the input signal.
Definition stm32h7xx_hal_tim.h:149
TIM_IC_InitTypeDef::ICFilter
uint32_t ICFilter
Specifies the input capture filter.
Definition stm32h7xx_hal_tim.h:158
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition stm32h7xx_hal_tim.h:234
TIM_MasterConfigTypeDef::MasterSlaveMode
uint32_t MasterSlaveMode
Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode.
Definition stm32h7xx_hal_tim.h:239
TIM_MasterConfigTypeDef::MasterOutputTrigger2
uint32_t MasterOutputTrigger2
Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2...
Definition stm32h7xx_hal_tim.h:237
TIM_MasterConfigTypeDef::MasterOutputTrigger
uint32_t MasterOutputTrigger
Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection.
Definition stm32h7xx_hal_tim.h:235
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition stm32h7xx_hal_tim.h:80
TIM_OC_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Specifies the TIM Output Compare pin state during Idle state.
Definition stm32h7xx_hal_tim.h:103
TIM_OC_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Specifies the complementary output polarity.
Definition stm32h7xx_hal_tim.h:90
TIM_OC_InitTypeDef::OCFastMode
uint32_t OCFastMode
Specifies the Fast mode state.
Definition stm32h7xx_hal_tim.h:94
TIM_OC_InitTypeDef::OCPolarity
uint32_t OCPolarity
Specifies the output polarity.
Definition stm32h7xx_hal_tim.h:87
TIM_OC_InitTypeDef::Pulse
uint32_t Pulse
Specifies the pulse value to be loaded into the Capture Compare Register.
Definition stm32h7xx_hal_tim.h:84
TIM_OC_InitTypeDef::OCIdleState
uint32_t OCIdleState
Specifies the TIM Output Compare pin state during Idle state.
Definition stm32h7xx_hal_tim.h:99
TIM_OC_InitTypeDef::OCMode
uint32_t OCMode
Specifies the TIM mode.
Definition stm32h7xx_hal_tim.h:81
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition stm32h7xx_hal_tim.h:112
TIM_OnePulse_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Specifies the complementary output polarity.
Definition stm32h7xx_hal_tim.h:122
TIM_OnePulse_InitTypeDef::OCPolarity
uint32_t OCPolarity
Specifies the output polarity.
Definition stm32h7xx_hal_tim.h:119
TIM_OnePulse_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Specifies the TIM Output Compare pin state during Idle state.
Definition stm32h7xx_hal_tim.h:130
TIM_OnePulse_InitTypeDef::Pulse
uint32_t Pulse
Specifies the pulse value to be loaded into the Capture Compare Register.
Definition stm32h7xx_hal_tim.h:116
TIM_OnePulse_InitTypeDef::ICPolarity
uint32_t ICPolarity
Specifies the active edge of the input signal.
Definition stm32h7xx_hal_tim.h:134
TIM_OnePulse_InitTypeDef::ICFilter
uint32_t ICFilter
Specifies the input capture filter.
Definition stm32h7xx_hal_tim.h:140
TIM_OnePulse_InitTypeDef::ICSelection
uint32_t ICSelection
Specifies the input.
Definition stm32h7xx_hal_tim.h:137
TIM_OnePulse_InitTypeDef::OCIdleState
uint32_t OCIdleState
Specifies the TIM Output Compare pin state during Idle state.
Definition stm32h7xx_hal_tim.h:126
TIM_OnePulse_InitTypeDef::OCMode
uint32_t OCMode
Specifies the TIM mode.
Definition stm32h7xx_hal_tim.h:113
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition stm32h7xx_hal_tim.h:252
TIM_SlaveConfigTypeDef::TriggerFilter
uint32_t TriggerFilter
Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF.
Definition stm32h7xx_hal_tim.h:261
TIM_SlaveConfigTypeDef::SlaveMode
uint32_t SlaveMode
Slave mode selection This parameter can be a value of TIM Slave mode.
Definition stm32h7xx_hal_tim.h:253
TIM_SlaveConfigTypeDef::TriggerPrescaler
uint32_t TriggerPrescaler
Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler.
Definition stm32h7xx_hal_tim.h:259
TIM_SlaveConfigTypeDef::InputTrigger
uint32_t InputTrigger
Input Trigger source This parameter can be a value of TIM Trigger Selection.
Definition stm32h7xx_hal_tim.h:255
TIM_SlaveConfigTypeDef::TriggerPolarity
uint32_t TriggerPolarity
Input Trigger polarity This parameter can be a value of TIM Trigger Polarity.
Definition stm32h7xx_hal_tim.h:257
TIM_TypeDef
TIM.
Definition stm32h723xx.h:1525