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TIM Output Compare and PWM Modes
STM32H7xx_HAL_Driver » TIM » TIM Exported Constants
Collaboration diagram for TIM Output Compare and PWM Modes:

Macros

#define TIM_OCMODE_TIMING   0x00000000U
 Frozen.
#define TIM_OCMODE_ACTIVE   TIM_CCMR1_OC1M_0
 Set channel to active level on match.
#define TIM_OCMODE_INACTIVE   TIM_CCMR1_OC1M_1
 Set channel to inactive level on match.
#define TIM_OCMODE_TOGGLE   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
 Toggle.
#define TIM_OCMODE_PWM1   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
 PWM mode 1.
#define TIM_OCMODE_PWM2   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
 PWM mode 2.
#define TIM_OCMODE_FORCED_ACTIVE   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
 Force active level.
#define TIM_OCMODE_FORCED_INACTIVE   TIM_CCMR1_OC1M_2
 Force inactive level.
#define TIM_OCMODE_RETRIGERRABLE_OPM1   TIM_CCMR1_OC1M_3
 Retrigerrable OPM mode 1.
#define TIM_OCMODE_RETRIGERRABLE_OPM2   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
 Retrigerrable OPM mode 2.
#define TIM_OCMODE_COMBINED_PWM1   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
 Combined PWM mode 1.
#define TIM_OCMODE_COMBINED_PWM2   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
 Combined PWM mode 2.
#define TIM_OCMODE_ASYMMETRIC_PWM1   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
 Asymmetric PWM mode 1.
#define TIM_OCMODE_ASYMMETRIC_PWM2   TIM_CCMR1_OC1M
 Asymmetric PWM mode 2.

Detailed Description

Macro Definition Documentation

◆ TIM_OCMODE_ACTIVE

#define TIM_OCMODE_ACTIVE   TIM_CCMR1_OC1M_0

Set channel to active level on match.

Definition at line 1028 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_ASYMMETRIC_PWM1

#define TIM_OCMODE_ASYMMETRIC_PWM1   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1.

Definition at line 1039 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_ASYMMETRIC_PWM2

#define TIM_OCMODE_ASYMMETRIC_PWM2   TIM_CCMR1_OC1M

Asymmetric PWM mode 2.

Definition at line 1040 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_COMBINED_PWM1

#define TIM_OCMODE_COMBINED_PWM1   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1.

Definition at line 1037 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_COMBINED_PWM2

#define TIM_OCMODE_COMBINED_PWM2   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2.

Definition at line 1038 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_FORCED_ACTIVE

#define TIM_OCMODE_FORCED_ACTIVE   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Force active level.

Definition at line 1033 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_FORCED_INACTIVE

#define TIM_OCMODE_FORCED_INACTIVE   TIM_CCMR1_OC1M_2

Force inactive level.

Definition at line 1034 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_INACTIVE

#define TIM_OCMODE_INACTIVE   TIM_CCMR1_OC1M_1

Set channel to inactive level on match.

Definition at line 1029 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_PWM1

#define TIM_OCMODE_PWM1   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

PWM mode 1.

Definition at line 1031 of file stm32h7xx_hal_tim.h.

Referenced by MX_TIM1_Init(), and MX_TIM3_Init().

◆ TIM_OCMODE_PWM2

#define TIM_OCMODE_PWM2   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

PWM mode 2.

Definition at line 1032 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_RETRIGERRABLE_OPM1

#define TIM_OCMODE_RETRIGERRABLE_OPM1   TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1.

Definition at line 1035 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_RETRIGERRABLE_OPM2

#define TIM_OCMODE_RETRIGERRABLE_OPM2   (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2.

Definition at line 1036 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_TIMING

#define TIM_OCMODE_TIMING   0x00000000U

Frozen.

Definition at line 1027 of file stm32h7xx_hal_tim.h.

◆ TIM_OCMODE_TOGGLE

#define TIM_OCMODE_TOGGLE   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Toggle.

Definition at line 1030 of file stm32h7xx_hal_tim.h.