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ism330dhcx_reg.h
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1/**
2 ******************************************************************************
3 * @file ism330dhcx_reg.h
4 * @author Sensor Solutions Software Team
5 * @brief This file contains all the functions prototypes for the
6 * ism330dhcx_reg.c driver.
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
11 * All rights reserved.</center></h2>
12 *
13 * This software component is licensed by ST under BSD 3-Clause license,
14 * the "License"; You may not use this file except in compliance with the
15 * License. You may obtain a copy of the License at:
16 * opensource.org/licenses/BSD-3-Clause
17 *
18 ******************************************************************************
19 */
20
21/* Define to prevent recursive inclusion -------------------------------------*/
22#ifndef ISM330DHCX_REGS_H
23#define ISM330DHCX_REGS_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/* Includes ------------------------------------------------------------------*/
30#include <stdint.h>
31#include <stddef.h>
32#include <math.h>
33
34
35/** @addtogroup ISM330DHCX
36 * @{
37 *
38 */
39
40/** @defgroup Endianness definitions
41 * @{
42 *
43 */
44
45#ifndef DRV_BYTE_ORDER
46#ifndef __BYTE_ORDER__
47
48#define DRV_LITTLE_ENDIAN 1234
49#define DRV_BIG_ENDIAN 4321
50
51/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
52 * by uncommenting the define which fits your platform endianness
53 */
54#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
55//#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
56
57#else /* defined __BYTE_ORDER__ */
58
59#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
60#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
61#define DRV_BYTE_ORDER __BYTE_ORDER__
62
63#endif /* __BYTE_ORDER__*/
64#endif /* DRV_BYTE_ORDER */
65
66/**
67 * @}
68 *
69 */
70
71/** @defgroup STMicroelectronics sensors common types
72 * @{
73 *
74 */
75
76#ifndef MEMS_SHARED_TYPES
77#define MEMS_SHARED_TYPES
78
79typedef struct
80{
81#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
82 uint8_t bit0 : 1;
83 uint8_t bit1 : 1;
84 uint8_t bit2 : 1;
85 uint8_t bit3 : 1;
86 uint8_t bit4 : 1;
87 uint8_t bit5 : 1;
88 uint8_t bit6 : 1;
89 uint8_t bit7 : 1;
90#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
91 uint8_t bit7 : 1;
92 uint8_t bit6 : 1;
93 uint8_t bit5 : 1;
94 uint8_t bit4 : 1;
95 uint8_t bit3 : 1;
96 uint8_t bit2 : 1;
97 uint8_t bit1 : 1;
98 uint8_t bit0 : 1;
99#endif /* DRV_BYTE_ORDER */
100} bitwise_t;
101
102#define PROPERTY_DISABLE (0U)
103#define PROPERTY_ENABLE (1U)
104
105/** @addtogroup Interfaces_Functions
106 * @brief This section provide a set of functions used to read and
107 * write a generic register of the device.
108 * MANDATORY: return 0 -> no Error.
109 * @{
110 *
111 */
112
113typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
114typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
115
116typedef struct
117{
118 /** Component mandatory fields **/
119 stmdev_write_ptr write_reg;
120 stmdev_read_ptr read_reg;
121 /** Customizable optional pointer **/
122 void *handle;
123} stmdev_ctx_t;
124
125/**
126 * @}
127 *
128 */
129
130#endif /* MEMS_SHARED_TYPES */
131
132#ifndef MEMS_UCF_SHARED_TYPES
133#define MEMS_UCF_SHARED_TYPES
134
135/** @defgroup Generic address-data structure definition
136 * @brief This structure is useful to load a predefined configuration
137 * of a sensor.
138 * You can create a sensor configuration by your own or using
139 * Unico / Unicleo tools available on STMicroelectronics
140 * web site.
141 *
142 * @{
143 *
144 */
145
146typedef struct
147{
148 uint8_t address;
149 uint8_t data;
150} ucf_line_t;
151
152/**
153 * @}
154 *
155 */
156
157#endif /* MEMS_UCF_SHARED_TYPES */
158
159/**
160 * @}
161 *
162 */
163
164/** @defgroup ISM330DHCX Infos
165 * @{
166 *
167 */
168
169/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/
170#define ISM330DHCX_I2C_ADD_L 0xD5U
171#define ISM330DHCX_I2C_ADD_H 0xD7U
172
173/** Device Identification (Who am I) **/
174#define ISM330DHCX_ID 0x6BU
175
176/**
177 * @}
178 *
179 */
180
181#define ISM330DHCX_FUNC_CFG_ACCESS 0x01U
182typedef struct
183{
184#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
185 uint8_t not_used_01 : 6;
186uint8_t reg_access :
187 2; /* shub_reg_access + func_cfg_access */
188#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
189uint8_t reg_access :
190 2; /* shub_reg_access + func_cfg_access */
191 uint8_t not_used_01 : 6;
192#endif /* DRV_BYTE_ORDER */
193} ism330dhcx_func_cfg_access_t;
194
195#define ISM330DHCX_PIN_CTRL 0x02U
196typedef struct
197{
198#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
199 uint8_t not_used_01 : 6;
200 uint8_t sdo_pu_en : 1;
201 uint8_t ois_pu_dis : 1;
202#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
203 uint8_t ois_pu_dis : 1;
204 uint8_t sdo_pu_en : 1;
205 uint8_t not_used_01 : 6;
206#endif /* DRV_BYTE_ORDER */
207} ism330dhcx_pin_ctrl_t;
208
209#define ISM330DHCX_FIFO_CTRL1 0x07U
210typedef struct
211{
212 uint8_t wtm : 8;
213} ism330dhcx_fifo_ctrl1_t;
214
215#define ISM330DHCX_FIFO_CTRL2 0x08U
216typedef struct
217{
218#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
219 uint8_t wtm : 1;
220 uint8_t uncoptr_rate : 2;
221 uint8_t not_used_01 : 1;
222 uint8_t odrchg_en : 1;
223 uint8_t not_used_02 : 1;
224 uint8_t fifo_compr_rt_en : 1;
225 uint8_t stop_on_wtm : 1;
226#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
227 uint8_t stop_on_wtm : 1;
228 uint8_t fifo_compr_rt_en : 1;
229 uint8_t not_used_02 : 1;
230 uint8_t odrchg_en : 1;
231 uint8_t not_used_01 : 1;
232 uint8_t uncoptr_rate : 2;
233 uint8_t wtm : 1;
234#endif /* DRV_BYTE_ORDER */
235} ism330dhcx_fifo_ctrl2_t;
236
237#define ISM330DHCX_FIFO_CTRL3 0x09U
238typedef struct
239{
240#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
241 uint8_t bdr_xl : 4;
242 uint8_t bdr_gy : 4;
243#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
244 uint8_t bdr_gy : 4;
245 uint8_t bdr_xl : 4;
246#endif /* DRV_BYTE_ORDER */
247} ism330dhcx_fifo_ctrl3_t;
248
249#define ISM330DHCX_FIFO_CTRL4 0x0AU
250typedef struct
251{
252#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
253 uint8_t fifo_mode : 3;
254 uint8_t not_used_01 : 1;
255 uint8_t odr_t_batch : 2;
256 uint8_t odr_ts_batch : 2;
257#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
258 uint8_t odr_ts_batch : 2;
259 uint8_t odr_t_batch : 2;
260 uint8_t not_used_01 : 1;
261 uint8_t fifo_mode : 3;
262#endif /* DRV_BYTE_ORDER */
263} ism330dhcx_fifo_ctrl4_t;
264
265#define ISM330DHCX_COUNTER_BDR_REG1 0x0BU
266typedef struct
267{
268#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
269 uint8_t cnt_bdr_th : 3;
270 uint8_t not_used_01 : 2;
271 uint8_t trig_counter_bdr : 1;
272 uint8_t rst_counter_bdr : 1;
273 uint8_t dataready_pulsed : 1;
274#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
275 uint8_t dataready_pulsed : 1;
276 uint8_t rst_counter_bdr : 1;
277 uint8_t trig_counter_bdr : 1;
278 uint8_t not_used_01 : 2;
279 uint8_t cnt_bdr_th : 3;
280#endif /* DRV_BYTE_ORDER */
281} ism330dhcx_counter_bdr_reg1_t;
282
283#define ISM330DHCX_COUNTER_BDR_REG2 0x0CU
284typedef struct
285{
286 uint8_t cnt_bdr_th : 8;
287} ism330dhcx_counter_bdr_reg2_t;
288
289#define ISM330DHCX_INT1_CTRL 0x0DU
290typedef struct
291{
292#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
293 uint8_t int1_drdy_xl : 1;
294 uint8_t int1_drdy_g : 1;
295 uint8_t int1_boot : 1;
296 uint8_t int1_fifo_th : 1;
297 uint8_t int1_fifo_ovr : 1;
298 uint8_t int1_fifo_full : 1;
299 uint8_t int1_cnt_bdr : 1;
300 uint8_t den_drdy_flag : 1;
301#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
302 uint8_t den_drdy_flag : 1;
303 uint8_t int1_cnt_bdr : 1;
304 uint8_t int1_fifo_full : 1;
305 uint8_t int1_fifo_ovr : 1;
306 uint8_t int1_fifo_th : 1;
307 uint8_t int1_boot : 1;
308 uint8_t int1_drdy_g : 1;
309 uint8_t int1_drdy_xl : 1;
310#endif /* DRV_BYTE_ORDER */
311} ism330dhcx_int1_ctrl_t;
312
313#define ISM330DHCX_INT2_CTRL 0x0EU
314typedef struct
315{
316#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
317 uint8_t int2_drdy_xl : 1;
318 uint8_t int2_drdy_g : 1;
319 uint8_t int2_drdy_temp : 1;
320 uint8_t int2_fifo_th : 1;
321 uint8_t int2_fifo_ovr : 1;
322 uint8_t int2_fifo_full : 1;
323 uint8_t int2_cnt_bdr : 1;
324 uint8_t not_used_01 : 1;
325#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
326 uint8_t not_used_01 : 1;
327 uint8_t int2_cnt_bdr : 1;
328 uint8_t int2_fifo_full : 1;
329 uint8_t int2_fifo_ovr : 1;
330 uint8_t int2_fifo_th : 1;
331 uint8_t int2_drdy_temp : 1;
332 uint8_t int2_drdy_g : 1;
333 uint8_t int2_drdy_xl : 1;
334#endif /* DRV_BYTE_ORDER */
335} ism330dhcx_int2_ctrl_t;
336
337#define ISM330DHCX_WHO_AM_I 0x0FU
338#define ISM330DHCX_CTRL1_XL 0x10U
339typedef struct
340{
341#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
342 uint8_t not_used_01 : 1;
343 uint8_t lpf2_xl_en : 1;
344 uint8_t fs_xl : 2;
345 uint8_t odr_xl : 4;
346#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
347 uint8_t odr_xl : 4;
348 uint8_t fs_xl : 2;
349 uint8_t lpf2_xl_en : 1;
350 uint8_t not_used_01 : 1;
351#endif /* DRV_BYTE_ORDER */
352} ism330dhcx_ctrl1_xl_t;
353
354#define ISM330DHCX_CTRL2_G 0x11U
355typedef struct
356{
357#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
358 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
359 uint8_t odr_g : 4;
360#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
361 uint8_t odr_g : 4;
362 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
363#endif /* DRV_BYTE_ORDER */
364} ism330dhcx_ctrl2_g_t;
365
366#define ISM330DHCX_CTRL3_C 0x12U
367typedef struct
368{
369#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
370 uint8_t sw_reset : 1;
371 uint8_t not_used_01 : 1;
372 uint8_t if_inc : 1;
373 uint8_t sim : 1;
374 uint8_t pp_od : 1;
375 uint8_t h_lactive : 1;
376 uint8_t bdu : 1;
377 uint8_t boot : 1;
378#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
379 uint8_t boot : 1;
380 uint8_t bdu : 1;
381 uint8_t h_lactive : 1;
382 uint8_t pp_od : 1;
383 uint8_t sim : 1;
384 uint8_t if_inc : 1;
385 uint8_t not_used_01 : 1;
386 uint8_t sw_reset : 1;
387#endif /* DRV_BYTE_ORDER */
388} ism330dhcx_ctrl3_c_t;
389
390#define ISM330DHCX_CTRL4_C 0x13U
391typedef struct
392{
393#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
394 uint8_t not_used_01 : 1;
395 uint8_t lpf1_sel_g : 1;
396 uint8_t i2c_disable : 1;
397 uint8_t drdy_mask : 1;
398 uint8_t not_used_02 : 1;
399 uint8_t int2_on_int1 : 1;
400 uint8_t sleep_g : 1;
401 uint8_t not_used_03 : 1;
402#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
403 uint8_t not_used_03 : 1;
404 uint8_t sleep_g : 1;
405 uint8_t int2_on_int1 : 1;
406 uint8_t not_used_02 : 1;
407 uint8_t drdy_mask : 1;
408 uint8_t i2c_disable : 1;
409 uint8_t lpf1_sel_g : 1;
410 uint8_t not_used_01 : 1;
411#endif /* DRV_BYTE_ORDER */
412} ism330dhcx_ctrl4_c_t;
413
414#define ISM330DHCX_CTRL5_C 0x14U
415typedef struct
416{
417#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
418 uint8_t st_xl : 2;
419 uint8_t st_g : 2;
420 uint8_t not_used_01 : 1;
421 uint8_t rounding : 2;
422 uint8_t not_used_02 : 1;
423#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
424 uint8_t not_used_02 : 1;
425 uint8_t rounding : 2;
426 uint8_t not_used_01 : 1;
427 uint8_t st_g : 2;
428 uint8_t st_xl : 2;
429#endif /* DRV_BYTE_ORDER */
430} ism330dhcx_ctrl5_c_t;
431
432#define ISM330DHCX_CTRL6_C 0x15U
433typedef struct
434{
435#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
436 uint8_t ftype : 3;
437 uint8_t usr_off_w : 1;
438 uint8_t xl_hm_mode : 1;
439uint8_t den_mode :
440 3; /* trig_en + lvl1_en + lvl2_en */
441#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
442uint8_t den_mode :
443 3; /* trig_en + lvl1_en + lvl2_en */
444 uint8_t xl_hm_mode : 1;
445 uint8_t usr_off_w : 1;
446 uint8_t ftype : 3;
447#endif /* DRV_BYTE_ORDER */
448} ism330dhcx_ctrl6_c_t;
449
450#define ISM330DHCX_CTRL7_G 0x16U
451typedef struct
452{
453#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
454 uint8_t ois_on : 1;
455 uint8_t usr_off_on_out : 1;
456 uint8_t ois_on_en : 1;
457 uint8_t not_used_01 : 1;
458 uint8_t hpm_g : 2;
459 uint8_t hp_en_g : 1;
460 uint8_t g_hm_mode : 1;
461#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
462 uint8_t g_hm_mode : 1;
463 uint8_t hp_en_g : 1;
464 uint8_t hpm_g : 2;
465 uint8_t not_used_01 : 1;
466 uint8_t ois_on_en : 1;
467 uint8_t usr_off_on_out : 1;
468 uint8_t ois_on : 1;
469#endif /* DRV_BYTE_ORDER */
470} ism330dhcx_ctrl7_g_t;
471
472#define ISM330DHCX_CTRL8_XL 0x17U
473typedef struct
474{
475#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
476 uint8_t low_pass_on_6d : 1;
477 uint8_t not_used_01 : 1;
478 uint8_t hp_slope_xl_en : 1;
479 uint8_t fastsettl_mode_xl : 1;
480 uint8_t hp_ref_mode_xl : 1;
481 uint8_t hpcf_xl : 3;
482#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
483 uint8_t hpcf_xl : 3;
484 uint8_t hp_ref_mode_xl : 1;
485 uint8_t fastsettl_mode_xl : 1;
486 uint8_t hp_slope_xl_en : 1;
487 uint8_t not_used_01 : 1;
488 uint8_t low_pass_on_6d : 1;
489#endif /* DRV_BYTE_ORDER */
490} ism330dhcx_ctrl8_xl_t;
491
492#define ISM330DHCX_CTRL9_XL 0x18U
493typedef struct
494{
495#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
496 uint8_t not_used_01 : 1;
497 uint8_t device_conf : 1;
498 uint8_t den_lh : 1;
499 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
500 uint8_t den_z : 1;
501 uint8_t den_y : 1;
502 uint8_t den_x : 1;
503#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
504 uint8_t den_x : 1;
505 uint8_t den_y : 1;
506 uint8_t den_z : 1;
507 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
508 uint8_t den_lh : 1;
509 uint8_t device_conf : 1;
510 uint8_t not_used_01 : 1;
511#endif /* DRV_BYTE_ORDER */
512} ism330dhcx_ctrl9_xl_t;
513
514#define ISM330DHCX_CTRL10_C 0x19U
515typedef struct
516{
517#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
518 uint8_t not_used_01 : 5;
519 uint8_t timestamp_en : 1;
520 uint8_t not_used_02 : 2;
521#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
522 uint8_t not_used_02 : 2;
523 uint8_t timestamp_en : 1;
524 uint8_t not_used_01 : 5;
525#endif /* DRV_BYTE_ORDER */
526} ism330dhcx_ctrl10_c_t;
527
528#define ISM330DHCX_ALL_INT_SRC 0x1AU
529typedef struct
530{
531#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
532 uint8_t ff_ia : 1;
533 uint8_t wu_ia : 1;
534 uint8_t single_tap : 1;
535 uint8_t double_tap : 1;
536 uint8_t d6d_ia : 1;
537 uint8_t sleep_change_ia : 1;
538 uint8_t not_used_01 : 1;
539 uint8_t timestamp_endcount : 1;
540#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
541 uint8_t timestamp_endcount : 1;
542 uint8_t not_used_01 : 1;
543 uint8_t sleep_change_ia : 1;
544 uint8_t d6d_ia : 1;
545 uint8_t double_tap : 1;
546 uint8_t single_tap : 1;
547 uint8_t wu_ia : 1;
548 uint8_t ff_ia : 1;
549#endif /* DRV_BYTE_ORDER */
550} ism330dhcx_all_int_src_t;
551
552#define ISM330DHCX_WAKE_UP_SRC 0x1BU
553typedef struct
554{
555#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
556 uint8_t z_wu : 1;
557 uint8_t y_wu : 1;
558 uint8_t x_wu : 1;
559 uint8_t wu_ia : 1;
560 uint8_t sleep_state : 1;
561 uint8_t ff_ia : 1;
562 uint8_t sleep_change_ia : 1;
563 uint8_t not_used_01 : 1;
564#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
565 uint8_t not_used_01 : 1;
566 uint8_t sleep_change_ia : 1;
567 uint8_t ff_ia : 1;
568 uint8_t sleep_state : 1;
569 uint8_t wu_ia : 1;
570 uint8_t x_wu : 1;
571 uint8_t y_wu : 1;
572 uint8_t z_wu : 1;
573#endif /* DRV_BYTE_ORDER */
574} ism330dhcx_wake_up_src_t;
575
576#define ISM330DHCX_TAP_SRC 0x1CU
577typedef struct
578{
579#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
580 uint8_t z_tap : 1;
581 uint8_t y_tap : 1;
582 uint8_t x_tap : 1;
583 uint8_t tap_sign : 1;
584 uint8_t double_tap : 1;
585 uint8_t single_tap : 1;
586 uint8_t tap_ia : 1;
587 uint8_t not_used_01 : 1;
588#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
589 uint8_t not_used_01 : 1;
590 uint8_t tap_ia : 1;
591 uint8_t single_tap : 1;
592 uint8_t double_tap : 1;
593 uint8_t tap_sign : 1;
594 uint8_t x_tap : 1;
595 uint8_t y_tap : 1;
596 uint8_t z_tap : 1;
597#endif /* DRV_BYTE_ORDER */
598} ism330dhcx_tap_src_t;
599
600#define ISM330DHCX_D6D_SRC 0x1DU
601typedef struct
602{
603#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
604 uint8_t xl : 1;
605 uint8_t xh : 1;
606 uint8_t yl : 1;
607 uint8_t yh : 1;
608 uint8_t zl : 1;
609 uint8_t zh : 1;
610 uint8_t d6d_ia : 1;
611 uint8_t den_drdy : 1;
612#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
613 uint8_t den_drdy : 1;
614 uint8_t d6d_ia : 1;
615 uint8_t zh : 1;
616 uint8_t zl : 1;
617 uint8_t yh : 1;
618 uint8_t yl : 1;
619 uint8_t xh : 1;
620 uint8_t xl : 1;
621#endif /* DRV_BYTE_ORDER */
622} ism330dhcx_d6d_src_t;
623
624#define ISM330DHCX_STATUS_REG 0x1EU
625typedef struct
626{
627#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
628 uint8_t xlda : 1;
629 uint8_t gda : 1;
630 uint8_t tda : 1;
631 uint8_t not_used_01 : 5;
632#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
633 uint8_t not_used_01 : 5;
634 uint8_t tda : 1;
635 uint8_t gda : 1;
636 uint8_t xlda : 1;
637#endif /* DRV_BYTE_ORDER */
638} ism330dhcx_status_reg_t;
639
640#define ISM330DHCX_STATUS_SPIAUX 0x1EU
641typedef struct
642{
643#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
644 uint8_t xlda : 1;
645 uint8_t gda : 1;
646 uint8_t gyro_settling : 1;
647 uint8_t not_used_01 : 5;
648#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
649 uint8_t not_used_01 : 5;
650 uint8_t gyro_settling : 1;
651 uint8_t gda : 1;
652 uint8_t xlda : 1;
653#endif /* DRV_BYTE_ORDER */
654} ism330dhcx_status_spiaux_t;
655
656#define ISM330DHCX_OUT_TEMP_L 0x20U
657#define ISM330DHCX_OUT_TEMP_H 0x21U
658#define ISM330DHCX_OUTX_L_G 0x22U
659#define ISM330DHCX_OUTX_H_G 0x23U
660#define ISM330DHCX_OUTY_L_G 0x24U
661#define ISM330DHCX_OUTY_H_G 0x25U
662#define ISM330DHCX_OUTZ_L_G 0x26U
663#define ISM330DHCX_OUTZ_H_G 0x27U
664#define ISM330DHCX_OUTX_L_A 0x28U
665#define ISM330DHCX_OUTX_H_A 0x29U
666#define ISM330DHCX_OUTY_L_A 0x2AU
667#define ISM330DHCX_OUTY_H_A 0x2BU
668#define ISM330DHCX_OUTZ_L_A 0x2CU
669#define ISM330DHCX_OUTZ_H_A 0x2DU
670#define ISM330DHCX_EMB_FUNC_STATUS_MAINPAGE 0x35U
671typedef struct
672{
673#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
674 uint8_t not_used_01 : 3;
675 uint8_t is_step_det : 1;
676 uint8_t is_tilt : 1;
677 uint8_t is_sigmot : 1;
678 uint8_t not_used_02 : 1;
679 uint8_t is_fsm_lc : 1;
680#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
681 uint8_t is_fsm_lc : 1;
682 uint8_t not_used_02 : 1;
683 uint8_t is_sigmot : 1;
684 uint8_t is_tilt : 1;
685 uint8_t is_step_det : 1;
686 uint8_t not_used_01 : 3;
687#endif /* DRV_BYTE_ORDER */
688} ism330dhcx_emb_func_status_mainpage_t;
689
690#define ISM330DHCX_FSM_STATUS_A_MAINPAGE 0x36U
691typedef struct
692{
693#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
694 uint8_t is_fsm1 : 1;
695 uint8_t is_fsm2 : 1;
696 uint8_t is_fsm3 : 1;
697 uint8_t is_fsm4 : 1;
698 uint8_t is_fsm5 : 1;
699 uint8_t is_fsm6 : 1;
700 uint8_t is_fsm7 : 1;
701 uint8_t is_fsm8 : 1;
702#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
703 uint8_t is_fsm8 : 1;
704 uint8_t is_fsm7 : 1;
705 uint8_t is_fsm6 : 1;
706 uint8_t is_fsm5 : 1;
707 uint8_t is_fsm4 : 1;
708 uint8_t is_fsm3 : 1;
709 uint8_t is_fsm2 : 1;
710 uint8_t is_fsm1 : 1;
711#endif /* DRV_BYTE_ORDER */
712} ism330dhcx_fsm_status_a_mainpage_t;
713
714#define ISM330DHCX_FSM_STATUS_B_MAINPAGE 0x37U
715typedef struct
716{
717#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
718 uint8_t is_fsm9 : 1;
719 uint8_t is_fsm10 : 1;
720 uint8_t is_fsm11 : 1;
721 uint8_t is_fsm12 : 1;
722 uint8_t is_fsm13 : 1;
723 uint8_t is_fsm14 : 1;
724 uint8_t is_fsm15 : 1;
725 uint8_t is_fsm16 : 1;
726#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
727 uint8_t is_fsm16 : 1;
728 uint8_t is_fsm15 : 1;
729 uint8_t is_fsm14 : 1;
730 uint8_t is_fsm13 : 1;
731 uint8_t is_fsm12 : 1;
732 uint8_t is_fsm11 : 1;
733 uint8_t is_fsm10 : 1;
734 uint8_t is_fsm9 : 1;
735#endif /* DRV_BYTE_ORDER */
736} ism330dhcx_fsm_status_b_mainpage_t;
737
738#define ISM330DHCX_MLC_STATUS_MAINPAGE 0x38U
739typedef struct
740{
741#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
742 uint8_t is_mlc1 : 1;
743 uint8_t is_mlc2 : 1;
744 uint8_t is_mlc3 : 1;
745 uint8_t is_mlc4 : 1;
746 uint8_t is_mlc5 : 1;
747 uint8_t is_mlc6 : 1;
748 uint8_t is_mlc7 : 1;
749 uint8_t is_mlc8 : 1;
750#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
751 uint8_t is_mlc8 : 1;
752 uint8_t is_mlc7 : 1;
753 uint8_t is_mlc6 : 1;
754 uint8_t is_mlc5 : 1;
755 uint8_t is_mlc4 : 1;
756 uint8_t is_mlc3 : 1;
757 uint8_t is_mlc2 : 1;
758 uint8_t is_mlc1 : 1;
759#endif /* DRV_BYTE_ORDER */
760} ism330dhcx_mlc_status_mainpage_t;
761
762#define ISM330DHCX_STATUS_MASTER_MAINPAGE 0x39U
763typedef struct
764{
765#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
766 uint8_t sens_hub_endop : 1;
767 uint8_t not_used_01 : 2;
768 uint8_t slave0_nack : 1;
769 uint8_t slave1_nack : 1;
770 uint8_t slave2_nack : 1;
771 uint8_t slave3_nack : 1;
772 uint8_t wr_once_done : 1;
773#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
774 uint8_t wr_once_done : 1;
775 uint8_t slave3_nack : 1;
776 uint8_t slave2_nack : 1;
777 uint8_t slave1_nack : 1;
778 uint8_t slave0_nack : 1;
779 uint8_t not_used_01 : 2;
780 uint8_t sens_hub_endop : 1;
781#endif /* DRV_BYTE_ORDER */
782} ism330dhcx_status_master_mainpage_t;
783
784#define ISM330DHCX_FIFO_STATUS1 0x3AU
785typedef struct
786{
787 uint8_t diff_fifo : 8;
788} ism330dhcx_fifo_status1_t;
789
790#define ISM330DHCX_FIFO_STATUS2 0x3BU
791typedef struct
792{
793#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
794 uint8_t diff_fifo : 2;
795 uint8_t not_used_01 : 1;
796 uint8_t over_run_latched : 1;
797 uint8_t counter_bdr_ia : 1;
798 uint8_t fifo_full_ia : 1;
799 uint8_t fifo_ovr_ia : 1;
800 uint8_t fifo_wtm_ia : 1;
801#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
802 uint8_t fifo_wtm_ia : 1;
803 uint8_t fifo_ovr_ia : 1;
804 uint8_t fifo_full_ia : 1;
805 uint8_t counter_bdr_ia : 1;
806 uint8_t over_run_latched : 1;
807 uint8_t not_used_01 : 1;
808 uint8_t diff_fifo : 2;
809#endif /* DRV_BYTE_ORDER */
810} ism330dhcx_fifo_status2_t;
811
812#define ISM330DHCX_TIMESTAMP0 0x40U
813#define ISM330DHCX_TIMESTAMP1 0x41U
814#define ISM330DHCX_TIMESTAMP2 0x42U
815#define ISM330DHCX_TIMESTAMP3 0x43U
816#define ISM330DHCX_TAP_CFG0 0x56U
817typedef struct
818{
819#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
820 uint8_t lir : 1;
821 uint8_t tap_z_en : 1;
822 uint8_t tap_y_en : 1;
823 uint8_t tap_x_en : 1;
824 uint8_t slope_fds : 1;
825 uint8_t sleep_status_on_int : 1;
826 uint8_t int_clr_on_read : 1;
827 uint8_t not_used_01 : 1;
828#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
829 uint8_t not_used_01 : 1;
830 uint8_t int_clr_on_read : 1;
831 uint8_t sleep_status_on_int : 1;
832 uint8_t slope_fds : 1;
833 uint8_t tap_x_en : 1;
834 uint8_t tap_y_en : 1;
835 uint8_t tap_z_en : 1;
836 uint8_t lir : 1;
837#endif /* DRV_BYTE_ORDER */
838} ism330dhcx_tap_cfg0_t;
839
840#define ISM330DHCX_TAP_CFG1 0x57U
841typedef struct
842{
843#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
844 uint8_t tap_ths_x : 5;
845 uint8_t tap_priority : 3;
846#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
847 uint8_t tap_priority : 3;
848 uint8_t tap_ths_x : 5;
849#endif /* DRV_BYTE_ORDER */
850} ism330dhcx_tap_cfg1_t;
851
852#define ISM330DHCX_TAP_CFG2 0x58U
853typedef struct
854{
855#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
856 uint8_t tap_ths_y : 5;
857 uint8_t inact_en : 2;
858 uint8_t interrupts_enable : 1;
859#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
860 uint8_t interrupts_enable : 1;
861 uint8_t inact_en : 2;
862 uint8_t tap_ths_y : 5;
863#endif /* DRV_BYTE_ORDER */
864} ism330dhcx_tap_cfg2_t;
865
866#define ISM330DHCX_TAP_THS_6D 0x59U
867typedef struct
868{
869#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
870 uint8_t tap_ths_z : 5;
871 uint8_t sixd_ths : 2;
872 uint8_t d4d_en : 1;
873#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
874 uint8_t d4d_en : 1;
875 uint8_t sixd_ths : 2;
876 uint8_t tap_ths_z : 5;
877#endif /* DRV_BYTE_ORDER */
878} ism330dhcx_tap_ths_6d_t;
879
880#define ISM330DHCX_INT_DUR2 0x5AU
881typedef struct
882{
883#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
884 uint8_t shock : 2;
885 uint8_t quiet : 2;
886 uint8_t dur : 4;
887#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
888 uint8_t dur : 4;
889 uint8_t quiet : 2;
890 uint8_t shock : 2;
891#endif /* DRV_BYTE_ORDER */
892} ism330dhcx_int_dur2_t;
893
894#define ISM330DHCX_WAKE_UP_THS 0x5BU
895typedef struct
896{
897#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
898 uint8_t wk_ths : 6;
899 uint8_t usr_off_on_wu : 1;
900 uint8_t single_double_tap : 1;
901#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
902 uint8_t single_double_tap : 1;
903 uint8_t usr_off_on_wu : 1;
904 uint8_t wk_ths : 6;
905#endif /* DRV_BYTE_ORDER */
906} ism330dhcx_wake_up_ths_t;
907
908#define ISM330DHCX_WAKE_UP_DUR 0x5CU
909typedef struct
910{
911#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
912 uint8_t sleep_dur : 4;
913 uint8_t wake_ths_w : 1;
914 uint8_t wake_dur : 2;
915 uint8_t ff_dur : 1;
916#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
917 uint8_t ff_dur : 1;
918 uint8_t wake_dur : 2;
919 uint8_t wake_ths_w : 1;
920 uint8_t sleep_dur : 4;
921#endif /* DRV_BYTE_ORDER */
922} ism330dhcx_wake_up_dur_t;
923
924#define ISM330DHCX_FREE_FALL 0x5DU
925typedef struct
926{
927#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
928 uint8_t ff_ths : 3;
929 uint8_t ff_dur : 5;
930#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
931 uint8_t ff_dur : 5;
932 uint8_t ff_ths : 3;
933#endif /* DRV_BYTE_ORDER */
934} ism330dhcx_free_fall_t;
935
936#define ISM330DHCX_MD1_CFG 0x5EU
937typedef struct
938{
939#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
940 uint8_t int1_shub : 1;
941 uint8_t int1_emb_func : 1;
942 uint8_t int1_6d : 1;
943 uint8_t int1_double_tap : 1;
944 uint8_t int1_ff : 1;
945 uint8_t int1_wu : 1;
946 uint8_t int1_single_tap : 1;
947 uint8_t int1_sleep_change : 1;
948#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
949 uint8_t int1_sleep_change : 1;
950 uint8_t int1_single_tap : 1;
951 uint8_t int1_wu : 1;
952 uint8_t int1_ff : 1;
953 uint8_t int1_double_tap : 1;
954 uint8_t int1_6d : 1;
955 uint8_t int1_emb_func : 1;
956 uint8_t int1_shub : 1;
957#endif /* DRV_BYTE_ORDER */
958} ism330dhcx_md1_cfg_t;
959
960#define ISM330DHCX_MD2_CFG 0x5FU
961typedef struct
962{
963#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
964 uint8_t int2_timestamp : 1;
965 uint8_t int2_emb_func : 1;
966 uint8_t int2_6d : 1;
967 uint8_t int2_double_tap : 1;
968 uint8_t int2_ff : 1;
969 uint8_t int2_wu : 1;
970 uint8_t int2_single_tap : 1;
971 uint8_t int2_sleep_change : 1;
972#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
973 uint8_t int2_sleep_change : 1;
974 uint8_t int2_single_tap : 1;
975 uint8_t int2_wu : 1;
976 uint8_t int2_ff : 1;
977 uint8_t int2_double_tap : 1;
978 uint8_t int2_6d : 1;
979 uint8_t int2_emb_func : 1;
980 uint8_t int2_timestamp : 1;
981#endif /* DRV_BYTE_ORDER */
982} ism330dhcx_md2_cfg_t;
983
984#define ISM330DHCX_INTERNAL_FREQ_FINE 0x63U
985typedef struct
986{
987 uint8_t freq_fine : 8;
988} ism330dhcx_internal_freq_fine_t;
989
990#define ISM330DHCX_INT_OIS 0x6FU
991typedef struct
992{
993#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
994 uint8_t st_xl_ois : 2;
995 uint8_t not_used_01 : 3;
996 uint8_t den_lh_ois : 1;
997 uint8_t lvl2_ois : 1;
998 uint8_t int2_drdy_ois : 1;
999#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1000 uint8_t int2_drdy_ois : 1;
1001 uint8_t lvl2_ois : 1;
1002 uint8_t den_lh_ois : 1;
1003 uint8_t not_used_01 : 3;
1004 uint8_t st_xl_ois : 2;
1005#endif /* DRV_BYTE_ORDER */
1006} ism330dhcx_int_ois_t;
1007
1008#define ISM330DHCX_CTRL1_OIS 0x70U
1009typedef struct
1010{
1011#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1012 uint8_t ois_en_spi2 : 1;
1013 uint8_t fs_125_ois : 1;
1014 uint8_t fs_g_ois : 2;
1015 uint8_t mode4_en : 1;
1016 uint8_t sim_ois : 1;
1017 uint8_t lvl1_ois : 1;
1018 uint8_t not_used_01 : 1;
1019#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1020 uint8_t not_used_01 : 1;
1021 uint8_t lvl1_ois : 1;
1022 uint8_t sim_ois : 1;
1023 uint8_t mode4_en : 1;
1024 uint8_t fs_g_ois : 2;
1025 uint8_t fs_125_ois : 1;
1026 uint8_t ois_en_spi2 : 1;
1027#endif /* DRV_BYTE_ORDER */
1028} ism330dhcx_ctrl1_ois_t;
1029
1030#define ISM330DHCX_CTRL2_OIS 0x71U
1031typedef struct
1032{
1033#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1034 uint8_t hp_en_ois : 1;
1035 uint8_t ftype_ois : 2;
1036 uint8_t not_used_01 : 1;
1037 uint8_t hpm_ois : 2;
1038 uint8_t not_used_02 : 2;
1039#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1040 uint8_t not_used_02 : 2;
1041 uint8_t hpm_ois : 2;
1042 uint8_t not_used_01 : 1;
1043 uint8_t ftype_ois : 2;
1044 uint8_t hp_en_ois : 1;
1045#endif /* DRV_BYTE_ORDER */
1046} ism330dhcx_ctrl2_ois_t;
1047
1048#define ISM330DHCX_CTRL3_OIS 0x72U
1049typedef struct
1050{
1051#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1052 uint8_t st_ois_clampdis : 1;
1053 uint8_t st_ois : 2;
1054 uint8_t filter_xl_conf_ois : 3;
1055 uint8_t fs_xl_ois : 2;
1056#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1057 uint8_t fs_xl_ois : 2;
1058 uint8_t filter_xl_conf_ois : 3;
1059 uint8_t st_ois : 2;
1060 uint8_t st_ois_clampdis : 1;
1061#endif /* DRV_BYTE_ORDER */
1062} ism330dhcx_ctrl3_ois_t;
1063
1064#define ISM330DHCX_X_OFS_USR 0x73U
1065#define ISM330DHCX_Y_OFS_USR 0x74U
1066#define ISM330DHCX_Z_OFS_USR 0x75U
1067#define ISM330DHCX_FIFO_DATA_OUT_TAG 0x78U
1068typedef struct
1069{
1070#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1071 uint8_t tag_parity : 1;
1072 uint8_t tag_cnt : 2;
1073 uint8_t tag_sensor : 5;
1074#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1075 uint8_t tag_sensor : 5;
1076 uint8_t tag_cnt : 2;
1077 uint8_t tag_parity : 1;
1078#endif /* DRV_BYTE_ORDER */
1079} ism330dhcx_fifo_data_out_tag_t;
1080
1081#define ISM330DHCX_FIFO_DATA_OUT_X_L 0x79U
1082#define ISM330DHCX_FIFO_DATA_OUT_X_H 0x7AU
1083#define ISM330DHCX_FIFO_DATA_OUT_Y_L 0x7BU
1084#define ISM330DHCX_FIFO_DATA_OUT_Y_H 0x7CU
1085#define ISM330DHCX_FIFO_DATA_OUT_Z_L 0x7DU
1086#define ISM330DHCX_FIFO_DATA_OUT_Z_H 0x7EU
1087#define ISM330DHCX_PAGE_SEL 0x02U
1088typedef struct
1089{
1090#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1091 uint8_t not_used_01 : 4;
1092 uint8_t page_sel : 4;
1093#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1094 uint8_t page_sel : 4;
1095 uint8_t not_used_01 : 4;
1096#endif /* DRV_BYTE_ORDER */
1097} ism330dhcx_page_sel_t;
1098
1099#define ISM330DHCX_EMB_FUNC_EN_A 0x04U
1100typedef struct
1101{
1102#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1103 uint8_t not_used_01 : 3;
1104 uint8_t pedo_en : 1;
1105 uint8_t tilt_en : 1;
1106 uint8_t sign_motion_en : 1;
1107 uint8_t not_used_02 : 2;
1108#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1109 uint8_t not_used_02 : 2;
1110 uint8_t sign_motion_en : 1;
1111 uint8_t tilt_en : 1;
1112 uint8_t pedo_en : 1;
1113 uint8_t not_used_01 : 3;
1114#endif /* DRV_BYTE_ORDER */
1115} ism330dhcx_emb_func_en_a_t;
1116
1117#define ISM330DHCX_EMB_FUNC_EN_B 0x05U
1118typedef struct
1119{
1120#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1121 uint8_t fsm_en : 1;
1122 uint8_t not_used_01 : 2;
1123 uint8_t fifo_compr_en : 1;
1124 uint8_t mlc_en : 1;
1125 uint8_t not_used_02 : 3;
1126#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1127 uint8_t not_used_02 : 3;
1128 uint8_t mlc_en : 1;
1129 uint8_t fifo_compr_en : 1;
1130 uint8_t not_used_01 : 2;
1131 uint8_t fsm_en : 1;
1132#endif /* DRV_BYTE_ORDER */
1133} ism330dhcx_emb_func_en_b_t;
1134
1135#define ISM330DHCX_PAGE_ADDRESS 0x08U
1136typedef struct
1137{
1138 uint8_t page_addr : 8;
1139} ism330dhcx_page_address_t;
1140
1141#define ISM330DHCX_PAGE_VALUE 0x09U
1142typedef struct
1143{
1144 uint8_t page_value : 8;
1145} ism330dhcx_page_value_t;
1146
1147#define ISM330DHCX_EMB_FUNC_INT1 0x0AU
1148typedef struct
1149{
1150#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1151 uint8_t not_used_01 : 3;
1152 uint8_t int1_step_detector : 1;
1153 uint8_t int1_tilt : 1;
1154 uint8_t int1_sig_mot : 1;
1155 uint8_t not_used_02 : 1;
1156 uint8_t int1_fsm_lc : 1;
1157#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1158 uint8_t int1_fsm_lc : 1;
1159 uint8_t not_used_02 : 1;
1160 uint8_t int1_sig_mot : 1;
1161 uint8_t int1_tilt : 1;
1162 uint8_t int1_step_detector : 1;
1163 uint8_t not_used_01 : 3;
1164#endif /* DRV_BYTE_ORDER */
1165} ism330dhcx_emb_func_int1_t;
1166
1167#define ISM330DHCX_FSM_INT1_A 0x0BU
1168typedef struct
1169{
1170#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1171 uint8_t int1_fsm1 : 1;
1172 uint8_t int1_fsm2 : 1;
1173 uint8_t int1_fsm3 : 1;
1174 uint8_t int1_fsm4 : 1;
1175 uint8_t int1_fsm5 : 1;
1176 uint8_t int1_fsm6 : 1;
1177 uint8_t int1_fsm7 : 1;
1178 uint8_t int1_fsm8 : 1;
1179#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1180 uint8_t int1_fsm8 : 1;
1181 uint8_t int1_fsm7 : 1;
1182 uint8_t int1_fsm6 : 1;
1183 uint8_t int1_fsm5 : 1;
1184 uint8_t int1_fsm4 : 1;
1185 uint8_t int1_fsm3 : 1;
1186 uint8_t int1_fsm2 : 1;
1187 uint8_t int1_fsm1 : 1;
1188#endif /* DRV_BYTE_ORDER */
1189} ism330dhcx_fsm_int1_a_t;
1190
1191#define ISM330DHCX_FSM_INT1_B 0x0CU
1192typedef struct
1193{
1194#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1195 uint8_t int1_fsm9 : 1;
1196 uint8_t int1_fsm10 : 1;
1197 uint8_t int1_fsm11 : 1;
1198 uint8_t int1_fsm12 : 1;
1199 uint8_t int1_fsm13 : 1;
1200 uint8_t int1_fsm14 : 1;
1201 uint8_t int1_fsm15 : 1;
1202 uint8_t int1_fsm16 : 1;
1203#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1204 uint8_t int1_fsm16 : 1;
1205 uint8_t int1_fsm15 : 1;
1206 uint8_t int1_fsm14 : 1;
1207 uint8_t int1_fsm13 : 1;
1208 uint8_t int1_fsm12 : 1;
1209 uint8_t int1_fsm11 : 1;
1210 uint8_t int1_fsm10 : 1;
1211 uint8_t int1_fsm9 : 1;
1212#endif /* DRV_BYTE_ORDER */
1213} ism330dhcx_fsm_int1_b_t;
1214
1215#define ISM330DHCX_MLC_INT1 0x0DU
1216typedef struct
1217{
1218#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1219 uint8_t int1_mlc1 : 1;
1220 uint8_t int1_mlc2 : 1;
1221 uint8_t int1_mlc3 : 1;
1222 uint8_t int1_mlc4 : 1;
1223 uint8_t int1_mlc5 : 1;
1224 uint8_t int1_mlc6 : 1;
1225 uint8_t int1_mlc7 : 1;
1226 uint8_t int1_mlc8 : 1;
1227#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1228 uint8_t int1_mlc8 : 1;
1229 uint8_t int1_mlc7 : 1;
1230 uint8_t int1_mlc6 : 1;
1231 uint8_t int1_mlc5 : 1;
1232 uint8_t int1_mlc4 : 1;
1233 uint8_t int1_mlc3 : 1;
1234 uint8_t int1_mlc2 : 1;
1235 uint8_t int1_mlc1 : 1;
1236#endif /* DRV_BYTE_ORDER */
1237} ism330dhcx_mlc_int1_t;
1238
1239#define ISM330DHCX_EMB_FUNC_INT2 0x0EU
1240typedef struct
1241{
1242#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1243 uint8_t not_used_01 : 3;
1244 uint8_t int2_step_detector : 1;
1245 uint8_t int2_tilt : 1;
1246 uint8_t int2_sig_mot : 1;
1247 uint8_t not_used_02 : 1;
1248 uint8_t int2_fsm_lc : 1;
1249#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1250 uint8_t int2_fsm_lc : 1;
1251 uint8_t not_used_02 : 1;
1252 uint8_t int2_sig_mot : 1;
1253 uint8_t int2_tilt : 1;
1254 uint8_t int2_step_detector : 1;
1255 uint8_t not_used_01 : 3;
1256#endif /* DRV_BYTE_ORDER */
1257} ism330dhcx_emb_func_int2_t;
1258
1259#define ISM330DHCX_FSM_INT2_A 0x0FU
1260typedef struct
1261{
1262#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1263 uint8_t int2_fsm1 : 1;
1264 uint8_t int2_fsm2 : 1;
1265 uint8_t int2_fsm3 : 1;
1266 uint8_t int2_fsm4 : 1;
1267 uint8_t int2_fsm5 : 1;
1268 uint8_t int2_fsm6 : 1;
1269 uint8_t int2_fsm7 : 1;
1270 uint8_t int2_fsm8 : 1;
1271#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1272 uint8_t int2_fsm8 : 1;
1273 uint8_t int2_fsm7 : 1;
1274 uint8_t int2_fsm6 : 1;
1275 uint8_t int2_fsm5 : 1;
1276 uint8_t int2_fsm4 : 1;
1277 uint8_t int2_fsm3 : 1;
1278 uint8_t int2_fsm2 : 1;
1279 uint8_t int2_fsm1 : 1;
1280#endif /* DRV_BYTE_ORDER */
1281} ism330dhcx_fsm_int2_a_t;
1282
1283#define ISM330DHCX_FSM_INT2_B 0x10U
1284typedef struct
1285{
1286#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1287 uint8_t int2_fsm9 : 1;
1288 uint8_t int2_fsm10 : 1;
1289 uint8_t int2_fsm11 : 1;
1290 uint8_t int2_fsm12 : 1;
1291 uint8_t int2_fsm13 : 1;
1292 uint8_t int2_fsm14 : 1;
1293 uint8_t int2_fsm15 : 1;
1294 uint8_t int2_fsm16 : 1;
1295#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1296 uint8_t int2_fsm16 : 1;
1297 uint8_t int2_fsm15 : 1;
1298 uint8_t int2_fsm14 : 1;
1299 uint8_t int2_fsm13 : 1;
1300 uint8_t int2_fsm12 : 1;
1301 uint8_t int2_fsm11 : 1;
1302 uint8_t int2_fsm10 : 1;
1303 uint8_t int2_fsm9 : 1;
1304#endif /* DRV_BYTE_ORDER */
1305} ism330dhcx_fsm_int2_b_t;
1306
1307#define ISM330DHCX_MLC_INT2 0x11U
1308typedef struct
1309{
1310#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1311 uint8_t int2_mlc1 : 1;
1312 uint8_t int2_mlc2 : 1;
1313 uint8_t int2_mlc3 : 1;
1314 uint8_t int2_mlc4 : 1;
1315 uint8_t int2_mlc5 : 1;
1316 uint8_t int2_mlc6 : 1;
1317 uint8_t int2_mlc7 : 1;
1318 uint8_t int2_mlc8 : 1;
1319#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1320 uint8_t int2_mlc8 : 1;
1321 uint8_t int2_mlc7 : 1;
1322 uint8_t int2_mlc6 : 1;
1323 uint8_t int2_mlc5 : 1;
1324 uint8_t int2_mlc4 : 1;
1325 uint8_t int2_mlc3 : 1;
1326 uint8_t int2_mlc2 : 1;
1327 uint8_t int2_mlc1 : 1;
1328#endif /* DRV_BYTE_ORDER */
1329} ism330dhcx_mlc_int2_t;
1330
1331#define ISM330DHCX_EMB_FUNC_STATUS 0x12U
1332typedef struct
1333{
1334#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1335 uint8_t not_used_01 : 3;
1336 uint8_t is_step_det : 1;
1337 uint8_t is_tilt : 1;
1338 uint8_t is_sigmot : 1;
1339 uint8_t not_used_02 : 1;
1340 uint8_t is_fsm_lc : 1;
1341#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1342 uint8_t is_fsm_lc : 1;
1343 uint8_t not_used_02 : 1;
1344 uint8_t is_sigmot : 1;
1345 uint8_t is_tilt : 1;
1346 uint8_t is_step_det : 1;
1347 uint8_t not_used_01 : 3;
1348#endif /* DRV_BYTE_ORDER */
1349} ism330dhcx_emb_func_status_t;
1350
1351#define ISM330DHCX_FSM_STATUS_A 0x13U
1352typedef struct
1353{
1354#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1355 uint8_t is_fsm1 : 1;
1356 uint8_t is_fsm2 : 1;
1357 uint8_t is_fsm3 : 1;
1358 uint8_t is_fsm4 : 1;
1359 uint8_t is_fsm5 : 1;
1360 uint8_t is_fsm6 : 1;
1361 uint8_t is_fsm7 : 1;
1362 uint8_t is_fsm8 : 1;
1363#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1364 uint8_t is_fsm8 : 1;
1365 uint8_t is_fsm7 : 1;
1366 uint8_t is_fsm6 : 1;
1367 uint8_t is_fsm5 : 1;
1368 uint8_t is_fsm4 : 1;
1369 uint8_t is_fsm3 : 1;
1370 uint8_t is_fsm2 : 1;
1371 uint8_t is_fsm1 : 1;
1372#endif /* DRV_BYTE_ORDER */
1373} ism330dhcx_fsm_status_a_t;
1374
1375#define ISM330DHCX_FSM_STATUS_B 0x14U
1376typedef struct
1377{
1378#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1379 uint8_t is_fsm9 : 1;
1380 uint8_t is_fsm10 : 1;
1381 uint8_t is_fsm11 : 1;
1382 uint8_t is_fsm12 : 1;
1383 uint8_t is_fsm13 : 1;
1384 uint8_t is_fsm14 : 1;
1385 uint8_t is_fsm15 : 1;
1386 uint8_t is_fsm16 : 1;
1387#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1388 uint8_t is_fsm16 : 1;
1389 uint8_t is_fsm15 : 1;
1390 uint8_t is_fsm14 : 1;
1391 uint8_t is_fsm13 : 1;
1392 uint8_t is_fsm12 : 1;
1393 uint8_t is_fsm11 : 1;
1394 uint8_t is_fsm10 : 1;
1395 uint8_t is_fsm9 : 1;
1396#endif /* DRV_BYTE_ORDER */
1397} ism330dhcx_fsm_status_b_t;
1398
1399#define ISM330DHCX_MLC_STATUS 0x15U
1400typedef struct
1401{
1402#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1403 uint8_t is_mlc1 : 1;
1404 uint8_t is_mlc2 : 1;
1405 uint8_t is_mlc3 : 1;
1406 uint8_t is_mlc4 : 1;
1407 uint8_t is_mlc5 : 1;
1408 uint8_t is_mlc6 : 1;
1409 uint8_t is_mlc7 : 1;
1410 uint8_t is_mlc8 : 1;
1411#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1412 uint8_t is_mlc8 : 1;
1413 uint8_t is_mlc7 : 1;
1414 uint8_t is_mlc6 : 1;
1415 uint8_t is_mlc5 : 1;
1416 uint8_t is_mlc4 : 1;
1417 uint8_t is_mlc3 : 1;
1418 uint8_t is_mlc2 : 1;
1419 uint8_t is_mlc1 : 1;
1420#endif /* DRV_BYTE_ORDER */
1421} ism330dhcx_mlc_status_t;
1422
1423#define ISM330DHCX_PAGE_RW 0x17U
1424typedef struct
1425{
1426#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1427 uint8_t not_used_01 : 5;
1428 uint8_t page_rw : 2; /* page_write + page_read */
1429 uint8_t emb_func_lir : 1;
1430#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1431 uint8_t emb_func_lir : 1;
1432 uint8_t page_rw : 2; /* page_write + page_read */
1433 uint8_t not_used_01 : 5;
1434#endif /* DRV_BYTE_ORDER */
1435} ism330dhcx_page_rw_t;
1436
1437#define ISM330DHCX_EMB_FUNC_FIFO_CFG 0x44U
1438typedef struct
1439{
1440#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1441 uint8_t not_used_01 : 6;
1442 uint8_t pedo_fifo_en : 1;
1443 uint8_t not_used_02 : 1;
1444#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1445 uint8_t not_used_02 : 1;
1446 uint8_t pedo_fifo_en : 1;
1447 uint8_t not_used_01 : 6;
1448#endif /* DRV_BYTE_ORDER */
1449} ism330dhcx_emb_func_fifo_cfg_t;
1450
1451#define ISM330DHCX_FSM_ENABLE_A 0x46U
1452typedef struct
1453{
1454#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1455 uint8_t fsm1_en : 1;
1456 uint8_t fsm2_en : 1;
1457 uint8_t fsm3_en : 1;
1458 uint8_t fsm4_en : 1;
1459 uint8_t fsm5_en : 1;
1460 uint8_t fsm6_en : 1;
1461 uint8_t fsm7_en : 1;
1462 uint8_t fsm8_en : 1;
1463#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1464 uint8_t fsm8_en : 1;
1465 uint8_t fsm7_en : 1;
1466 uint8_t fsm6_en : 1;
1467 uint8_t fsm5_en : 1;
1468 uint8_t fsm4_en : 1;
1469 uint8_t fsm3_en : 1;
1470 uint8_t fsm2_en : 1;
1471 uint8_t fsm1_en : 1;
1472#endif /* DRV_BYTE_ORDER */
1473} ism330dhcx_fsm_enable_a_t;
1474
1475#define ISM330DHCX_FSM_ENABLE_B 0x47U
1476typedef struct
1477{
1478#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1479 uint8_t fsm9_en : 1;
1480 uint8_t fsm10_en : 1;
1481 uint8_t fsm11_en : 1;
1482 uint8_t fsm12_en : 1;
1483 uint8_t fsm13_en : 1;
1484 uint8_t fsm14_en : 1;
1485 uint8_t fsm15_en : 1;
1486 uint8_t fsm16_en : 1;
1487#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1488 uint8_t fsm16_en : 1;
1489 uint8_t fsm15_en : 1;
1490 uint8_t fsm14_en : 1;
1491 uint8_t fsm13_en : 1;
1492 uint8_t fsm12_en : 1;
1493 uint8_t fsm11_en : 1;
1494 uint8_t fsm10_en : 1;
1495 uint8_t fsm9_en : 1;
1496#endif /* DRV_BYTE_ORDER */
1497} ism330dhcx_fsm_enable_b_t;
1498
1499#define ISM330DHCX_FSM_LONG_COUNTER_L 0x48U
1500#define ISM330DHCX_FSM_LONG_COUNTER_H 0x49U
1501#define ISM330DHCX_FSM_LONG_COUNTER_CLEAR 0x4AU
1502typedef struct
1503{
1504#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1505uint8_t fsm_lc_clr :
1506 2; /* fsm_lc_cleared + fsm_lc_clear */
1507 uint8_t not_used_01 : 6;
1508#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1509 uint8_t not_used_01 : 6;
1510uint8_t fsm_lc_clr :
1511 2; /* fsm_lc_cleared + fsm_lc_clear */
1512#endif /* DRV_BYTE_ORDER */
1513} ism330dhcx_fsm_long_counter_clear_t;
1514
1515#define ISM330DHCX_FSM_OUTS1 0x4CU
1516typedef struct
1517{
1518#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1519 uint8_t n_v : 1;
1520 uint8_t p_v : 1;
1521 uint8_t n_z : 1;
1522 uint8_t p_z : 1;
1523 uint8_t n_y : 1;
1524 uint8_t p_y : 1;
1525 uint8_t n_x : 1;
1526 uint8_t p_x : 1;
1527#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1528 uint8_t p_x : 1;
1529 uint8_t n_x : 1;
1530 uint8_t p_y : 1;
1531 uint8_t n_y : 1;
1532 uint8_t p_z : 1;
1533 uint8_t n_z : 1;
1534 uint8_t p_v : 1;
1535 uint8_t n_v : 1;
1536#endif /* DRV_BYTE_ORDER */
1537} ism330dhcx_fsm_outs1_t;
1538
1539#define ISM330DHCX_FSM_OUTS2 0x4DU
1540typedef struct
1541{
1542#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1543 uint8_t n_v : 1;
1544 uint8_t p_v : 1;
1545 uint8_t n_z : 1;
1546 uint8_t p_z : 1;
1547 uint8_t n_y : 1;
1548 uint8_t p_y : 1;
1549 uint8_t n_x : 1;
1550 uint8_t p_x : 1;
1551#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1552 uint8_t p_x : 1;
1553 uint8_t n_x : 1;
1554 uint8_t p_y : 1;
1555 uint8_t n_y : 1;
1556 uint8_t p_z : 1;
1557 uint8_t n_z : 1;
1558 uint8_t p_v : 1;
1559 uint8_t n_v : 1;
1560#endif /* DRV_BYTE_ORDER */
1561} ism330dhcx_fsm_outs2_t;
1562
1563#define ISM330DHCX_FSM_OUTS3 0x4EU
1564typedef struct
1565{
1566#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1567 uint8_t n_v : 1;
1568 uint8_t p_v : 1;
1569 uint8_t n_z : 1;
1570 uint8_t p_z : 1;
1571 uint8_t n_y : 1;
1572 uint8_t p_y : 1;
1573 uint8_t n_x : 1;
1574 uint8_t p_x : 1;
1575#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1576 uint8_t p_x : 1;
1577 uint8_t n_x : 1;
1578 uint8_t p_y : 1;
1579 uint8_t n_y : 1;
1580 uint8_t p_z : 1;
1581 uint8_t n_z : 1;
1582 uint8_t p_v : 1;
1583 uint8_t n_v : 1;
1584#endif /* DRV_BYTE_ORDER */
1585} ism330dhcx_fsm_outs3_t;
1586
1587#define ISM330DHCX_FSM_OUTS4 0x4FU
1588typedef struct
1589{
1590#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1591 uint8_t n_v : 1;
1592 uint8_t p_v : 1;
1593 uint8_t n_z : 1;
1594 uint8_t p_z : 1;
1595 uint8_t n_y : 1;
1596 uint8_t p_y : 1;
1597 uint8_t n_x : 1;
1598 uint8_t p_x : 1;
1599#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1600 uint8_t p_x : 1;
1601 uint8_t n_x : 1;
1602 uint8_t p_y : 1;
1603 uint8_t n_y : 1;
1604 uint8_t p_z : 1;
1605 uint8_t n_z : 1;
1606 uint8_t p_v : 1;
1607 uint8_t n_v : 1;
1608#endif /* DRV_BYTE_ORDER */
1609} ism330dhcx_fsm_outs4_t;
1610
1611#define ISM330DHCX_FSM_OUTS5 0x50U
1612typedef struct
1613{
1614#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1615 uint8_t n_v : 1;
1616 uint8_t p_v : 1;
1617 uint8_t n_z : 1;
1618 uint8_t p_z : 1;
1619 uint8_t n_y : 1;
1620 uint8_t p_y : 1;
1621 uint8_t n_x : 1;
1622 uint8_t p_x : 1;
1623#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1624 uint8_t p_x : 1;
1625 uint8_t n_x : 1;
1626 uint8_t p_y : 1;
1627 uint8_t n_y : 1;
1628 uint8_t p_z : 1;
1629 uint8_t n_z : 1;
1630 uint8_t p_v : 1;
1631 uint8_t n_v : 1;
1632#endif /* DRV_BYTE_ORDER */
1633} ism330dhcx_fsm_outs5_t;
1634
1635#define ISM330DHCX_FSM_OUTS6 0x51U
1636typedef struct
1637{
1638#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1639 uint8_t n_v : 1;
1640 uint8_t p_v : 1;
1641 uint8_t n_z : 1;
1642 uint8_t p_z : 1;
1643 uint8_t n_y : 1;
1644 uint8_t p_y : 1;
1645 uint8_t n_x : 1;
1646 uint8_t p_x : 1;
1647#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1648 uint8_t p_x : 1;
1649 uint8_t n_x : 1;
1650 uint8_t p_y : 1;
1651 uint8_t n_y : 1;
1652 uint8_t p_z : 1;
1653 uint8_t n_z : 1;
1654 uint8_t p_v : 1;
1655 uint8_t n_v : 1;
1656#endif /* DRV_BYTE_ORDER */
1657} ism330dhcx_fsm_outs6_t;
1658
1659#define ISM330DHCX_FSM_OUTS7 0x52U
1660typedef struct
1661{
1662#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1663 uint8_t n_v : 1;
1664 uint8_t p_v : 1;
1665 uint8_t n_z : 1;
1666 uint8_t p_z : 1;
1667 uint8_t n_y : 1;
1668 uint8_t p_y : 1;
1669 uint8_t n_x : 1;
1670 uint8_t p_x : 1;
1671#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1672 uint8_t p_x : 1;
1673 uint8_t n_x : 1;
1674 uint8_t p_y : 1;
1675 uint8_t n_y : 1;
1676 uint8_t p_z : 1;
1677 uint8_t n_z : 1;
1678 uint8_t p_v : 1;
1679 uint8_t n_v : 1;
1680#endif /* DRV_BYTE_ORDER */
1681} ism330dhcx_fsm_outs7_t;
1682
1683#define ISM330DHCX_FSM_OUTS8 0x53U
1684typedef struct
1685{
1686#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1687 uint8_t n_v : 1;
1688 uint8_t p_v : 1;
1689 uint8_t n_z : 1;
1690 uint8_t p_z : 1;
1691 uint8_t n_y : 1;
1692 uint8_t p_y : 1;
1693 uint8_t n_x : 1;
1694 uint8_t p_x : 1;
1695#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1696 uint8_t p_x : 1;
1697 uint8_t n_x : 1;
1698 uint8_t p_y : 1;
1699 uint8_t n_y : 1;
1700 uint8_t p_z : 1;
1701 uint8_t n_z : 1;
1702 uint8_t p_v : 1;
1703 uint8_t n_v : 1;
1704#endif /* DRV_BYTE_ORDER */
1705} ism330dhcx_fsm_outs8_t;
1706
1707#define ISM330DHCX_FSM_OUTS9 0x54U
1708typedef struct
1709{
1710#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1711 uint8_t n_v : 1;
1712 uint8_t p_v : 1;
1713 uint8_t n_z : 1;
1714 uint8_t p_z : 1;
1715 uint8_t n_y : 1;
1716 uint8_t p_y : 1;
1717 uint8_t n_x : 1;
1718 uint8_t p_x : 1;
1719#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1720 uint8_t p_x : 1;
1721 uint8_t n_x : 1;
1722 uint8_t p_y : 1;
1723 uint8_t n_y : 1;
1724 uint8_t p_z : 1;
1725 uint8_t n_z : 1;
1726 uint8_t p_v : 1;
1727 uint8_t n_v : 1;
1728#endif /* DRV_BYTE_ORDER */
1729} ism330dhcx_fsm_outs9_t;
1730
1731#define ISM330DHCX_FSM_OUTS10 0x55U
1732typedef struct
1733{
1734#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1735 uint8_t n_v : 1;
1736 uint8_t p_v : 1;
1737 uint8_t n_z : 1;
1738 uint8_t p_z : 1;
1739 uint8_t n_y : 1;
1740 uint8_t p_y : 1;
1741 uint8_t n_x : 1;
1742 uint8_t p_x : 1;
1743#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1744 uint8_t p_x : 1;
1745 uint8_t n_x : 1;
1746 uint8_t p_y : 1;
1747 uint8_t n_y : 1;
1748 uint8_t p_z : 1;
1749 uint8_t n_z : 1;
1750 uint8_t p_v : 1;
1751 uint8_t n_v : 1;
1752#endif /* DRV_BYTE_ORDER */
1753} ism330dhcx_fsm_outs10_t;
1754
1755#define ISM330DHCX_FSM_OUTS11 0x56U
1756typedef struct
1757{
1758#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1759 uint8_t n_v : 1;
1760 uint8_t p_v : 1;
1761 uint8_t n_z : 1;
1762 uint8_t p_z : 1;
1763 uint8_t n_y : 1;
1764 uint8_t p_y : 1;
1765 uint8_t n_x : 1;
1766 uint8_t p_x : 1;
1767#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1768 uint8_t p_x : 1;
1769 uint8_t n_x : 1;
1770 uint8_t p_y : 1;
1771 uint8_t n_y : 1;
1772 uint8_t p_z : 1;
1773 uint8_t n_z : 1;
1774 uint8_t p_v : 1;
1775 uint8_t n_v : 1;
1776#endif /* DRV_BYTE_ORDER */
1777} ism330dhcx_fsm_outs11_t;
1778
1779#define ISM330DHCX_FSM_OUTS12 0x57U
1780typedef struct
1781{
1782#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1783 uint8_t n_v : 1;
1784 uint8_t p_v : 1;
1785 uint8_t n_z : 1;
1786 uint8_t p_z : 1;
1787 uint8_t n_y : 1;
1788 uint8_t p_y : 1;
1789 uint8_t n_x : 1;
1790 uint8_t p_x : 1;
1791#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1792 uint8_t p_x : 1;
1793 uint8_t n_x : 1;
1794 uint8_t p_y : 1;
1795 uint8_t n_y : 1;
1796 uint8_t p_z : 1;
1797 uint8_t n_z : 1;
1798 uint8_t p_v : 1;
1799 uint8_t n_v : 1;
1800#endif /* DRV_BYTE_ORDER */
1801} ism330dhcx_fsm_outs12_t;
1802
1803#define ISM330DHCX_FSM_OUTS13 0x58U
1804typedef struct
1805{
1806#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1807 uint8_t n_v : 1;
1808 uint8_t p_v : 1;
1809 uint8_t n_z : 1;
1810 uint8_t p_z : 1;
1811 uint8_t n_y : 1;
1812 uint8_t p_y : 1;
1813 uint8_t n_x : 1;
1814 uint8_t p_x : 1;
1815#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1816 uint8_t p_x : 1;
1817 uint8_t n_x : 1;
1818 uint8_t p_y : 1;
1819 uint8_t n_y : 1;
1820 uint8_t p_z : 1;
1821 uint8_t n_z : 1;
1822 uint8_t p_v : 1;
1823 uint8_t n_v : 1;
1824#endif /* DRV_BYTE_ORDER */
1825} ism330dhcx_fsm_outs13_t;
1826
1827#define ISM330DHCX_FSM_OUTS14 0x59U
1828typedef struct
1829{
1830#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1831 uint8_t n_v : 1;
1832 uint8_t p_v : 1;
1833 uint8_t n_z : 1;
1834 uint8_t p_z : 1;
1835 uint8_t n_y : 1;
1836 uint8_t p_y : 1;
1837 uint8_t n_x : 1;
1838 uint8_t p_x : 1;
1839#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1840 uint8_t p_x : 1;
1841 uint8_t n_x : 1;
1842 uint8_t p_y : 1;
1843 uint8_t n_y : 1;
1844 uint8_t p_z : 1;
1845 uint8_t n_z : 1;
1846 uint8_t p_v : 1;
1847 uint8_t n_v : 1;
1848#endif /* DRV_BYTE_ORDER */
1849} ism330dhcx_fsm_outs14_t;
1850
1851#define ISM330DHCX_FSM_OUTS15 0x5AU
1852typedef struct
1853{
1854#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1855 uint8_t n_v : 1;
1856 uint8_t p_v : 1;
1857 uint8_t n_z : 1;
1858 uint8_t p_z : 1;
1859 uint8_t n_y : 1;
1860 uint8_t p_y : 1;
1861 uint8_t n_x : 1;
1862 uint8_t p_x : 1;
1863#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1864 uint8_t p_x : 1;
1865 uint8_t n_x : 1;
1866 uint8_t p_y : 1;
1867 uint8_t n_y : 1;
1868 uint8_t p_z : 1;
1869 uint8_t n_z : 1;
1870 uint8_t p_v : 1;
1871 uint8_t n_v : 1;
1872#endif /* DRV_BYTE_ORDER */
1873} ism330dhcx_fsm_outs15_t;
1874
1875#define ISM330DHCX_FSM_OUTS16 0x5BU
1876typedef struct
1877{
1878#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1879 uint8_t n_v : 1;
1880 uint8_t p_v : 1;
1881 uint8_t n_z : 1;
1882 uint8_t p_z : 1;
1883 uint8_t n_y : 1;
1884 uint8_t p_y : 1;
1885 uint8_t n_x : 1;
1886 uint8_t p_x : 1;
1887#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1888 uint8_t p_x : 1;
1889 uint8_t n_x : 1;
1890 uint8_t p_y : 1;
1891 uint8_t n_y : 1;
1892 uint8_t p_z : 1;
1893 uint8_t n_z : 1;
1894 uint8_t p_v : 1;
1895 uint8_t n_v : 1;
1896#endif /* DRV_BYTE_ORDER */
1897} ism330dhcx_fsm_outs16_t;
1898
1899#define ISM330DHCX_EMB_FUNC_ODR_CFG_B 0x5FU
1900typedef struct
1901{
1902#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1903 uint8_t not_used_01 : 3;
1904 uint8_t fsm_odr : 2;
1905 uint8_t not_used_02 : 3;
1906#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1907 uint8_t not_used_02 : 3;
1908 uint8_t fsm_odr : 2;
1909 uint8_t not_used_01 : 3;
1910#endif /* DRV_BYTE_ORDER */
1911} ism330dhcx_emb_func_odr_cfg_b_t;
1912
1913#define ISM330DHCX_EMB_FUNC_ODR_CFG_C 0x60U
1914typedef struct
1915{
1916#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1917 uint8_t not_used_01 : 4;
1918 uint8_t mlc_odr : 2;
1919 uint8_t not_used_02 : 2;
1920#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1921 uint8_t not_used_02 : 2;
1922 uint8_t mlc_odr : 2;
1923 uint8_t not_used_01 : 4;
1924#endif /* DRV_BYTE_ORDER */
1925} ism330dhcx_emb_func_odr_cfg_c_t;
1926
1927#define ISM330DHCX_STEP_COUNTER_L 0x62U
1928#define ISM330DHCX_STEP_COUNTER_H 0x63U
1929#define ISM330DHCX_EMB_FUNC_SRC 0x64U
1930typedef struct
1931{
1932#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1933 uint8_t not_used_01 : 2;
1934 uint8_t stepcounter_bit_set : 1;
1935 uint8_t step_overflow : 1;
1936 uint8_t step_count_delta_ia : 1;
1937 uint8_t step_detected : 1;
1938 uint8_t not_used_02 : 1;
1939 uint8_t pedo_rst_step : 1;
1940#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1941 uint8_t pedo_rst_step : 1;
1942 uint8_t not_used_02 : 1;
1943 uint8_t step_detected : 1;
1944 uint8_t step_count_delta_ia : 1;
1945 uint8_t step_overflow : 1;
1946 uint8_t stepcounter_bit_set : 1;
1947 uint8_t not_used_01 : 2;
1948#endif /* DRV_BYTE_ORDER */
1949} ism330dhcx_emb_func_src_t;
1950
1951#define ISM330DHCX_EMB_FUNC_INIT_A 0x66U
1952typedef struct
1953{
1954#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1955 uint8_t not_used_01 : 3;
1956 uint8_t step_det_init : 1;
1957 uint8_t tilt_init : 1;
1958 uint8_t sig_mot_init : 1;
1959 uint8_t not_used_02 : 2;
1960#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1961 uint8_t not_used_02 : 2;
1962 uint8_t sig_mot_init : 1;
1963 uint8_t tilt_init : 1;
1964 uint8_t step_det_init : 1;
1965 uint8_t not_used_01 : 3;
1966#endif /* DRV_BYTE_ORDER */
1967} ism330dhcx_emb_func_init_a_t;
1968
1969#define ISM330DHCX_EMB_FUNC_INIT_B 0x67U
1970typedef struct
1971{
1972#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1973 uint8_t fsm_init : 1;
1974 uint8_t not_used_01 : 2;
1975 uint8_t fifo_compr_init : 1;
1976 uint8_t mlc_init : 1;
1977 uint8_t not_used_02 : 3;
1978#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1979 uint8_t not_used_02 : 3;
1980 uint8_t mlc_init : 1;
1981 uint8_t fifo_compr_init : 1;
1982 uint8_t not_used_01 : 2;
1983 uint8_t fsm_init : 1;
1984#endif /* DRV_BYTE_ORDER */
1985} ism330dhcx_emb_func_init_b_t;
1986
1987#define ISM330DHCX_MLC0_SRC 0x70U
1988#define ISM330DHCX_MLC1_SRC 0x71U
1989#define ISM330DHCX_MLC2_SRC 0x72U
1990#define ISM330DHCX_MLC3_SRC 0x73U
1991#define ISM330DHCX_MLC4_SRC 0x74U
1992#define ISM330DHCX_MLC5_SRC 0x75U
1993#define ISM330DHCX_MLC6_SRC 0x76U
1994#define ISM330DHCX_MLC7_SRC 0x77U
1995#define ISM330DHCX_MAG_SENSITIVITY_L 0xBAU
1996#define ISM330DHCX_MAG_SENSITIVITY_H 0xBBU
1997#define ISM330DHCX_MAG_OFFX_L 0xC0U
1998#define ISM330DHCX_MAG_OFFX_H 0xC1U
1999#define ISM330DHCX_MAG_OFFY_L 0xC2U
2000#define ISM330DHCX_MAG_OFFY_H 0xC3U
2001#define ISM330DHCX_MAG_OFFZ_L 0xC4U
2002#define ISM330DHCX_MAG_OFFZ_H 0xC5U
2003#define ISM330DHCX_MAG_SI_XX_L 0xC6U
2004#define ISM330DHCX_MAG_SI_XX_H 0xC7U
2005#define ISM330DHCX_MAG_SI_XY_L 0xC8U
2006#define ISM330DHCX_MAG_SI_XY_H 0xC9U
2007#define ISM330DHCX_MAG_SI_XZ_L 0xCAU
2008#define ISM330DHCX_MAG_SI_XZ_H 0xCBU
2009#define ISM330DHCX_MAG_SI_YY_L 0xCCU
2010#define ISM330DHCX_MAG_SI_YY_H 0xCDU
2011#define ISM330DHCX_MAG_SI_YZ_L 0xCEU
2012#define ISM330DHCX_MAG_SI_YZ_H 0xCFU
2013#define ISM330DHCX_MAG_SI_ZZ_L 0xD0U
2014#define ISM330DHCX_MAG_SI_ZZ_H 0xD1U
2015#define ISM330DHCX_MAG_CFG_A 0xD4U
2016typedef struct
2017{
2018#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2019 uint8_t mag_z_axis : 3;
2020 uint8_t not_used_01 : 1;
2021 uint8_t mag_y_axis : 3;
2022 uint8_t not_used_02 : 1;
2023#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2024 uint8_t not_used_02 : 1;
2025 uint8_t mag_y_axis : 3;
2026 uint8_t not_used_01 : 1;
2027 uint8_t mag_z_axis : 3;
2028#endif /* DRV_BYTE_ORDER */
2029} ism330dhcx_mag_cfg_a_t;
2030
2031#define ISM330DHCX_MAG_CFG_B 0xD5U
2032typedef struct
2033{
2034#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2035 uint8_t mag_x_axis : 3;
2036 uint8_t not_used_01 : 5;
2037#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2038 uint8_t not_used_01 : 5;
2039 uint8_t mag_x_axis : 3;
2040#endif /* DRV_BYTE_ORDER */
2041} ism330dhcx_mag_cfg_b_t;
2042
2043#define ISM330DHCX_FSM_LC_TIMEOUT_L 0x17AU
2044#define ISM330DHCX_FSM_LC_TIMEOUT_H 0x17BU
2045#define ISM330DHCX_FSM_PROGRAMS 0x17CU
2046#define ISM330DHCX_FSM_START_ADD_L 0x17EU
2047#define ISM330DHCX_FSM_START_ADD_H 0x17FU
2048#define ISM330DHCX_PEDO_CMD_REG 0x183U
2049typedef struct
2050{
2051#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2052 uint8_t not_used_01 : 3;
2053 uint8_t carry_count_en : 1;
2054 uint8_t not_used_02 : 4;
2055#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2056 uint8_t not_used_02 : 4;
2057 uint8_t carry_count_en : 1;
2058 uint8_t not_used_01 : 3;
2059#endif /* DRV_BYTE_ORDER */
2060} ism330dhcx_pedo_cmd_reg_t;
2061
2062#define ISM330DHCX_PEDO_DEB_STEPS_CONF 0x184U
2063#define ISM330DHCX_PEDO_SC_DELTAT_L 0x1D0U
2064#define ISM330DHCX_PEDO_SC_DELTAT_H 0x1D1U
2065#define ISM330DHCX_MLC_MAG_SENSITIVITY_L 0x1E8U
2066#define ISM330DHCX_MLC_MAG_SENSITIVITY_H 0x1E9U
2067#define ISM330DHCX_SENSOR_HUB_1 0x02U
2068typedef struct
2069{
2070#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2071 uint8_t bit0 : 1;
2072 uint8_t bit1 : 1;
2073 uint8_t bit2 : 1;
2074 uint8_t bit3 : 1;
2075 uint8_t bit4 : 1;
2076 uint8_t bit5 : 1;
2077 uint8_t bit6 : 1;
2078 uint8_t bit7 : 1;
2079#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2080 uint8_t bit7 : 1;
2081 uint8_t bit6 : 1;
2082 uint8_t bit5 : 1;
2083 uint8_t bit4 : 1;
2084 uint8_t bit3 : 1;
2085 uint8_t bit2 : 1;
2086 uint8_t bit1 : 1;
2087 uint8_t bit0 : 1;
2088#endif /* DRV_BYTE_ORDER */
2089} ism330dhcx_sensor_hub_1_t;
2090
2091#define ISM330DHCX_SENSOR_HUB_2 0x03U
2092typedef struct
2093{
2094#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2095 uint8_t bit0 : 1;
2096 uint8_t bit1 : 1;
2097 uint8_t bit2 : 1;
2098 uint8_t bit3 : 1;
2099 uint8_t bit4 : 1;
2100 uint8_t bit5 : 1;
2101 uint8_t bit6 : 1;
2102 uint8_t bit7 : 1;
2103#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2104 uint8_t bit7 : 1;
2105 uint8_t bit6 : 1;
2106 uint8_t bit5 : 1;
2107 uint8_t bit4 : 1;
2108 uint8_t bit3 : 1;
2109 uint8_t bit2 : 1;
2110 uint8_t bit1 : 1;
2111 uint8_t bit0 : 1;
2112#endif /* DRV_BYTE_ORDER */
2113} ism330dhcx_sensor_hub_2_t;
2114
2115#define ISM330DHCX_SENSOR_HUB_3 0x04U
2116typedef struct
2117{
2118#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2119 uint8_t bit0 : 1;
2120 uint8_t bit1 : 1;
2121 uint8_t bit2 : 1;
2122 uint8_t bit3 : 1;
2123 uint8_t bit4 : 1;
2124 uint8_t bit5 : 1;
2125 uint8_t bit6 : 1;
2126 uint8_t bit7 : 1;
2127#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2128 uint8_t bit7 : 1;
2129 uint8_t bit6 : 1;
2130 uint8_t bit5 : 1;
2131 uint8_t bit4 : 1;
2132 uint8_t bit3 : 1;
2133 uint8_t bit2 : 1;
2134 uint8_t bit1 : 1;
2135 uint8_t bit0 : 1;
2136#endif /* DRV_BYTE_ORDER */
2137} ism330dhcx_sensor_hub_3_t;
2138
2139#define ISM330DHCX_SENSOR_HUB_4 0x05U
2140typedef struct
2141{
2142#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2143 uint8_t bit0 : 1;
2144 uint8_t bit1 : 1;
2145 uint8_t bit2 : 1;
2146 uint8_t bit3 : 1;
2147 uint8_t bit4 : 1;
2148 uint8_t bit5 : 1;
2149 uint8_t bit6 : 1;
2150 uint8_t bit7 : 1;
2151#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2152 uint8_t bit7 : 1;
2153 uint8_t bit6 : 1;
2154 uint8_t bit5 : 1;
2155 uint8_t bit4 : 1;
2156 uint8_t bit3 : 1;
2157 uint8_t bit2 : 1;
2158 uint8_t bit1 : 1;
2159 uint8_t bit0 : 1;
2160#endif /* DRV_BYTE_ORDER */
2161} ism330dhcx_sensor_hub_4_t;
2162
2163#define ISM330DHCX_SENSOR_HUB_5 0x06U
2164typedef struct
2165{
2166#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2167 uint8_t bit0 : 1;
2168 uint8_t bit1 : 1;
2169 uint8_t bit2 : 1;
2170 uint8_t bit3 : 1;
2171 uint8_t bit4 : 1;
2172 uint8_t bit5 : 1;
2173 uint8_t bit6 : 1;
2174 uint8_t bit7 : 1;
2175#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2176 uint8_t bit7 : 1;
2177 uint8_t bit6 : 1;
2178 uint8_t bit5 : 1;
2179 uint8_t bit4 : 1;
2180 uint8_t bit3 : 1;
2181 uint8_t bit2 : 1;
2182 uint8_t bit1 : 1;
2183 uint8_t bit0 : 1;
2184#endif /* DRV_BYTE_ORDER */
2185} ism330dhcx_sensor_hub_5_t;
2186
2187#define ISM330DHCX_SENSOR_HUB_6 0x07U
2188typedef struct
2189{
2190#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2191 uint8_t bit0 : 1;
2192 uint8_t bit1 : 1;
2193 uint8_t bit2 : 1;
2194 uint8_t bit3 : 1;
2195 uint8_t bit4 : 1;
2196 uint8_t bit5 : 1;
2197 uint8_t bit6 : 1;
2198 uint8_t bit7 : 1;
2199#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2200 uint8_t bit7 : 1;
2201 uint8_t bit6 : 1;
2202 uint8_t bit5 : 1;
2203 uint8_t bit4 : 1;
2204 uint8_t bit3 : 1;
2205 uint8_t bit2 : 1;
2206 uint8_t bit1 : 1;
2207 uint8_t bit0 : 1;
2208#endif /* DRV_BYTE_ORDER */
2209} ism330dhcx_sensor_hub_6_t;
2210
2211#define ISM330DHCX_SENSOR_HUB_7 0x08U
2212typedef struct
2213{
2214#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2215 uint8_t bit0 : 1;
2216 uint8_t bit1 : 1;
2217 uint8_t bit2 : 1;
2218 uint8_t bit3 : 1;
2219 uint8_t bit4 : 1;
2220 uint8_t bit5 : 1;
2221 uint8_t bit6 : 1;
2222 uint8_t bit7 : 1;
2223#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2224 uint8_t bit7 : 1;
2225 uint8_t bit6 : 1;
2226 uint8_t bit5 : 1;
2227 uint8_t bit4 : 1;
2228 uint8_t bit3 : 1;
2229 uint8_t bit2 : 1;
2230 uint8_t bit1 : 1;
2231 uint8_t bit0 : 1;
2232#endif /* DRV_BYTE_ORDER */
2233} ism330dhcx_sensor_hub_7_t;
2234
2235#define ISM330DHCX_SENSOR_HUB_8 0x09U
2236typedef struct
2237{
2238#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2239 uint8_t bit0 : 1;
2240 uint8_t bit1 : 1;
2241 uint8_t bit2 : 1;
2242 uint8_t bit3 : 1;
2243 uint8_t bit4 : 1;
2244 uint8_t bit5 : 1;
2245 uint8_t bit6 : 1;
2246 uint8_t bit7 : 1;
2247#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2248 uint8_t bit7 : 1;
2249 uint8_t bit6 : 1;
2250 uint8_t bit5 : 1;
2251 uint8_t bit4 : 1;
2252 uint8_t bit3 : 1;
2253 uint8_t bit2 : 1;
2254 uint8_t bit1 : 1;
2255 uint8_t bit0 : 1;
2256#endif /* DRV_BYTE_ORDER */
2257} ism330dhcx_sensor_hub_8_t;
2258
2259#define ISM330DHCX_SENSOR_HUB_9 0x0AU
2260typedef struct
2261{
2262#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2263 uint8_t bit0 : 1;
2264 uint8_t bit1 : 1;
2265 uint8_t bit2 : 1;
2266 uint8_t bit3 : 1;
2267 uint8_t bit4 : 1;
2268 uint8_t bit5 : 1;
2269 uint8_t bit6 : 1;
2270 uint8_t bit7 : 1;
2271#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2272 uint8_t bit7 : 1;
2273 uint8_t bit6 : 1;
2274 uint8_t bit5 : 1;
2275 uint8_t bit4 : 1;
2276 uint8_t bit3 : 1;
2277 uint8_t bit2 : 1;
2278 uint8_t bit1 : 1;
2279 uint8_t bit0 : 1;
2280#endif /* DRV_BYTE_ORDER */
2281} ism330dhcx_sensor_hub_9_t;
2282
2283#define ISM330DHCX_SENSOR_HUB_10 0x0BU
2284typedef struct
2285{
2286#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2287 uint8_t bit0 : 1;
2288 uint8_t bit1 : 1;
2289 uint8_t bit2 : 1;
2290 uint8_t bit3 : 1;
2291 uint8_t bit4 : 1;
2292 uint8_t bit5 : 1;
2293 uint8_t bit6 : 1;
2294 uint8_t bit7 : 1;
2295#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2296 uint8_t bit7 : 1;
2297 uint8_t bit6 : 1;
2298 uint8_t bit5 : 1;
2299 uint8_t bit4 : 1;
2300 uint8_t bit3 : 1;
2301 uint8_t bit2 : 1;
2302 uint8_t bit1 : 1;
2303 uint8_t bit0 : 1;
2304#endif /* DRV_BYTE_ORDER */
2305} ism330dhcx_sensor_hub_10_t;
2306
2307#define ISM330DHCX_SENSOR_HUB_11 0x0CU
2308typedef struct
2309{
2310#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2311 uint8_t bit0 : 1;
2312 uint8_t bit1 : 1;
2313 uint8_t bit2 : 1;
2314 uint8_t bit3 : 1;
2315 uint8_t bit4 : 1;
2316 uint8_t bit5 : 1;
2317 uint8_t bit6 : 1;
2318 uint8_t bit7 : 1;
2319#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2320 uint8_t bit7 : 1;
2321 uint8_t bit6 : 1;
2322 uint8_t bit5 : 1;
2323 uint8_t bit4 : 1;
2324 uint8_t bit3 : 1;
2325 uint8_t bit2 : 1;
2326 uint8_t bit1 : 1;
2327 uint8_t bit0 : 1;
2328#endif /* DRV_BYTE_ORDER */
2329} ism330dhcx_sensor_hub_11_t;
2330
2331#define ISM330DHCX_SENSOR_HUB_12 0x0DU
2332typedef struct
2333{
2334#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2335 uint8_t bit0 : 1;
2336 uint8_t bit1 : 1;
2337 uint8_t bit2 : 1;
2338 uint8_t bit3 : 1;
2339 uint8_t bit4 : 1;
2340 uint8_t bit5 : 1;
2341 uint8_t bit6 : 1;
2342 uint8_t bit7 : 1;
2343#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2344 uint8_t bit7 : 1;
2345 uint8_t bit6 : 1;
2346 uint8_t bit5 : 1;
2347 uint8_t bit4 : 1;
2348 uint8_t bit3 : 1;
2349 uint8_t bit2 : 1;
2350 uint8_t bit1 : 1;
2351 uint8_t bit0 : 1;
2352#endif /* DRV_BYTE_ORDER */
2353} ism330dhcx_sensor_hub_12_t;
2354
2355#define ISM330DHCX_SENSOR_HUB_13 0x0EU
2356typedef struct
2357{
2358#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2359 uint8_t bit0 : 1;
2360 uint8_t bit1 : 1;
2361 uint8_t bit2 : 1;
2362 uint8_t bit3 : 1;
2363 uint8_t bit4 : 1;
2364 uint8_t bit5 : 1;
2365 uint8_t bit6 : 1;
2366 uint8_t bit7 : 1;
2367#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2368 uint8_t bit7 : 1;
2369 uint8_t bit6 : 1;
2370 uint8_t bit5 : 1;
2371 uint8_t bit4 : 1;
2372 uint8_t bit3 : 1;
2373 uint8_t bit2 : 1;
2374 uint8_t bit1 : 1;
2375 uint8_t bit0 : 1;
2376#endif /* DRV_BYTE_ORDER */
2377} ism330dhcx_sensor_hub_13_t;
2378
2379#define ISM330DHCX_SENSOR_HUB_14 0x0FU
2380typedef struct
2381{
2382#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2383 uint8_t bit0 : 1;
2384 uint8_t bit1 : 1;
2385 uint8_t bit2 : 1;
2386 uint8_t bit3 : 1;
2387 uint8_t bit4 : 1;
2388 uint8_t bit5 : 1;
2389 uint8_t bit6 : 1;
2390 uint8_t bit7 : 1;
2391#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2392 uint8_t bit7 : 1;
2393 uint8_t bit6 : 1;
2394 uint8_t bit5 : 1;
2395 uint8_t bit4 : 1;
2396 uint8_t bit3 : 1;
2397 uint8_t bit2 : 1;
2398 uint8_t bit1 : 1;
2399 uint8_t bit0 : 1;
2400#endif /* DRV_BYTE_ORDER */
2401} ism330dhcx_sensor_hub_14_t;
2402
2403#define ISM330DHCX_SENSOR_HUB_15 0x10U
2404typedef struct
2405{
2406#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2407 uint8_t bit0 : 1;
2408 uint8_t bit1 : 1;
2409 uint8_t bit2 : 1;
2410 uint8_t bit3 : 1;
2411 uint8_t bit4 : 1;
2412 uint8_t bit5 : 1;
2413 uint8_t bit6 : 1;
2414 uint8_t bit7 : 1;
2415#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2416 uint8_t bit7 : 1;
2417 uint8_t bit6 : 1;
2418 uint8_t bit5 : 1;
2419 uint8_t bit4 : 1;
2420 uint8_t bit3 : 1;
2421 uint8_t bit2 : 1;
2422 uint8_t bit1 : 1;
2423 uint8_t bit0 : 1;
2424#endif /* DRV_BYTE_ORDER */
2425} ism330dhcx_sensor_hub_15_t;
2426
2427#define ISM330DHCX_SENSOR_HUB_16 0x11U
2428typedef struct
2429{
2430#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2431 uint8_t bit0 : 1;
2432 uint8_t bit1 : 1;
2433 uint8_t bit2 : 1;
2434 uint8_t bit3 : 1;
2435 uint8_t bit4 : 1;
2436 uint8_t bit5 : 1;
2437 uint8_t bit6 : 1;
2438 uint8_t bit7 : 1;
2439#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2440 uint8_t bit7 : 1;
2441 uint8_t bit6 : 1;
2442 uint8_t bit5 : 1;
2443 uint8_t bit4 : 1;
2444 uint8_t bit3 : 1;
2445 uint8_t bit2 : 1;
2446 uint8_t bit1 : 1;
2447 uint8_t bit0 : 1;
2448#endif /* DRV_BYTE_ORDER */
2449} ism330dhcx_sensor_hub_16_t;
2450
2451#define ISM330DHCX_SENSOR_HUB_17 0x12U
2452typedef struct
2453{
2454#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2455 uint8_t bit0 : 1;
2456 uint8_t bit1 : 1;
2457 uint8_t bit2 : 1;
2458 uint8_t bit3 : 1;
2459 uint8_t bit4 : 1;
2460 uint8_t bit5 : 1;
2461 uint8_t bit6 : 1;
2462 uint8_t bit7 : 1;
2463#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2464 uint8_t bit7 : 1;
2465 uint8_t bit6 : 1;
2466 uint8_t bit5 : 1;
2467 uint8_t bit4 : 1;
2468 uint8_t bit3 : 1;
2469 uint8_t bit2 : 1;
2470 uint8_t bit1 : 1;
2471 uint8_t bit0 : 1;
2472#endif /* DRV_BYTE_ORDER */
2473} ism330dhcx_sensor_hub_17_t;
2474
2475#define ISM330DHCX_SENSOR_HUB_18 0x13U
2476typedef struct
2477{
2478#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2479 uint8_t bit0 : 1;
2480 uint8_t bit1 : 1;
2481 uint8_t bit2 : 1;
2482 uint8_t bit3 : 1;
2483 uint8_t bit4 : 1;
2484 uint8_t bit5 : 1;
2485 uint8_t bit6 : 1;
2486 uint8_t bit7 : 1;
2487#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2488 uint8_t bit7 : 1;
2489 uint8_t bit6 : 1;
2490 uint8_t bit5 : 1;
2491 uint8_t bit4 : 1;
2492 uint8_t bit3 : 1;
2493 uint8_t bit2 : 1;
2494 uint8_t bit1 : 1;
2495 uint8_t bit0 : 1;
2496#endif /* DRV_BYTE_ORDER */
2497} ism330dhcx_sensor_hub_18_t;
2498
2499#define ISM330DHCX_MASTER_CONFIG 0x14U
2500typedef struct
2501{
2502#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2503 uint8_t aux_sens_on : 2;
2504 uint8_t master_on : 1;
2505 uint8_t shub_pu_en : 1;
2506 uint8_t pass_through_mode : 1;
2507 uint8_t start_config : 1;
2508 uint8_t write_once : 1;
2509 uint8_t rst_master_regs : 1;
2510#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2511 uint8_t rst_master_regs : 1;
2512 uint8_t write_once : 1;
2513 uint8_t start_config : 1;
2514 uint8_t pass_through_mode : 1;
2515 uint8_t shub_pu_en : 1;
2516 uint8_t master_on : 1;
2517 uint8_t aux_sens_on : 2;
2518#endif /* DRV_BYTE_ORDER */
2519
2520} ism330dhcx_master_config_t;
2521
2522#define ISM330DHCX_SLV0_ADD 0x15U
2523typedef struct
2524{
2525#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2526 uint8_t rw_0 : 1;
2527 uint8_t slave0 : 7;
2528#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2529 uint8_t slave0 : 7;
2530 uint8_t rw_0 : 1;
2531#endif /* DRV_BYTE_ORDER */
2532
2533} ism330dhcx_slv0_add_t;
2534
2535#define ISM330DHCX_SLV0_SUBADD 0x16U
2536typedef struct
2537{
2538 uint8_t slave0_reg : 8;
2539} ism330dhcx_slv0_subadd_t;
2540
2541#define ISM330DHCX_SLV0_CONFIG 0x17U
2542typedef struct
2543{
2544#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2545 uint8_t slave0_numop : 3;
2546 uint8_t batch_ext_sens_0_en : 1;
2547 uint8_t not_used_01 : 2;
2548 uint8_t shub_odr : 2;
2549#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2550 uint8_t shub_odr : 2;
2551 uint8_t not_used_01 : 2;
2552 uint8_t batch_ext_sens_0_en : 1;
2553 uint8_t slave0_numop : 3;
2554#endif /* DRV_BYTE_ORDER */
2555
2556} ism330dhcx_slv0_config_t;
2557
2558#define ISM330DHCX_SLV1_ADD 0x18U
2559typedef struct
2560{
2561#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2562 uint8_t r_1 : 1;
2563 uint8_t slave1_add : 7;
2564#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2565 uint8_t slave1_add : 7;
2566 uint8_t r_1 : 1;
2567#endif /* DRV_BYTE_ORDER */
2568} ism330dhcx_slv1_add_t;
2569
2570#define ISM330DHCX_SLV1_SUBADD 0x19U
2571typedef struct
2572{
2573 uint8_t slave1_reg : 8;
2574} ism330dhcx_slv1_subadd_t;
2575
2576#define ISM330DHCX_SLV1_CONFIG 0x1AU
2577typedef struct
2578{
2579#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2580 uint8_t slave1_numop : 3;
2581 uint8_t batch_ext_sens_1_en : 1;
2582 uint8_t not_used_01 : 4;
2583#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2584 uint8_t not_used_01 : 4;
2585 uint8_t batch_ext_sens_1_en : 1;
2586 uint8_t slave1_numop : 3;
2587#endif /* DRV_BYTE_ORDER */
2588} ism330dhcx_slv1_config_t;
2589
2590#define ISM330DHCX_SLV2_ADD 0x1BU
2591typedef struct
2592{
2593#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2594 uint8_t r_2 : 1;
2595 uint8_t slave2_add : 7;
2596#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2597 uint8_t slave2_add : 7;
2598 uint8_t r_2 : 1;
2599#endif /* DRV_BYTE_ORDER */
2600} ism330dhcx_slv2_add_t;
2601
2602#define ISM330DHCX_SLV2_SUBADD 0x1CU
2603typedef struct
2604{
2605 uint8_t slave2_reg : 8;
2606} ism330dhcx_slv2_subadd_t;
2607
2608#define ISM330DHCX_SLV2_CONFIG 0x1DU
2609typedef struct
2610{
2611#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2612 uint8_t slave2_numop : 3;
2613 uint8_t batch_ext_sens_2_en : 1;
2614 uint8_t not_used_01 : 4;
2615#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2616 uint8_t not_used_01 : 4;
2617 uint8_t batch_ext_sens_2_en : 1;
2618 uint8_t slave2_numop : 3;
2619#endif /* DRV_BYTE_ORDER */
2620} ism330dhcx_slv2_config_t;
2621
2622#define ISM330DHCX_SLV3_ADD 0x1EU
2623typedef struct
2624{
2625#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2626 uint8_t r_3 : 1;
2627 uint8_t slave3_add : 7;
2628#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2629 uint8_t slave3_add : 7;
2630 uint8_t r_3 : 1;
2631#endif /* DRV_BYTE_ORDER */
2632} ism330dhcx_slv3_add_t;
2633
2634#define ISM330DHCX_SLV3_SUBADD 0x1FU
2635typedef struct
2636{
2637 uint8_t slave3_reg : 8;
2638} ism330dhcx_slv3_subadd_t;
2639
2640#define ISM330DHCX_SLV3_CONFIG 0x20U
2641typedef struct
2642{
2643#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2644 uint8_t slave3_numop : 3;
2645 uint8_t batch_ext_sens_3_en : 1;
2646 uint8_t not_used_01 : 4;
2647#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2648 uint8_t not_used_01 : 4;
2649 uint8_t batch_ext_sens_3_en : 1;
2650 uint8_t slave3_numop : 3;
2651#endif /* DRV_BYTE_ORDER */
2652} ism330dhcx_slv3_config_t;
2653
2654#define ISM330DHCX_DATAWRITE_SLV0 0x21U
2655typedef struct
2656{
2657 uint8_t slave0_dataw : 8;
2658} ism330dhcx_datawrite_slv0_t;
2659
2660#define ISM330DHCX_STATUS_MASTER 0x22U
2661typedef struct
2662{
2663#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2664 uint8_t sens_hub_endop : 1;
2665 uint8_t not_used_01 : 2;
2666 uint8_t slave0_nack : 1;
2667 uint8_t slave1_nack : 1;
2668 uint8_t slave2_nack : 1;
2669 uint8_t slave3_nack : 1;
2670 uint8_t wr_once_done : 1;
2671#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2672 uint8_t wr_once_done : 1;
2673 uint8_t slave3_nack : 1;
2674 uint8_t slave2_nack : 1;
2675 uint8_t slave1_nack : 1;
2676 uint8_t slave0_nack : 1;
2677 uint8_t not_used_01 : 2;
2678 uint8_t sens_hub_endop : 1;
2679#endif /* DRV_BYTE_ORDER */
2680} ism330dhcx_status_master_t;
2681
2682/**
2683 * @defgroup ISM330DHCX_Register_Union
2684 * @brief This union group all the registers having a bit-field
2685 * description.
2686 * This union is useful but it's not needed by the driver.
2687 *
2688 * REMOVING this union you are compliant with:
2689 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
2690 *
2691 * @{
2692 *
2693 */
2694typedef union
2695{
2696 ism330dhcx_func_cfg_access_t func_cfg_access;
2697 ism330dhcx_pin_ctrl_t pin_ctrl;
2698 ism330dhcx_fifo_ctrl1_t fifo_ctrl1;
2699 ism330dhcx_fifo_ctrl2_t fifo_ctrl2;
2700 ism330dhcx_fifo_ctrl3_t fifo_ctrl3;
2701 ism330dhcx_fifo_ctrl4_t fifo_ctrl4;
2702 ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1;
2703 ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2;
2704 ism330dhcx_int1_ctrl_t int1_ctrl;
2705 ism330dhcx_int2_ctrl_t int2_ctrl;
2706 ism330dhcx_ctrl1_xl_t ctrl1_xl;
2707 ism330dhcx_ctrl2_g_t ctrl2_g;
2708 ism330dhcx_ctrl3_c_t ctrl3_c;
2709 ism330dhcx_ctrl4_c_t ctrl4_c;
2710 ism330dhcx_ctrl5_c_t ctrl5_c;
2711 ism330dhcx_ctrl6_c_t ctrl6_c;
2712 ism330dhcx_ctrl7_g_t ctrl7_g;
2713 ism330dhcx_ctrl8_xl_t ctrl8_xl;
2714 ism330dhcx_ctrl9_xl_t ctrl9_xl;
2715 ism330dhcx_ctrl10_c_t ctrl10_c;
2716 ism330dhcx_all_int_src_t all_int_src;
2717 ism330dhcx_wake_up_src_t wake_up_src;
2718 ism330dhcx_tap_src_t tap_src;
2719 ism330dhcx_d6d_src_t d6d_src;
2720 ism330dhcx_status_reg_t status_reg;
2721 ism330dhcx_status_spiaux_t status_spiaux;
2722 ism330dhcx_fifo_status1_t fifo_status1;
2723 ism330dhcx_fifo_status2_t fifo_status2;
2724 ism330dhcx_tap_cfg0_t tap_cfg0;
2725 ism330dhcx_tap_cfg1_t tap_cfg1;
2726 ism330dhcx_tap_cfg2_t tap_cfg2;
2727 ism330dhcx_tap_ths_6d_t tap_ths_6d;
2728 ism330dhcx_int_dur2_t int_dur2;
2729 ism330dhcx_wake_up_ths_t wake_up_ths;
2730 ism330dhcx_wake_up_dur_t wake_up_dur;
2731 ism330dhcx_free_fall_t free_fall;
2732 ism330dhcx_md1_cfg_t md1_cfg;
2733 ism330dhcx_md2_cfg_t md2_cfg;
2734 ism330dhcx_internal_freq_fine_t internal_freq_fine;
2735 ism330dhcx_int_ois_t int_ois;
2736 ism330dhcx_ctrl1_ois_t ctrl1_ois;
2737 ism330dhcx_ctrl2_ois_t ctrl2_ois;
2738 ism330dhcx_ctrl3_ois_t ctrl3_ois;
2739 ism330dhcx_fifo_data_out_tag_t fifo_data_out_tag;
2740 ism330dhcx_page_sel_t page_sel;
2741 ism330dhcx_emb_func_en_a_t emb_func_en_a;
2742 ism330dhcx_emb_func_en_b_t emb_func_en_b;
2743 ism330dhcx_page_address_t page_address;
2744 ism330dhcx_page_value_t page_value;
2745 ism330dhcx_emb_func_int1_t emb_func_int1;
2746 ism330dhcx_fsm_int1_a_t fsm_int1_a;
2747 ism330dhcx_fsm_int1_b_t fsm_int1_b;
2748 ism330dhcx_emb_func_int2_t emb_func_int2;
2749 ism330dhcx_fsm_int2_a_t fsm_int2_a;
2750 ism330dhcx_fsm_int2_b_t fsm_int2_b;
2751 ism330dhcx_emb_func_status_t emb_func_status;
2752 ism330dhcx_fsm_status_a_t fsm_status_a;
2753 ism330dhcx_fsm_status_b_t fsm_status_b;
2754 ism330dhcx_page_rw_t page_rw;
2755 ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
2756 ism330dhcx_fsm_enable_a_t fsm_enable_a;
2757 ism330dhcx_fsm_enable_b_t fsm_enable_b;
2758 ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear;
2759 ism330dhcx_fsm_outs1_t fsm_outs1;
2760 ism330dhcx_fsm_outs2_t fsm_outs2;
2761 ism330dhcx_fsm_outs3_t fsm_outs3;
2762 ism330dhcx_fsm_outs4_t fsm_outs4;
2763 ism330dhcx_fsm_outs5_t fsm_outs5;
2764 ism330dhcx_fsm_outs6_t fsm_outs6;
2765 ism330dhcx_fsm_outs7_t fsm_outs7;
2766 ism330dhcx_fsm_outs8_t fsm_outs8;
2767 ism330dhcx_fsm_outs9_t fsm_outs9;
2768 ism330dhcx_fsm_outs10_t fsm_outs10;
2769 ism330dhcx_fsm_outs11_t fsm_outs11;
2770 ism330dhcx_fsm_outs12_t fsm_outs12;
2771 ism330dhcx_fsm_outs13_t fsm_outs13;
2772 ism330dhcx_fsm_outs14_t fsm_outs14;
2773 ism330dhcx_fsm_outs15_t fsm_outs15;
2774 ism330dhcx_fsm_outs16_t fsm_outs16;
2775 ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
2776 ism330dhcx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c_t;
2777 ism330dhcx_emb_func_src_t emb_func_src;
2778 ism330dhcx_emb_func_init_a_t emb_func_init_a;
2779 ism330dhcx_emb_func_init_b_t emb_func_init_b;
2780 ism330dhcx_mag_cfg_a_t mag_cfg_a;
2781 ism330dhcx_mag_cfg_b_t mag_cfg_b;
2782 ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg;
2783 ism330dhcx_sensor_hub_1_t sensor_hub_1;
2784 ism330dhcx_sensor_hub_2_t sensor_hub_2;
2785 ism330dhcx_sensor_hub_3_t sensor_hub_3;
2786 ism330dhcx_sensor_hub_4_t sensor_hub_4;
2787 ism330dhcx_sensor_hub_5_t sensor_hub_5;
2788 ism330dhcx_sensor_hub_6_t sensor_hub_6;
2789 ism330dhcx_sensor_hub_7_t sensor_hub_7;
2790 ism330dhcx_sensor_hub_8_t sensor_hub_8;
2791 ism330dhcx_sensor_hub_9_t sensor_hub_9;
2792 ism330dhcx_sensor_hub_10_t sensor_hub_10;
2793 ism330dhcx_sensor_hub_11_t sensor_hub_11;
2794 ism330dhcx_sensor_hub_12_t sensor_hub_12;
2795 ism330dhcx_sensor_hub_13_t sensor_hub_13;
2796 ism330dhcx_sensor_hub_14_t sensor_hub_14;
2797 ism330dhcx_sensor_hub_15_t sensor_hub_15;
2798 ism330dhcx_sensor_hub_16_t sensor_hub_16;
2799 ism330dhcx_sensor_hub_17_t sensor_hub_17;
2800 ism330dhcx_sensor_hub_18_t sensor_hub_18;
2801 ism330dhcx_master_config_t master_config;
2802 ism330dhcx_slv0_add_t slv0_add;
2803 ism330dhcx_slv0_subadd_t slv0_subadd;
2804 ism330dhcx_slv0_config_t slv0_config;
2805 ism330dhcx_slv1_add_t slv1_add;
2806 ism330dhcx_slv1_subadd_t slv1_subadd;
2807 ism330dhcx_slv1_config_t slv1_config;
2808 ism330dhcx_slv2_add_t slv2_add;
2809 ism330dhcx_slv2_subadd_t slv2_subadd;
2810 ism330dhcx_slv2_config_t slv2_config;
2811 ism330dhcx_slv3_add_t slv3_add;
2812 ism330dhcx_slv3_subadd_t slv3_subadd;
2813 ism330dhcx_slv3_config_t slv3_config;
2814 ism330dhcx_datawrite_slv0_t datawrite_slv0;
2815 ism330dhcx_status_master_t status_master;
2816 bitwise_t bitwise;
2817 uint8_t byte;
2818} ism330dhcx_reg_t;
2819
2820/**
2821 * @}
2822 *
2823 */
2824
2825int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
2826 uint8_t *data,
2827 uint16_t len);
2828int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
2829 uint8_t *data,
2830 uint16_t len);
2831
2832float ism330dhcx_from_fs2g_to_mg(int16_t lsb);
2833float ism330dhcx_from_fs4g_to_mg(int16_t lsb);
2834float ism330dhcx_from_fs8g_to_mg(int16_t lsb);
2835float ism330dhcx_from_fs16g_to_mg(int16_t lsb);
2836
2837float ism330dhcx_from_fs125dps_to_mdps(int16_t lsb);
2838float ism330dhcx_from_fs250dps_to_mdps(int16_t lsb);
2839float ism330dhcx_from_fs500dps_to_mdps(int16_t lsb);
2840float ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb);
2841float ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb);
2842float ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb);
2843
2844float ism330dhcx_from_lsb_to_celsius(int16_t lsb);
2845
2846float ism330dhcx_from_lsb_to_nsec(int32_t lsb);
2847
2848typedef enum
2849{
2850 ISM330DHCX_2g = 0,
2851 ISM330DHCX_16g = 1, /* if XL_FS_MODE = ‘1’ -> ISM330DHCX_2g */
2852 ISM330DHCX_4g = 2,
2853 ISM330DHCX_8g = 3,
2854} ism330dhcx_fs_xl_t;
2855int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx,
2856 ism330dhcx_fs_xl_t val);
2857int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx,
2858 ism330dhcx_fs_xl_t *val);
2859
2875int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx,
2876 ism330dhcx_odr_xl_t val);
2877int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx,
2878 ism330dhcx_odr_xl_t *val);
2879
2889int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx,
2890 ism330dhcx_fs_g_t val);
2891int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx,
2892 ism330dhcx_fs_g_t *val);
2893
2908int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx,
2909 ism330dhcx_odr_g_t val);
2910int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx,
2911 ism330dhcx_odr_g_t *val);
2912
2913int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx,
2914 uint8_t val);
2915int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx,
2916 uint8_t *val);
2917
2923int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx,
2924 ism330dhcx_usr_off_w_t val);
2925int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx,
2926 ism330dhcx_usr_off_w_t *val);
2927
2933int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx,
2934 ism330dhcx_xl_hm_mode_t val);
2935int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx,
2936 ism330dhcx_xl_hm_mode_t *val);
2937
2943int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx,
2944 ism330dhcx_g_hm_mode_t val);
2945int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx,
2946 ism330dhcx_g_hm_mode_t *val);
2947
2959int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx,
2960 ism330dhcx_all_sources_t *val);
2961
2962int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx,
2963 ism330dhcx_status_reg_t *val);
2964
2965int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
2966 uint8_t *val);
2967
2968int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
2969 uint8_t *val);
2970
2971int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
2972 uint8_t *val);
2973
2974int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
2975 uint8_t *buff);
2976int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
2977 uint8_t *buff);
2978
2979int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
2980 uint8_t *buff);
2981int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
2982 uint8_t *buff);
2983
2984int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
2985 uint8_t *buff);
2986int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
2987 uint8_t *buff);
2988
2989int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
2990int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
2991
2992int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx);
2993
2994int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
2995int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
2996
2997int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx,
2998 uint32_t *val);
2999
3007int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx,
3008 ism330dhcx_rounding_t val);
3009int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx,
3010 ism330dhcx_rounding_t *val);
3011
3012int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx,
3013 int16_t *val);
3014
3015int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx,
3016 int16_t *val);
3017
3018int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx,
3019 int16_t *val);
3020
3021int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
3022
3023int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
3024
3025int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val);
3026int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val);
3027
3028int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
3029int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
3030
3031int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx,
3032 uint16_t *val);
3033
3034int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx);
3035
3042int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx,
3043 ism330dhcx_reg_access_t val);
3044int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx,
3045 ism330dhcx_reg_access_t *val);
3046
3047int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx,
3048 uint16_t address,
3049 uint8_t *val);
3050int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
3051 uint8_t *buf, uint8_t len);
3052int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
3053 uint8_t *val);
3054int32_t ism330dhcx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
3055 uint8_t *val);
3056
3062int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx,
3063 ism330dhcx_dataready_pulsed_t val);
3064int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx,
3065 ism330dhcx_dataready_pulsed_t *val);
3066
3067int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
3068
3069int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val);
3070int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
3071
3072int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
3073int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx,
3074 uint8_t *val);
3075
3076int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val);
3077int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
3078
3085int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx,
3086 ism330dhcx_st_xl_t val);
3087int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx,
3088 ism330dhcx_st_xl_t *val);
3089
3096int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx,
3097 ism330dhcx_st_g_t val);
3098int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx,
3099 ism330dhcx_st_g_t *val);
3100
3101int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
3102int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
3103
3104int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
3105int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
3106
3107int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx,
3108 uint8_t val);
3109int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx,
3110 uint8_t *val);
3111
3123int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3124 ism330dhcx_ftype_t val);
3125int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3126 ism330dhcx_ftype_t *val);
3127
3128int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
3129int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
3130
3157int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
3158 ism330dhcx_hp_slope_xl_en_t val);
3159int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
3160 ism330dhcx_hp_slope_xl_en_t *val);
3161
3162int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx,
3163 uint8_t val);
3164int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx,
3165 uint8_t *val);
3166
3172int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
3173 ism330dhcx_slope_fds_t val);
3174int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
3175 ism330dhcx_slope_fds_t *val);
3176
3185int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
3186 ism330dhcx_hpm_g_t val);
3187int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
3188 ism330dhcx_hpm_g_t *val);
3189
3195int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
3196 ism330dhcx_ois_pu_dis_t val);
3197int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
3198 ism330dhcx_ois_pu_dis_t *val);
3199
3205int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
3206 ism330dhcx_ois_on_t val);
3207int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
3208 ism330dhcx_ois_on_t *val);
3209
3210int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx,
3211 ism330dhcx_status_spiaux_t *val);
3212
3213int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
3214 uint8_t *val);
3215
3216int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
3217 uint8_t *val);
3218
3219int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
3220 uint8_t *val);
3221
3228int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
3229 ism330dhcx_st_xl_ois_t val);
3230int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
3231 ism330dhcx_st_xl_ois_t *val);
3232
3238int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx,
3239 ism330dhcx_den_lh_ois_t val);
3240int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx,
3241 ism330dhcx_den_lh_ois_t *val);
3242
3249int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx,
3250 ism330dhcx_lvl2_ois_t val);
3251int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx,
3252 ism330dhcx_lvl2_ois_t *val);
3253
3254int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx,
3255 uint8_t val);
3256int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
3257 uint8_t *val);
3258
3265int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx,
3266 ism330dhcx_ois_en_spi2_t val);
3267int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx,
3268 ism330dhcx_ois_en_spi2_t *val);
3269
3278int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
3279 ism330dhcx_fs_g_ois_t val);
3280int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
3281 ism330dhcx_fs_g_ois_t *val);
3282
3288int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx,
3289 ism330dhcx_sim_ois_t val);
3290int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx,
3291 ism330dhcx_sim_ois_t *val);
3292
3300int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3301 ism330dhcx_ftype_ois_t val);
3302int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3303 ism330dhcx_ftype_ois_t *val);
3304
3313int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
3314 ism330dhcx_hpm_ois_t val);
3315int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
3316 ism330dhcx_hpm_ois_t *val);
3317
3323int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
3324 ism330dhcx_st_ois_clampdis_t val);
3325int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
3326 ism330dhcx_st_ois_clampdis_t *val);
3327
3334int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
3335 ism330dhcx_st_ois_t val);
3336int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
3337 ism330dhcx_st_ois_t *val);
3338
3350int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
3351 ism330dhcx_filter_xl_conf_ois_t val);
3352int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
3353 ism330dhcx_filter_xl_conf_ois_t *val);
3354
3362int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
3363 ism330dhcx_fs_xl_ois_t val);
3364int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
3365 ism330dhcx_fs_xl_ois_t *val);
3366
3372int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
3373 ism330dhcx_sdo_pu_en_t val);
3374int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
3375 ism330dhcx_sdo_pu_en_t *val);
3376
3382int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx,
3383 ism330dhcx_sim_t val);
3384int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx,
3385 ism330dhcx_sim_t *val);
3386
3392int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx,
3393 ism330dhcx_i2c_disable_t val);
3394int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx,
3395 ism330dhcx_i2c_disable_t *val);
3396
3406int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx,
3407 ism330dhcx_pin_int1_route_t *val);
3408int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx,
3409 ism330dhcx_pin_int1_route_t *val);
3410
3420int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx,
3421 ism330dhcx_pin_int2_route_t *val);
3422int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx,
3423 ism330dhcx_pin_int2_route_t *val);
3424
3430int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx,
3431 ism330dhcx_pp_od_t val);
3432int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx,
3433 ism330dhcx_pp_od_t *val);
3434
3440int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx,
3441 ism330dhcx_h_lactive_t val);
3442int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx,
3443 ism330dhcx_h_lactive_t *val);
3444
3445int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
3446int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
3447
3455int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx,
3456 ism330dhcx_lir_t val);
3457int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx,
3458 ism330dhcx_lir_t *val);
3459
3465int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
3466 ism330dhcx_wake_ths_w_t val);
3467int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
3468 ism330dhcx_wake_ths_w_t *val);
3469
3470int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
3471int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx,
3472 uint8_t *val);
3473
3474int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
3475 uint8_t val);
3476int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
3477 uint8_t *val);
3478
3479int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3480int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3481
3482int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
3483int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
3484
3490int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx,
3491 ism330dhcx_sleep_status_on_int_t val);
3492int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx,
3493 ism330dhcx_sleep_status_on_int_t *val);
3494
3502int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx,
3503 ism330dhcx_inact_en_t val);
3504int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx,
3505 ism330dhcx_inact_en_t *val);
3506
3507int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3508int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3509
3510int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
3511 uint8_t val);
3512int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
3513 uint8_t *val);
3514
3515int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
3516 uint8_t val);
3517int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
3518 uint8_t *val);
3519
3520int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
3521 uint8_t val);
3522int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
3523 uint8_t *val);
3524
3525int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx,
3526 uint8_t val);
3527int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx,
3528 uint8_t *val);
3529
3539int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx,
3540 ism330dhcx_tap_priority_t val);
3541int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx,
3542 ism330dhcx_tap_priority_t *val);
3543
3544int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx,
3545 uint8_t val);
3546int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx,
3547 uint8_t *val);
3548
3549int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx,
3550 uint8_t val);
3551int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx,
3552 uint8_t *val);
3553
3554int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
3555int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
3556
3557int32_t ism330dhcx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val);
3558int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
3559
3560int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3561int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3562
3568int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx,
3569 ism330dhcx_single_double_tap_t val);
3570int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx,
3571 ism330dhcx_single_double_tap_t *val);
3572
3580int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx,
3581 ism330dhcx_sixd_ths_t val);
3582int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx,
3583 ism330dhcx_sixd_ths_t *val);
3584
3585int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
3586int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
3587
3599int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx,
3600 ism330dhcx_ff_ths_t val);
3601int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx,
3602 ism330dhcx_ff_ths_t *val);
3603
3604int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3605int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3606
3607int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx,
3608 uint16_t val);
3609int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx,
3610 uint16_t *val);
3611
3612int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx,
3613 uint8_t val);
3614int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx,
3615 uint8_t *val);
3616
3625int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx,
3626 ism330dhcx_uncoptr_rate_t val);
3627int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx,
3628 ism330dhcx_uncoptr_rate_t *val);
3629
3630int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
3631 uint8_t val);
3632int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
3633 uint8_t *val);
3634
3635int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
3636 uint8_t val);
3637int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
3638 uint8_t *val);
3639
3640int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
3641 uint8_t val);
3642int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
3643 uint8_t *val);
3644
3660int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
3661 ism330dhcx_bdr_xl_t val);
3662int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
3663 ism330dhcx_bdr_xl_t *val);
3664
3680int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
3681 ism330dhcx_bdr_gy_t val);
3682int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
3683 ism330dhcx_bdr_gy_t *val);
3684
3694int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx,
3695 ism330dhcx_fifo_mode_t val);
3696int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx,
3697 ism330dhcx_fifo_mode_t *val);
3698
3706int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
3707 ism330dhcx_odr_t_batch_t val);
3708int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
3709 ism330dhcx_odr_t_batch_t *val);
3710
3718int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
3719 ism330dhcx_odr_ts_batch_t val);
3720int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
3721 ism330dhcx_odr_ts_batch_t *val);
3722
3728int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
3729 ism330dhcx_trig_counter_bdr_t val);
3730int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
3731 ism330dhcx_trig_counter_bdr_t *val);
3732
3733int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx,
3734 uint8_t val);
3735int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx,
3736 uint8_t *val);
3737
3738int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
3739 uint16_t val);
3740int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
3741 uint16_t *val);
3742
3743int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx,
3744 uint16_t *val);
3745
3746int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx,
3747 ism330dhcx_fifo_status2_t *val);
3748
3749int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx,
3750 uint8_t *val);
3751
3752int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
3753
3754int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
3755
3781int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
3782 ism330dhcx_fifo_tag_t *val);
3783
3784int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx,
3785 uint8_t val);
3786int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
3787 uint8_t *val);
3788
3789int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
3790 uint8_t val);
3791int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
3792 uint8_t *val);
3793
3794int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
3795 uint8_t val);
3796int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
3797 uint8_t *val);
3798
3799int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
3800 uint8_t val);
3801int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
3802 uint8_t *val);
3803
3804int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
3805 uint8_t val);
3806int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
3807 uint8_t *val);
3808
3817int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx,
3818 ism330dhcx_den_mode_t val);
3819int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx,
3820 ism330dhcx_den_mode_t *val);
3821
3827int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx,
3828 ism330dhcx_den_lh_t val);
3829int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx,
3830 ism330dhcx_den_lh_t *val);
3831
3838int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx,
3839 ism330dhcx_den_xl_g_t val);
3840int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx,
3841 ism330dhcx_den_xl_g_t *val);
3842
3843int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx,
3844 uint8_t val);
3845int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx,
3846 uint8_t *val);
3847
3848int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx,
3849 uint8_t val);
3850int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx,
3851 uint8_t *val);
3852
3853int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx,
3854 uint8_t val);
3855int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx,
3856 uint8_t *val);
3857
3858int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
3859int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
3860
3861int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx,
3862 uint8_t *val);
3863
3864int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
3865 uint8_t *buff);
3866int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
3867 uint8_t *buff);
3868
3869int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx,
3870 uint16_t val);
3871int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx,
3872 uint16_t *val);
3873
3879int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx,
3880 ism330dhcx_carry_count_en_t val);
3881int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx,
3882 ism330dhcx_carry_count_en_t *val);
3883
3884int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
3885int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
3886
3887int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
3888 uint8_t *val);
3889
3890int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
3891int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
3892
3893int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
3894 uint8_t *val);
3895
3896int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx,
3897 uint16_t val);
3898int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx,
3899 uint16_t *val);
3900
3901int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
3902int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
3903
3904int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx,
3905 uint16_t *val);
3906int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx,
3907 uint16_t *val);
3908
3918int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx,
3919 ism330dhcx_mag_z_axis_t val);
3920int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx,
3921 ism330dhcx_mag_z_axis_t *val);
3922
3932int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx,
3933 ism330dhcx_mag_y_axis_t val);
3934int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx,
3935 ism330dhcx_mag_y_axis_t *val);
3936
3946int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx,
3947 ism330dhcx_mag_x_axis_t val);
3948int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx,
3949 ism330dhcx_mag_x_axis_t *val);
3950
3951int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
3952 uint8_t *val);
3953
3954int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
3955int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
3956
3962int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx,
3963 ism330dhcx_emb_fsm_enable_t *val);
3964int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx,
3965 ism330dhcx_emb_fsm_enable_t *val);
3966
3967int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
3968int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
3969
3976int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx,
3977 ism330dhcx_fsm_lc_clr_t val);
3978int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx,
3979 ism330dhcx_fsm_lc_clr_t *val);
3980
4000int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx,
4001 ism330dhcx_fsm_out_t *val);
4002
4010int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx,
4011 ism330dhcx_fsm_odr_t val);
4012int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx,
4013 ism330dhcx_fsm_odr_t *val);
4014
4015int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
4016int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
4017
4018int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
4019 uint16_t val);
4020int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
4021 uint16_t *val);
4022
4023int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
4024 uint8_t *buff);
4025int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
4026 uint8_t *buff);
4027
4028int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx,
4029 uint16_t val);
4030int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx,
4031 uint16_t *val);
4032
4033int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val);
4034int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
4035
4036int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx,
4037 ism330dhcx_mlc_status_mainpage_t *val);
4038
4046int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx,
4047 ism330dhcx_mlc_odr_t val);
4048int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx,
4049 ism330dhcx_mlc_odr_t *val);
4050
4072int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
4073 ism330dhcx_emb_sh_read_t *val,
4074 uint8_t len);
4075
4083int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx,
4084 ism330dhcx_aux_sens_on_t val);
4085int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx,
4086 ism330dhcx_aux_sens_on_t *val);
4087
4088int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
4089int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
4090
4096int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx,
4097 ism330dhcx_shub_pu_en_t val);
4098int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx,
4099 ism330dhcx_shub_pu_en_t *val);
4100
4101int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx,
4102 uint8_t val);
4103int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx,
4104 uint8_t *val);
4105
4111int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
4112 ism330dhcx_start_config_t val);
4113int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
4114 ism330dhcx_start_config_t *val);
4115
4121int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx,
4122 ism330dhcx_write_once_t val);
4123int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx,
4124 ism330dhcx_write_once_t *val);
4125
4126int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx);
4127int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
4128
4136int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx,
4137 ism330dhcx_shub_odr_t val);
4138int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx,
4139 ism330dhcx_shub_odr_t *val);
4140
4141typedef struct
4142{
4143 uint8_t slv0_add;
4144 uint8_t slv0_subadd;
4145 uint8_t slv0_data;
4146} ism330dhcx_sh_cfg_write_t;
4147int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx,
4148 ism330dhcx_sh_cfg_write_t *val);
4149
4150typedef struct
4151{
4152 uint8_t slv_add;
4153 uint8_t slv_subadd;
4154 uint8_t slv_len;
4155} ism330dhcx_sh_cfg_read_t;
4156int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
4157 ism330dhcx_sh_cfg_read_t *val);
4158int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
4159 ism330dhcx_sh_cfg_read_t *val);
4160int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
4161 ism330dhcx_sh_cfg_read_t *val);
4162int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
4163 ism330dhcx_sh_cfg_read_t *val);
4164
4165int32_t ism330dhcx_sh_status_get(stmdev_ctx_t *ctx,
4166 ism330dhcx_status_master_t *val);
4167
4168/**
4169 *@}
4170 *
4171 */
4172
4173#ifdef __cplusplus
4174}
4175#endif
4176
4177#endif /* ISM330DHCX_REGS_H */
4178
4179/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
reg
uint8_t reg
Definition dev_h3lis100dl.c:19
ism330dhcx_sleep_status_on_int_t
ism330dhcx_sleep_status_on_int_t
Definition ism330dhcx_reg.h:3486
ism330dhcx_pedo_int_mode_set
int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx, ism330dhcx_carry_count_en_t val)
Set when user wants to generate interrupt on count overflow event/every step.
Definition ism330dhcx_reg.c:8620
ism330dhcx_aux_gy_lp1_bandwidth_set
int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, ism330dhcx_ftype_ois_t val)
Selects gyroscope digital LPF1 filter bandwidth.
Definition ism330dhcx_reg.c:3940
ism330dhcx_device_conf_get
int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val)
DEVICE_CONF bit configuration[get].
Definition ism330dhcx_reg.c:1896
ism330dhcx_fifo_mode_get
int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx, ism330dhcx_fifo_mode_t *val)
FIFO mode selection.
Definition ism330dhcx_reg.c:7152
ism330dhcx_tap_threshold_x_get
int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
X-axis tap recognition threshold.
Definition ism330dhcx_reg.c:5846
ism330dhcx_carry_count_en_t
ism330dhcx_carry_count_en_t
Definition ism330dhcx_reg.h:3875
ism330dhcx_tap_axis_priority_get
int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx, ism330dhcx_tap_priority_t *val)
Selection of axis priority for TAP detection[get].
Definition ism330dhcx_reg.c:5892
ism330dhcx_den_lh_t
ism330dhcx_den_lh_t
Definition ism330dhcx_reg.h:3823
ism330dhcx_den_lh_ois_t
ism330dhcx_den_lh_ois_t
Definition ism330dhcx_reg.h:3234
ism330dhcx_ois_on_t
ism330dhcx_ois_on_t
Definition ism330dhcx_reg.h:3201
ism330dhcx_sim_ois_t
ism330dhcx_sim_ois_t
Definition ism330dhcx_reg.h:3284
ism330dhcx_den_mode_set
int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx, ism330dhcx_den_mode_t val)
DEN functionality marking mode.
Definition ism330dhcx_reg.c:8092
ism330dhcx_den_polarity_set
int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx, ism330dhcx_den_lh_t val)
DEN active level configuration.
Definition ism330dhcx_reg.c:8164
ism330dhcx_aux_gy_clamp_set
int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx, ism330dhcx_st_ois_clampdis_t val)
Enable / Disables OIS chain clamp.
Definition ism330dhcx_reg.c:4083
ism330dhcx_trig_counter_bdr_t
ism330dhcx_trig_counter_bdr_t
Definition ism330dhcx_reg.h:3724
ism330dhcx_ff_dur_set
int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
Free-fall duration event(1LSb = 1 / ODR).
Definition ism330dhcx_reg.c:6472
ism330dhcx_fifo_xl_batch_set
int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx, ism330dhcx_bdr_xl_t val)
Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.
Definition ism330dhcx_reg.c:6923
ism330dhcx_sh_status_get
int32_t ism330dhcx_sh_status_get(stmdev_ctx_t *ctx, ism330dhcx_status_master_t *val)
Sensor hub source register.
Definition ism330dhcx_reg.c:11382
ism330dhcx_sh_master_get
int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
Sensor hub I2C master enable.
Definition ism330dhcx_reg.c:10626
ism330dhcx_fifo_temp_batch_set
int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx, ism330dhcx_odr_t_batch_t val)
Selects Batching Data Rate (writing frequency in FIFO) for temperature data.
Definition ism330dhcx_reg.c:7203
ism330dhcx_from_fs8g_to_mg
float ism330dhcx_from_fs8g_to_mg(int16_t lsb)
Definition ism330dhcx_reg.c:101
ism330dhcx_act_pin_notification_set
int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx, ism330dhcx_sleep_status_on_int_t val)
Drives the sleep status instead of sleep change on INT pins (only if INT1_SLEEP_CHANGE or INT2_SLEEP_...
Definition ism330dhcx_reg.c:5496
ism330dhcx_act_sleep_dur_get
int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
Duration to go in sleep mode.
Definition ism330dhcx_reg.c:5651
ism330dhcx_xl_hp_path_internal_get
int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, ism330dhcx_slope_fds_t *val)
HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.
Definition ism330dhcx_reg.c:3149
ism330dhcx_gy_self_test_get
int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx, ism330dhcx_st_g_t *val)
Angular rate sensor self-test enable.
Definition ism330dhcx_reg.c:2604
ism330dhcx_aux_xl_self_test_set
int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx, ism330dhcx_st_xl_ois_t val)
Selects accelerometer self-test.
Definition ism330dhcx_reg.c:3473
ism330dhcx_sh_batch_slave_0_set
int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
Enable FIFO batching data of first slave.
Definition ism330dhcx_reg.c:7808
ism330dhcx_fifo_gy_batch_set
int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx, ism330dhcx_bdr_gy_t val)
Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data.
Definition ism330dhcx_reg.c:7025
ism330dhcx_from_fs4000dps_to_mdps
float ism330dhcx_from_fs4000dps_to_mdps(int16_t lsb)
Definition ism330dhcx_reg.c:136
ism330dhcx_mag_offset_set
int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
Offset for hard-iron compensation register (r/w).
Definition ism330dhcx_reg.c:8962
ism330dhcx_wkup_threshold_get
int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR.
Definition ism330dhcx_reg.c:5328
ism330dhcx_wake_ths_w_t
ism330dhcx_wake_ths_w_t
Definition ism330dhcx_reg.h:3461
ism330dhcx_xl_offset_weight_get
int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx, ism330dhcx_usr_off_w_t *val)
Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h).
Definition ism330dhcx_reg.c:1048
ism330dhcx_xl_usr_offset_x_set
int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_...
Definition ism330dhcx_reg.c:1353
ism330dhcx_bdr_gy_t
ism330dhcx_bdr_gy_t
Definition ism330dhcx_reg.h:3666
ism330dhcx_mlc_data_rate_get
int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx, ism330dhcx_mlc_odr_t *val)
Machine Learning Core data rate selection.
Definition ism330dhcx_reg.c:10411
ism330dhcx_aux_sens_on_t
ism330dhcx_aux_sens_on_t
Definition ism330dhcx_reg.h:4077
ism330dhcx_xl_full_scale_get
int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx, ism330dhcx_fs_xl_t *val)
Accelerometer full-scale selection.
Definition ism330dhcx_reg.c:198
ism330dhcx_tilt_sens_set
int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
Enable tilt calculation.
Definition ism330dhcx_reg.c:8801
ism330dhcx_fifo_pedo_batch_set
int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
Enable FIFO batching of pedometer embedded function values.
Definition ism330dhcx_reg.c:7742
ism330dhcx_fs_g_t
ism330dhcx_fs_g_t
Definition ism330dhcx_reg.h:2881
ism330dhcx_pin_int2_route_set
int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx, ism330dhcx_pin_int2_route_t *val)
Select the signal that need to route on int2 pad[set].
Definition ism330dhcx_reg.c:4760
ism330dhcx_gy_full_scale_get
int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx, ism330dhcx_fs_g_t *val)
Gyroscope UI chain full-scale selection.
Definition ism330dhcx_reg.c:597
ism330dhcx_den_mark_axis_z_get
int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
DEN value stored in LSB of Z-axis.
Definition ism330dhcx_reg.c:8403
ism330dhcx_wkup_ths_weight_get
int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx, ism330dhcx_wake_ths_w_t *val)
Weight of 1 LSB of wakeup threshold.
Definition ism330dhcx_reg.c:5267
ism330dhcx_gy_flag_data_ready_get
int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
Gyroscope new data available.
Definition ism330dhcx_reg.c:1311
ism330dhcx_lvl2_ois_t
ism330dhcx_lvl2_ois_t
Definition ism330dhcx_reg.h:3244
ism330dhcx_fifo_tag_t
ism330dhcx_fifo_tag_t
Definition ism330dhcx_reg.h:3757
ism330dhcx_odr_g_t
ism330dhcx_odr_g_t
Definition ism330dhcx_reg.h:2895
ism330dhcx_compression_algo_get
int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t *val)
Enable and configure compression algo.
Definition ism330dhcx_reg.c:6735
ism330dhcx_single_double_tap_t
ism330dhcx_single_double_tap_t
Definition ism330dhcx_reg.h:3564
ism330dhcx_angular_rate_raw_get
int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
Angular rate sensor.
Definition ism330dhcx_reg.c:1705
ism330dhcx_timestamp_raw_get
int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
Timestamp first data output register (r).
Definition ism330dhcx_reg.c:1581
ism330dhcx_from_fs2g_to_mg
float ism330dhcx_from_fs2g_to_mg(int16_t lsb)
Definition ism330dhcx_reg.c:91
ism330dhcx_gy_filter_lp1_set
int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
Enables gyroscope digital LPF1 if auxiliary SPI is disabled; the bandwidth can be selected through FT...
Definition ism330dhcx_reg.c:2700
ism330dhcx_inact_en_t
ism330dhcx_inact_en_t
Definition ism330dhcx_reg.h:3496
ism330dhcx_aux_mode_set
int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx, ism330dhcx_ois_en_spi2_t val)
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data...
Definition ism330dhcx_reg.c:3736
ism330dhcx_fsm_number_of_programs_set
int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff)
FSM number of programs register.
Definition ism330dhcx_reg.c:10167
ism330dhcx_gy_power_mode_get
int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx, ism330dhcx_g_hm_mode_t *val)
gy_power_mode: [get] Operating mode for gyroscope.
Definition ism330dhcx_reg.c:1168
ism330dhcx_wkup_threshold_set
int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR.
Definition ism330dhcx_reg.c:5302
ism330dhcx_long_clr_get
int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx, ism330dhcx_fsm_lc_clr_t *val)
Clear FSM long counter value.
Definition ism330dhcx_reg.c:9871
ism330dhcx_device_id_get
int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
Device Who am I.
Definition ism330dhcx_reg.c:2362
ism330dhcx_tap_detection_on_y_get
int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable Y direction in tap recognition.
Definition ism330dhcx_reg.c:5755
ism330dhcx_gy_hp_path_internal_get
int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, ism330dhcx_hpm_g_t *val)
Enables gyroscope digital high-pass filter.
Definition ism330dhcx_reg.c:3212
ism330dhcx_filter_settling_mask_set
int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
Mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).
Definition ism330dhcx_reg.c:2746
ism330dhcx_aux_den_polarity_set
int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx, ism330dhcx_den_lh_ois_t val)
Indicates polarity of DEN signal on OIS chain.
Definition ism330dhcx_reg.c:3538
ism330dhcx_uncoptr_rate_t
ism330dhcx_uncoptr_rate_t
Definition ism330dhcx_reg.h:3618
ism330dhcx_den_xl_g_t
ism330dhcx_den_xl_g_t
Definition ism330dhcx_reg.h:3833
ism330dhcx_sh_data_rate_get
int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx, ism330dhcx_shub_odr_t *val)
Rate at which the master communicates.
Definition ism330dhcx_reg.c:11068
ism330dhcx_ftype_t
ism330dhcx_ftype_t
Definition ism330dhcx_reg.h:3113
ism330dhcx_from_fs4g_to_mg
float ism330dhcx_from_fs4g_to_mg(int16_t lsb)
Definition ism330dhcx_reg.c:96
ism330dhcx_mag_offset_get
int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
Offset for hard-iron compensation register (r/w).
Definition ism330dhcx_reg.c:9023
ism330dhcx_xl_self_test_get
int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx, ism330dhcx_st_xl_t *val)
Linear acceleration sensor self-test enable.
Definition ism330dhcx_reg.c:2540
ism330dhcx_fifo_watermark_get
int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
FIFO watermark level selection.
Definition ism330dhcx_reg.c:6584
ism330dhcx_ln_pg_read
int32_t ism330dhcx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val)
ism330dhcx_hp_slope_xl_en_t
ism330dhcx_hp_slope_xl_en_t
Definition ism330dhcx_reg.h:3132
ism330dhcx_xl_power_mode_get
int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx, ism330dhcx_xl_hm_mode_t *val)
Accelerometer power mode[get].
Definition ism330dhcx_reg.c:1108
ism330dhcx_tap_shock_set
int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap e...
Definition ism330dhcx_reg.c:6036
ism330dhcx_dataready_pulsed_t
ism330dhcx_dataready_pulsed_t
Definition ism330dhcx_reg.h:3058
ism330dhcx_long_cnt_int_value_get
int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
FSM long counter timeout register (r/w).
Definition ism330dhcx_reg.c:10137
ism330dhcx_wkup_ths_weight_set
int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx, ism330dhcx_wake_ths_w_t val)
Weight of 1 LSB of wakeup threshold.
Definition ism330dhcx_reg.c:5239
ism330dhcx_usr_off_w_t
ism330dhcx_usr_off_w_t
Definition ism330dhcx_reg.h:2919
ism330dhcx_sh_slv2_cfg_read
int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val)
Configure slave 2 for perform a write/read.
Definition ism330dhcx_reg.c:11277
ism330dhcx_odr_cal_reg_set
int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical.
Definition ism330dhcx_reg.c:1917
ism330dhcx_xl_usr_offset_y_set
int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
Accelerometer Y-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_...
Definition ism330dhcx_reg.c:1391
ism330dhcx_aux_xl_self_test_get
int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx, ism330dhcx_st_xl_ois_t *val)
Selects accelerometer self-test.
Definition ism330dhcx_reg.c:3500
ism330dhcx_xl_power_mode_set
int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx, ism330dhcx_xl_hm_mode_t val)
Accelerometer power mode.
Definition ism330dhcx_reg.c:1082
ism330dhcx_xl_flag_data_ready_get
int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
Accelerometer new data available.
Definition ism330dhcx_reg.c:1291
ism330dhcx_mag_y_orient_set
int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx, ism330dhcx_mag_y_axis_t val)
Magnetometer Y-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation).
Definition ism330dhcx_reg.c:9394
ism330dhcx_mag_x_orient_set
int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx, ism330dhcx_mag_x_axis_t val)
Magnetometer X-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation).
Definition ism330dhcx_reg.c:9472
ism330dhcx_sh_batch_slave_1_get
int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable FIFO batching data of second slave.
Definition ism330dhcx_reg.c:7913
ism330dhcx_aux_status_reg_get
int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx, ism330dhcx_status_spiaux_t *val)
The STATUS_SPIAux register is read by the auxiliary SPI.
Definition ism330dhcx_reg.c:3394
ism330dhcx_pedo_int_mode_get
int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx, ism330dhcx_carry_count_en_t *val)
Set when user wants to generate interrupt on count overflow event/every step.
Definition ism330dhcx_reg.c:8647
ism330dhcx_fifo_watermark_set
int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
FIFO watermark level selection.
Definition ism330dhcx_reg.c:6551
ism330dhcx_wkup_dur_set
int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
Wake up duration event(1LSb = 1 / ODR).
Definition ism330dhcx_reg.c:5393
ism330dhcx_fifo_virtual_sens_odr_chg_set
int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val)
Enables ODR CHANGE virtual sensor to be batched in FIFO.
Definition ism330dhcx_reg.c:6782
ism330dhcx_start_config_t
ism330dhcx_start_config_t
Definition ism330dhcx_reg.h:4107
ism330dhcx_xl_offset_weight_set
int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx, ism330dhcx_usr_off_w_t val)
Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h).
Definition ism330dhcx_reg.c:1021
ism330dhcx_aux_gy_lp1_bandwidth_get
int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, ism330dhcx_ftype_ois_t *val)
Selects gyroscope digital LPF1 filter bandwidth.
Definition ism330dhcx_reg.c:3966
ism330dhcx_gy_lp1_bandwidth_set
int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, ism330dhcx_ftype_t val)
Gyroscope low pass filter 1 bandwidth.
Definition ism330dhcx_reg.c:2793
ism330dhcx_compression_algo_real_time_get
int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables/Disables compression algorithm runtime.
Definition ism330dhcx_reg.c:6854
ism330dhcx_filter_xl_conf_ois_t
ism330dhcx_filter_xl_conf_ois_t
Definition ism330dhcx_reg.h:3340
ism330dhcx_sh_pin_mode_set
int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx, ism330dhcx_shub_pu_en_t val)
Master I2C pull-up enable.
Definition ism330dhcx_reg.c:10655
ism330dhcx_xl_hm_mode_t
ism330dhcx_xl_hm_mode_t
Definition ism330dhcx_reg.h:2929
ism330dhcx_pin_polarity_get
int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx, ism330dhcx_h_lactive_t *val)
Interrupt active-high/low.
Definition ism330dhcx_reg.c:5035
ism330dhcx_mlc_odr_t
ism330dhcx_mlc_odr_t
Definition ism330dhcx_reg.h:4040
ism330dhcx_sh_pass_through_set
int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
I2C interface pass-through.
Definition ism330dhcx_reg.c:10735
ism330dhcx_int_notification_get
int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx, ism330dhcx_lir_t *val)
All interrupt signals notification mode.
Definition ism330dhcx_reg.c:5164
ism330dhcx_mlc_set
int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
Enable Machine Learning Core.
Definition ism330dhcx_reg.c:10284
ism330dhcx_gy_full_scale_set
int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx, ism330dhcx_fs_g_t val)
Gyroscope UI chain full-scale selection.
Definition ism330dhcx_reg.c:571
ism330dhcx_sh_data_rate_set
int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx, ism330dhcx_shub_odr_t val)
Rate at which the master communicates.
Definition ism330dhcx_reg.c:11032
ism330dhcx_from_lsb_to_celsius
float ism330dhcx_from_lsb_to_celsius(int16_t lsb)
Definition ism330dhcx_reg.c:141
ism330dhcx_tilt_sens_get
int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable tilt calculation.
Definition ism330dhcx_reg.c:8836
ism330dhcx_fifo_mode_t
ism330dhcx_fifo_mode_t
Definition ism330dhcx_reg.h:3686
ism330dhcx_tap_axis_priority_set
int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx, ism330dhcx_tap_priority_t val)
Selection of axis priority for TAP detection.
Definition ism330dhcx_reg.c:5866
ism330dhcx_4d_mode_get
int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4D orientation detection enable.
Definition ism330dhcx_reg.c:6356
ism330dhcx_aux_drdy_on_int2_set
int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
Enables/Disable OIS chain DRDY on INT2 pin.
Definition ism330dhcx_reg.c:3684
ism330dhcx_pin_polarity_set
int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx, ism330dhcx_h_lactive_t val)
Interrupt active-high/low.
Definition ism330dhcx_reg.c:5009
ism330dhcx_aux_spi_mode_get
int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx, ism330dhcx_sim_ois_t *val)
SPI2 3- or 4-wire interface.
Definition ism330dhcx_reg.c:3906
ism330dhcx_tilt_flag_data_ready_get
int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
Interrupt status bit for tilt detection.
Definition ism330dhcx_reg.c:8865
ism330dhcx_gy_sleep_mode_set
int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
Enables gyroscope Sleep mode.
Definition ism330dhcx_reg.c:5450
ism330dhcx_tap_threshold_y_get
int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
Y-axis tap recognition threshold.
Definition ism330dhcx_reg.c:5967
ism330dhcx_sh_slv1_cfg_read
int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val)
Configure slave 0 for perform a write/read.
Definition ism330dhcx_reg.c:11223
ism330dhcx_sh_master_set
int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
Sensor hub I2C master enable.
Definition ism330dhcx_reg.c:10591
ism330dhcx_read_reg
int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len)
Read generic device register.
Definition ism330dhcx_reg.c:49
ism330dhcx_fifo_ovr_flag_get
int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
FIFO overrun status.
Definition ism330dhcx_reg.c:7589
ism330dhcx_fifo_temp_batch_get
int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx, ism330dhcx_odr_t_batch_t *val)
Selects Batching Data Rate (writing frequency in FIFO) for temperature data.
Definition ism330dhcx_reg.c:7230
ism330dhcx_emb_fsm_en_set
int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
Embedded final state machine functions mode.
Definition ism330dhcx_reg.c:9593
ism330dhcx_aux_xl_bandwidth_get
int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, ism330dhcx_filter_xl_conf_ois_t *val)
Selects accelerometer OIS channel bandwidth.
Definition ism330dhcx_reg.c:4235
ism330dhcx_all_on_int1_set
int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
All interrupt signals become available on INT1 pin.
Definition ism330dhcx_reg.c:5069
ism330dhcx_aux_den_polarity_get
int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx, ism330dhcx_den_lh_ois_t *val)
Indicates polarity of DEN signal on OIS chain.
Definition ism330dhcx_reg.c:3564
ism330dhcx_timestamp_set
int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
Enables timestamp counter.
Definition ism330dhcx_reg.c:1535
ism330dhcx_from_fs250dps_to_mdps
float ism330dhcx_from_fs250dps_to_mdps(int16_t lsb)
Definition ism330dhcx_reg.c:116
ism330dhcx_all_on_int1_get
int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
All interrupt signals become available on INT1 pin.
Definition ism330dhcx_reg.c:5094
ism330dhcx_pedo_steps_period_set
int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
Time period register for step detection on delta time (r/w).
Definition ism330dhcx_reg.c:8565
ism330dhcx_den_mark_axis_y_set
int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
DEN value stored in LSB of Y-axis.
Definition ism330dhcx_reg.c:8333
ism330dhcx_motion_flag_data_ready_get
int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
Interrupt status bit for significant motion detection.
Definition ism330dhcx_reg.c:8758
ism330dhcx_rounding_mode_get
int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx, ism330dhcx_rounding_t *val)
Gyroscope UI chain full-scale selection.
Definition ism330dhcx_reg.c:1640
ism330dhcx_fifo_out_raw_get
int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
FIFO data output.
Definition ism330dhcx_reg.c:1754
ism330dhcx_status_reg_get
int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx, ism330dhcx_status_reg_t *val)
The STATUS_REG register is read by the primary interface.
Definition ism330dhcx_reg.c:1274
ism330dhcx_sh_reset_set
int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx)
Reset Master logic and output registers.
Definition ism330dhcx_reg.c:10961
ism330dhcx_fifo_sensor_tag_get
int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, ism330dhcx_fifo_tag_t *val)
Identifies the sensor in FIFO_DATA_OUT.
Definition ism330dhcx_reg.c:7627
ism330dhcx_temp_flag_data_ready_get
int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
Temperature new data available.
Definition ism330dhcx_reg.c:1331
ism330dhcx_spi_mode_get
int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, ism330dhcx_sim_t *val)
SPI Serial Interface Mode selection.
Definition ism330dhcx_reg.c:4460
ism330dhcx_tap_detection_on_x_set
int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
Enable X direction in tap recognition.
Definition ism330dhcx_reg.c:5775
ism330dhcx_ln_pg_write_byte
int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val)
Write a line(byte) in a page.
Definition ism330dhcx_reg.c:2030
ism330dhcx_den_mode_get
int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx, ism330dhcx_den_mode_t *val)
DEN functionality marking mode.
Definition ism330dhcx_reg.c:8118
ism330dhcx_ff_dur_get
int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
Free-fall duration event(1LSb = 1 / ODR).
Definition ism330dhcx_reg.c:6511
ism330dhcx_aux_gy_self_test_set
int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx, ism330dhcx_st_ois_t val)
Selects gyroscope OIS chain self-test.
Definition ism330dhcx_reg.c:4145
ism330dhcx_auto_increment_set
int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
Register address automatically incremented during a multiple byte access with a serial interface.
Definition ism330dhcx_reg.c:2423
ism330dhcx_from_fs125dps_to_mdps
float ism330dhcx_from_fs125dps_to_mdps(int16_t lsb)
Definition ism330dhcx_reg.c:111
ism330dhcx_fsm_number_of_programs_get
int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff)
FSM number of programs register.
Definition ism330dhcx_reg.c:10191
ism330dhcx_boot_get
int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
Reboot memory content.
Definition ism330dhcx_reg.c:2493
ism330dhcx_pin_int1_route_get
int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx, ism330dhcx_pin_int1_route_t *val)
Select the signal that need to route on int1 pad.
Definition ism330dhcx_reg.c:4701
ism330dhcx_lir_t
ism330dhcx_lir_t
Definition ism330dhcx_reg.h:3449
ism330dhcx_fs_xl_ois_t
ism330dhcx_fs_xl_ois_t
Definition ism330dhcx_reg.h:3356
ism330dhcx_tap_threshold_y_set
int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
Y-axis tap recognition threshold.
Definition ism330dhcx_reg.c:5942
ism330dhcx_hpm_g_t
ism330dhcx_hpm_g_t
Definition ism330dhcx_reg.h:3178
ism330dhcx_pedo_step_detect_get
int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
Interrupt status bit for step detection.
Definition ism330dhcx_reg.c:8499
ism330dhcx_den_mark_axis_x_get
int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
DEN value stored in LSB of X-axis.
Definition ism330dhcx_reg.c:8313
ism330dhcx_block_data_update_get
int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
Block data update.
Definition ism330dhcx_reg.c:1000
ism330dhcx_fifo_pedo_batch_get
int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable FIFO batching of pedometer embedded function values.
Definition ism330dhcx_reg.c:7778
ism330dhcx_g_hm_mode_t
ism330dhcx_g_hm_mode_t
Definition ism330dhcx_reg.h:2939
ism330dhcx_motion_sens_set
int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
Enable significant motion detection function.
Definition ism330dhcx_reg.c:8694
ism330dhcx_from_fs2000dps_to_mdps
float ism330dhcx_from_fs2000dps_to_mdps(int16_t lsb)
Definition ism330dhcx_reg.c:131
ism330dhcx_aux_gy_flag_data_ready_get
int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
AUX gyroscope data available.
Definition ism330dhcx_reg.c:3432
ism330dhcx_odr_t_batch_t
ism330dhcx_odr_t_batch_t
Definition ism330dhcx_reg.h:3700
ism330dhcx_sh_slv0_cfg_read
int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val)
Configure slave 0 for perform a write/read.
Definition ism330dhcx_reg.c:11169
ism330dhcx_aux_gy_hp_bandwidth_get
int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, ism330dhcx_hpm_ois_t *val)
Selects gyroscope OIS chain digital high-pass filter cutoff.
Definition ism330dhcx_reg.c:4035
ism330dhcx_mlc_data_rate_set
int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx, ism330dhcx_mlc_odr_t val)
Machine Learning Core data rate selection.
Definition ism330dhcx_reg.c:10375
ism330dhcx_aux_xl_bandwidth_set
int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, ism330dhcx_filter_xl_conf_ois_t val)
Selects accelerometer OIS channel bandwidth.
Definition ism330dhcx_reg.c:4209
ism330dhcx_act_mode_set
int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx, ism330dhcx_inact_en_t val)
Enable inactivity function.
Definition ism330dhcx_reg.c:5558
ism330dhcx_reset_get
int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
Software reset.
Definition ism330dhcx_reg.c:2403
ism330dhcx_sh_write_mode_get
int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx, ism330dhcx_write_once_t *val)
Slave 0 write operation is performed only at the first sensor hub cycle.
Definition ism330dhcx_reg.c:10918
ism330dhcx_data_ready_mode_get
int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx, ism330dhcx_dataready_pulsed_t *val)
Data-ready pulsed / letched mode.
Definition ism330dhcx_reg.c:2328
ism330dhcx_sdo_sa0_mode_set
int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, ism330dhcx_sdo_pu_en_t val)
Connect/Disconnect SDO/SA0 internal pull-up.
Definition ism330dhcx_reg.c:4374
ism330dhcx_sh_batch_slave_2_set
int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
Enable FIFO batching data of third slave.
Definition ism330dhcx_reg.c:7944
ism330dhcx_xl_full_scale_set
int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx, ism330dhcx_fs_xl_t val)
Accelerometer full-scale selection[set].
Definition ism330dhcx_reg.c:172
ism330dhcx_sh_batch_slave_1_set
int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
Enable FIFO batching data of second slave.
Definition ism330dhcx_reg.c:7876
ism330dhcx_mag_z_orient_set
int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx, ism330dhcx_mag_z_axis_t val)
Magnetometer Z-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation).
Definition ism330dhcx_reg.c:9315
ism330dhcx_pedo_sens_set
int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
Enable pedometer algorithm.
Definition ism330dhcx_reg.c:8435
ism330dhcx_gy_lp1_bandwidth_get
int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, ism330dhcx_ftype_t *val)
Gyroscope low pass filter 1 bandwidth.
Definition ism330dhcx_reg.c:2819
ism330dhcx_aux_sdo_ocs_mode_set
int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, ism330dhcx_ois_pu_dis_t val)
On auxiliary interface connect/disconnect SDO and OCS internal pull-up.
Definition ism330dhcx_reg.c:3272
ism330dhcx_timestamp_get
int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables timestamp counter.
Definition ism330dhcx_reg.c:1560
ism330dhcx_sh_syncro_mode_get
int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx, ism330dhcx_start_config_t *val)
Sensor hub trigger signal selection.
Definition ism330dhcx_reg.c:10836
ism330dhcx_compression_algo_real_time_set
int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx, uint8_t val)
Enables/Disables compression algorithm runtime[set].
Definition ism330dhcx_reg.c:6828
ism330dhcx_sixd_ths_t
ism330dhcx_sixd_ths_t
Definition ism330dhcx_reg.h:3574
ism330dhcx_tap_threshold_z_set
int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
Z-axis recognition threshold.
Definition ism330dhcx_reg.c:5987
ism330dhcx_tap_threshold_z_get
int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
Z-axis recognition threshold.
Definition ism330dhcx_reg.c:6012
ism330dhcx_fsm_enable_set
int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx, ism330dhcx_emb_fsm_enable_t *val)
Embedded final state machine functions mode.
Definition ism330dhcx_reg.c:9663
ism330dhcx_aux_pw_on_ctrl_set
int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, ism330dhcx_ois_on_t val)
OIS chain on aux interface power on mode.
Definition ism330dhcx_reg.c:3333
ism330dhcx_rst_batch_counter_set
int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
Resets the internal counter of batching events for a single sensor.
Definition ism330dhcx_reg.c:7410
ism330dhcx_ois_en_spi2_t
ism330dhcx_ois_en_spi2_t
Definition ism330dhcx_reg.h:3260
ism330dhcx_hpm_ois_t
ism330dhcx_hpm_ois_t
Definition ism330dhcx_reg.h:3306
ism330dhcx_xl_usr_offset_on_wkup_set
int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
Wake up duration event( 1LSb = 1 / ODR ).
Definition ism330dhcx_reg.c:5347
ism330dhcx_batch_counter_threshold_get
int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx, uint16_t *val)
Batch data rate counter.
Definition ism330dhcx_reg.c:7494
ism330dhcx_mem_bank_get
int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx, ism330dhcx_reg_access_t *val)
Enable access to the embedded functions/sensor hub configuration registers.
Definition ism330dhcx_reg.c:1991
ism330dhcx_aux_gy_clamp_get
int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx, ism330dhcx_st_ois_clampdis_t *val)
Enable / Disables OIS chain clamp.
Definition ism330dhcx_reg.c:4111
ism330dhcx_sh_pin_mode_get
int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx, ism330dhcx_shub_pu_en_t *val)
Master I2C pull-up enable.
Definition ism330dhcx_reg.c:10691
ism330dhcx_fifo_wtm_flag_get
int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
FIFO watermark status.
Definition ism330dhcx_reg.c:7608
ism330dhcx_shub_odr_t
ism330dhcx_shub_odr_t
Definition ism330dhcx_reg.h:4130
ism330dhcx_tap_detection_on_x_get
int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable X direction in tap recognition.
Definition ism330dhcx_reg.c:5801
ism330dhcx_den_enable_set
int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx, ism330dhcx_den_xl_g_t val)
DEN configuration.
Definition ism330dhcx_reg.c:8224
ism330dhcx_ff_threshold_get
int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx, ism330dhcx_ff_ths_t *val)
Free fall threshold setting.
Definition ism330dhcx_reg.c:6414
ism330dhcx_pin_mode_get
int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx, ism330dhcx_pp_od_t *val)
Push-pull/open drain selection on interrupt pads.
Definition ism330dhcx_reg.c:4975
ism330dhcx_pedo_steps_period_get
int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx, uint16_t *val)
Time period register for step detection on delta time (r/w).
Definition ism330dhcx_reg.c:8592
ism330dhcx_xl_lp2_on_6d_set
int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
Low pass filter 2 on 6D function selection.
Definition ism330dhcx_reg.c:2877
ism330dhcx_xl_data_rate_set
int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx, ism330dhcx_odr_xl_t val)
Accelerometer UI data rate selection.
Definition ism330dhcx_reg.c:240
ism330dhcx_aux_den_mode_set
int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx, ism330dhcx_lvl2_ois_t val)
Configure DEN mode on the OIS chain.
Definition ism330dhcx_reg.c:3598
ism330dhcx_tap_dur_get
int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
When double tap recognition is enabled, this register expresses the maximum time between two consecut...
Definition ism330dhcx_reg.c:6171
ism330dhcx_pin_mode_set
int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx, ism330dhcx_pp_od_t val)
Push-pull/open drain selection on interrupt pads.
Definition ism330dhcx_reg.c:4949
ism330dhcx_boot_set
int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val)
Reboot memory content.
Definition ism330dhcx_reg.c:2468
ism330dhcx_fsm_start_address_get
int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
FSM start address register (r/w).
Definition ism330dhcx_reg.c:10240
ism330dhcx_aux_spi_mode_set
int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx, ism330dhcx_sim_ois_t val)
SPI2 3- or 4-wire interface.
Definition ism330dhcx_reg.c:3880
ism330dhcx_aux_xl_flag_data_ready_get
int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
AUX accelerometer data available.
Definition ism330dhcx_reg.c:3412
ism330dhcx_fifo_cnt_event_batch_get
int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, ism330dhcx_trig_counter_bdr_t *val)
Selects the trigger for the internal counter of batching events between XL and gyro.
Definition ism330dhcx_reg.c:7375
ism330dhcx_write_once_t
ism330dhcx_write_once_t
Definition ism330dhcx_reg.h:4117
ism330dhcx_from_fs500dps_to_mdps
float ism330dhcx_from_fs500dps_to_mdps(int16_t lsb)
Definition ism330dhcx_reg.c:121
ism330dhcx_from_fs1000dps_to_mdps
float ism330dhcx_from_fs1000dps_to_mdps(int16_t lsb)
Definition ism330dhcx_reg.c:126
ism330dhcx_pedo_debounce_steps_set
int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t *buff)
Pedometer debounce configuration register (r/w).
Definition ism330dhcx_reg.c:8529
ism330dhcx_st_ois_t
ism330dhcx_st_ois_t
Definition ism330dhcx_reg.h:3329
ism330dhcx_rst_batch_counter_get
int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
Resets the internal counter of batching events for a single sensor.
Definition ism330dhcx_reg.c:7437
ism330dhcx_6d_threshold_set
int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx, ism330dhcx_sixd_ths_t val)
Threshold for 4D/6D function.
Definition ism330dhcx_reg.c:6263
ism330dhcx_6d_threshold_get
int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx, ism330dhcx_sixd_ths_t *val)
Threshold for 4D/6D function.
Definition ism330dhcx_reg.c:6289
ism330dhcx_compression_algo_init_set
int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, uint8_t val)
FIFO compression feature initialization request.
Definition ism330dhcx_reg.c:6613
ism330dhcx_mag_soft_iron_get
int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
Definition ism330dhcx_reg.c:9204
ism330dhcx_xl_usr_offset_x_get
int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_...
Definition ism330dhcx_reg.c:1372
ism330dhcx_fifo_xl_batch_get
int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx, ism330dhcx_bdr_xl_t *val)
Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.
Definition ism330dhcx_reg.c:6950
ism330dhcx_gy_self_test_set
int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx, ism330dhcx_st_g_t val)
Angular rate sensor self-test enable.
Definition ism330dhcx_reg.c:2578
ism330dhcx_fsm_odr_t
ism330dhcx_fsm_odr_t
Definition ism330dhcx_reg.h:4004
ism330dhcx_fifo_full_flag_get
int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
Smart FIFO full status.
Definition ism330dhcx_reg.c:7569
ism330dhcx_mag_x_orient_get
int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx, ism330dhcx_mag_x_axis_t *val)
Magnetometer X-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation).
Definition ism330dhcx_reg.c:9499
ism330dhcx_tap_priority_t
ism330dhcx_tap_priority_t
Definition ism330dhcx_reg.h:3531
ism330dhcx_tap_detection_on_y_set
int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
Enable Y direction in tap recognition.
Definition ism330dhcx_reg.c:5729
ism330dhcx_aux_gy_flag_settling_get
int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
High when the gyroscope output is in the settling phase.
Definition ism330dhcx_reg.c:3452
ism330dhcx_tap_detection_on_z_set
int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
Enable Z direction in tap recognition.
Definition ism330dhcx_reg.c:5683
ism330dhcx_xl_lp2_on_6d_get
int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
Low pass filter 2 on 6D function selection.
Definition ism330dhcx_reg.c:2902
ism330dhcx_reg_access_t
ism330dhcx_reg_access_t
Definition ism330dhcx_reg.h:3037
ism330dhcx_steps_reset
int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx)
Reset step counter register.
Definition ism330dhcx_reg.c:1799
ism330dhcx_temperature_raw_get
int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
Temperature data output register (r).
Definition ism330dhcx_reg.c:1684
ism330dhcx_shub_pu_en_t
ism330dhcx_shub_pu_en_t
Definition ism330dhcx_reg.h:4092
ism330dhcx_xl_filter_lp2_get
int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
Accelerometer output from LPF2 filtering stage selection.
Definition ism330dhcx_reg.c:2680
ism330dhcx_aux_mode_get
int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx, ism330dhcx_ois_en_spi2_t *val)
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data...
Definition ism330dhcx_reg.c:3769
ism330dhcx_gy_data_rate_set
int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx, ism330dhcx_odr_g_t val)
Gyroscope data rate.
Definition ism330dhcx_reg.c:647
ism330dhcx_xl_usr_offset_z_get
int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_...
Definition ism330dhcx_reg.c:1448
ism330dhcx_mag_x_axis_t
ism330dhcx_mag_x_axis_t
Definition ism330dhcx_reg.h:3938
ism330dhcx_tap_dur_set
int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
When double tap recognition is enabled, this register expresses the maximum time between two consecut...
Definition ism330dhcx_reg.c:6142
ism330dhcx_fifo_timestamp_decimation_set
int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, ism330dhcx_odr_ts_batch_t val)
Selects decimation for timestamp batching in FIFO.
Definition ism330dhcx_reg.c:7274
ism330dhcx_ff_threshold_set
int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx, ism330dhcx_ff_ths_t val)
Free fall threshold setting.
Definition ism330dhcx_reg.c:6388
ism330dhcx_sim_t
ism330dhcx_sim_t
Definition ism330dhcx_reg.h:3378
ism330dhcx_ln_pg_read_byte
int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, uint8_t *val)
Read a line(byte) in a page.
Definition ism330dhcx_reg.c:2223
ism330dhcx_long_cnt_set
int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
FSM long counter status register.
Definition ism330dhcx_reg.c:9773
ism330dhcx_mlc_get
int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable Machine Learning Core.
Definition ism330dhcx_reg.c:10332
ism330dhcx_xl_usr_offset_on_wkup_get
int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, uint8_t *val)
Wake up duration event( 1LSb = 1 / ODR ).
Definition ism330dhcx_reg.c:5373
ism330dhcx_i2c_disable_t
ism330dhcx_i2c_disable_t
Definition ism330dhcx_reg.h:3388
ism330dhcx_sdo_pu_en_t
ism330dhcx_sdo_pu_en_t
Definition ism330dhcx_reg.h:3368
ism330dhcx_ois_pu_dis_t
ism330dhcx_ois_pu_dis_t
Definition ism330dhcx_reg.h:3191
ism330dhcx_xl_data_rate_get
int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx, ism330dhcx_odr_xl_t *val)
Accelerometer UI data rate selection.
Definition ism330dhcx_reg.c:497
ism330dhcx_slope_fds_t
ism330dhcx_slope_fds_t
Definition ism330dhcx_reg.h:3168
ism330dhcx_xl_fast_settling_set
int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
Enables accelerometer LPF2 and HPF fast-settling mode.
Definition ism330dhcx_reg.c:3073
ism330dhcx_aux_sdo_ocs_mode_get
int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, ism330dhcx_ois_pu_dis_t *val)
On auxiliary interface connect/disconnect SDO and OCS internal pull-up.
Definition ism330dhcx_reg.c:3299
ism330dhcx_fifo_mode_set
int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx, ism330dhcx_fifo_mode_t val)
FIFO mode selection.
Definition ism330dhcx_reg.c:7126
ism330dhcx_aux_xl_full_scale_get
int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, ism330dhcx_fs_xl_ois_t *val)
Selects accelerometer OIS channel full-scale.
Definition ism330dhcx_reg.c:4319
ism330dhcx_fifo_data_level_get
int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
Number of unread sensor data (TAG + 6 bytes) stored in FIFO.
Definition ism330dhcx_reg.c:7523
ism330dhcx_sh_write_mode_set
int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx, ism330dhcx_write_once_t val)
Slave 0 write operation is performed only at the first sensor hub cycle.
Definition ism330dhcx_reg.c:10881
ism330dhcx_fifo_status_get
int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx, ism330dhcx_fifo_status2_t *val)
Smart FIFO status.
Definition ism330dhcx_reg.c:7551
ism330dhcx_fifo_stop_on_wtm_set
int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
Sensing chain FIFO stop values memorization at threshold level.
Definition ism330dhcx_reg.c:6875
ism330dhcx_timestamp_rst
int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx)
Reset timestamp counter.
Definition ism330dhcx_reg.c:1521
ism330dhcx_gy_data_rate_get
int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx, ism330dhcx_odr_g_t *val)
Gyroscope data rate.
Definition ism330dhcx_reg.c:904
ism330dhcx_data_ready_mode_set
int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx, ism330dhcx_dataready_pulsed_t val)
Data-ready pulsed / letched mode.
Definition ism330dhcx_reg.c:2301
ism330dhcx_tap_quiet_get
int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
Quiet time is the time after the first detected tap in which there must not be any overthreshold even...
Definition ism330dhcx_reg.c:6117
ism330dhcx_bdr_xl_t
ism330dhcx_bdr_xl_t
Definition ism330dhcx_reg.h:3646
ism330dhcx_tap_mode_get
int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx, ism330dhcx_single_double_tap_t *val)
Single/double-tap event enable.
Definition ism330dhcx_reg.c:6216
ism330dhcx_sh_batch_slave_3_get
int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable FIFO batching data of fourth slave.
Definition ism330dhcx_reg.c:8049
ism330dhcx_mag_soft_iron_set
int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
Definition ism330dhcx_reg.c:9090
ism330dhcx_mag_sensitivity_set
int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
External magnetometer sensitivity value register.
Definition ism330dhcx_reg.c:8908
ism330dhcx_xl_usr_offset_z_set
int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
Accelerometer Z-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_...
Definition ism330dhcx_reg.c:1429
ism330dhcx_tap_threshold_x_set
int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
X-axis tap recognition threshold.
Definition ism330dhcx_reg.c:5821
ism330dhcx_4d_mode_set
int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4D orientation detection enable.
Definition ism330dhcx_reg.c:6331
ism330dhcx_emb_fsm_en_get
int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
Embedded final state machine functions mode.
Definition ism330dhcx_reg.c:9628
ism330dhcx_den_mark_axis_z_set
int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
DEN value stored in LSB of Z-axis.
Definition ism330dhcx_reg.c:8378
ism330dhcx_pedo_debounce_steps_get
int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *buff)
Pedometer debounce configuration register (r/w).
Definition ism330dhcx_reg.c:8547
ism330dhcx_ftype_ois_t
ism330dhcx_ftype_ois_t
Definition ism330dhcx_reg.h:3294
ism330dhcx_filter_settling_mask_get
int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val)
Mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).
Definition ism330dhcx_reg.c:2773
ism330dhcx_batch_counter_threshold_set
int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
Batch data rate counter.
Definition ism330dhcx_reg.c:7458
ism330dhcx_pin_int2_route_get
int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx, ism330dhcx_pin_int2_route_t *val)
Select the signal that need to route on int2 pad.
Definition ism330dhcx_reg.c:4891
ism330dhcx_tap_mode_set
int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx, ism330dhcx_single_double_tap_t val)
Single/double-tap event enable.
Definition ism330dhcx_reg.c:6190
ism330dhcx_int_notification_set
int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx, ism330dhcx_lir_t val)
All interrupt signals notification mode.
Definition ism330dhcx_reg.c:5113
ism330dhcx_compression_algo_init_get
int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx, uint8_t *val)
FIFO compression feature initialization request.
Definition ism330dhcx_reg.c:6650
ism330dhcx_odr_xl_t
ism330dhcx_odr_xl_t
Definition ism330dhcx_reg.h:2861
ism330dhcx_den_mark_axis_y_get
int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
DEN value stored in LSB of Y-axis.
Definition ism330dhcx_reg.c:8358
ism330dhcx_gy_filter_lp1_get
int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables gyroscope digital LPF1 if auxiliary SPI is disabled; the bandwidth can be selected through FT...
Definition ism330dhcx_reg.c:2726
ism330dhcx_st_ois_clampdis_t
ism330dhcx_st_ois_clampdis_t
Definition ism330dhcx_reg.h:3319
ism330dhcx_fsm_out_get
int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx, ism330dhcx_fsm_out_t *val)
FSM output registers.
Definition ism330dhcx_reg.c:9919
ism330dhcx_odr_ts_batch_t
ism330dhcx_odr_ts_batch_t
Definition ism330dhcx_reg.h:3712
ism330dhcx_den_enable_get
int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx, ism330dhcx_den_xl_g_t *val)
DEN configuration.
Definition ism330dhcx_reg.c:8250
ism330dhcx_tap_detection_on_z_get
int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable Z direction in tap recognition.
Definition ism330dhcx_reg.c:5709
ism330dhcx_xl_hp_path_on_out_set
int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, ism330dhcx_hp_slope_xl_en_t val)
Accelerometer slope filter / high-pass filter selection on output.
Definition ism330dhcx_reg.c:2922
ism330dhcx_gy_sleep_mode_get
int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables gyroscope Sleep mode.
Definition ism330dhcx_reg.c:5475
ism330dhcx_aux_gy_full_scale_get
int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, ism330dhcx_fs_g_ois_t *val)
Selects gyroscope OIS chain full-scale.
Definition ism330dhcx_reg.c:3834
ism330dhcx_xl_usr_offset_set
int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
Enables user offset on out.
Definition ism330dhcx_reg.c:1465
ism330dhcx_long_cnt_flag_data_ready_get
int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
Interrupt status bit for FSM long counter timeout interrupt event.
Definition ism330dhcx_reg.c:9563
ism330dhcx_sh_slave_connected_get
int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx, ism330dhcx_aux_sens_on_t *val)
Number of external sensors to be read by the sensor hub.
Definition ism330dhcx_reg.c:10539
ism330dhcx_sh_slave_connected_set
int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx, ism330dhcx_aux_sens_on_t val)
Number of external sensors to be read by the sensor hub.
Definition ism330dhcx_reg.c:10503
ism330dhcx_rounding_mode_set
int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx, ism330dhcx_rounding_t val)
Circular burst-mode (rounding) read of the output registers.
Definition ism330dhcx_reg.c:1614
ism330dhcx_auto_increment_get
int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
Register address automatically incremented during a multiple byte access with a serial interface.
Definition ism330dhcx_reg.c:2449
ism330dhcx_fifo_gy_batch_get
int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx, ism330dhcx_bdr_gy_t *val)
Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data.
Definition ism330dhcx_reg.c:7052
ism330dhcx_fifo_cnt_event_batch_set
int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, ism330dhcx_trig_counter_bdr_t val)
Selects the trigger for the internal counter of batching events between XL and gyro.
Definition ism330dhcx_reg.c:7347
ism330dhcx_rounding_t
ism330dhcx_rounding_t
Definition ism330dhcx_reg.h:3001
ism330dhcx_act_pin_notification_get
int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx, ism330dhcx_sleep_status_on_int_t *val)
Drives the sleep status instead of sleep change on INT pins (only if INT1_SLEEP_CHANGE or INT2_SLEEP_...
Definition ism330dhcx_reg.c:5524
ism330dhcx_mag_z_orient_get
int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx, ism330dhcx_mag_z_axis_t *val)
Magnetometer Z-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation).
Definition ism330dhcx_reg.c:9342
ism330dhcx_sh_batch_slave_2_get
int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable FIFO batching data of third slave.
Definition ism330dhcx_reg.c:7981
ism330dhcx_sdo_sa0_mode_get
int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, ism330dhcx_sdo_pu_en_t *val)
Connect/Disconnect SDO/SA0 internal pull-up.
Definition ism330dhcx_reg.c:4400
ism330dhcx_aux_drdy_on_int2_get
int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables/Disable OIS chain DRDY on INT2 pin.
Definition ism330dhcx_reg.c:3711
ism330dhcx_fifo_stop_on_wtm_get
int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
Sensing chain FIFO stop values memorization at threshold level.
Definition ism330dhcx_reg.c:6902
ism330dhcx_xl_fast_settling_get
int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables accelerometer LPF2 and HPF fast-settling mode.
Definition ism330dhcx_reg.c:3101
ism330dhcx_from_fs16g_to_mg
float ism330dhcx_from_fs16g_to_mg(int16_t lsb)
Definition ism330dhcx_reg.c:106
ism330dhcx_fsm_data_rate_get
int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx, ism330dhcx_fsm_odr_t *val)
Finite State Machine ODR configuration.
Definition ism330dhcx_reg.c:9985
ism330dhcx_mag_y_orient_get
int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx, ism330dhcx_mag_y_axis_t *val)
Magnetometer Y-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation).
Definition ism330dhcx_reg.c:9421
ism330dhcx_motion_sens_get
int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable significant motion detection function.
Definition ism330dhcx_reg.c:8729
ism330dhcx_wkup_dur_get
int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
Wake up duration event(1LSb = 1 / ODR).
Definition ism330dhcx_reg.c:5418
ism330dhcx_reset_set
int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val)
Software reset.
Definition ism330dhcx_reg.c:2378
ism330dhcx_act_mode_get
int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx, ism330dhcx_inact_en_t *val)
Enable inactivity function.
Definition ism330dhcx_reg.c:5584
ism330dhcx_fsm_init_get
int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
FSM initialization request.
Definition ism330dhcx_reg.c:10072
ism330dhcx_xl_hp_path_on_out_get
int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, ism330dhcx_hp_slope_xl_en_t *val)
Accelerometer slope filter / high-pass filter selection on output.
Definition ism330dhcx_reg.c:2951
ism330dhcx_block_data_update_set
int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
Block data update.
Definition ism330dhcx_reg.c:974
ism330dhcx_sh_slv3_cfg_read
int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val)
Configure slave 3 for perform a write/read.
Definition ism330dhcx_reg.c:11331
ism330dhcx_xl_hp_path_internal_set
int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, ism330dhcx_slope_fds_t val)
HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.
Definition ism330dhcx_reg.c:3122
ism330dhcx_aux_gy_self_test_get
int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx, ism330dhcx_st_ois_t *val)
Selects gyroscope OIS chain self-test.
Definition ism330dhcx_reg.c:4171
ism330dhcx_mlc_out_get
int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
prgsens_out: [get] Output value of all MLCx decision trees.
Definition ism330dhcx_reg.c:1833
ism330dhcx_mag_y_axis_t
ism330dhcx_mag_y_axis_t
Definition ism330dhcx_reg.h:3924
ism330dhcx_xl_self_test_set
int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx, ism330dhcx_st_xl_t val)
Linear acceleration sensor self-test enable.
Definition ism330dhcx_reg.c:2514
ism330dhcx_xl_filter_lp2_set
int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
Accelerometer output from LPF2 filtering stage selection.
Definition ism330dhcx_reg.c:2655
ism330dhcx_pp_od_t
ism330dhcx_pp_od_t
Definition ism330dhcx_reg.h:3426
ism330dhcx_aux_den_mode_get
int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx, ism330dhcx_lvl2_ois_t *val)
Configure DEN mode on the OIS chain.
Definition ism330dhcx_reg.c:3638
ism330dhcx_mag_z_axis_t
ism330dhcx_mag_z_axis_t
Definition ism330dhcx_reg.h:3910
ism330dhcx_fsm_start_address_set
int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
FSM start address register (r/w).
Definition ism330dhcx_reg.c:10209
ism330dhcx_sh_cfg_write
int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_write_t *val)
Configure slave 0 for perform a write.
Definition ism330dhcx_reg.c:11123
ism330dhcx_compression_algo_set
int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t val)
Enable and configure compression algo.
Definition ism330dhcx_reg.c:6680
ism330dhcx_gy_power_mode_set
int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx, ism330dhcx_g_hm_mode_t val)
Operating mode for gyroscope.
Definition ism330dhcx_reg.c:1142
ism330dhcx_fsm_data_rate_set
int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx, ism330dhcx_fsm_odr_t val)
Finite State Machine ODR configuration.
Definition ism330dhcx_reg.c:9947
ism330dhcx_pin_int1_route_set
int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx, ism330dhcx_pin_int1_route_t *val)
Select the signal that need to route on int1 pad[set].
Definition ism330dhcx_reg.c:4568
ism330dhcx_xl_usr_offset_y_get
int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
Accelerometer Y-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_...
Definition ism330dhcx_reg.c:1410
ism330dhcx_tap_shock_get
int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap e...
Definition ism330dhcx_reg.c:6065
ism330dhcx_sh_reset_get
int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
Reset Master logic and output registers.
Definition ism330dhcx_reg.c:11003
ism330dhcx_fsm_enable_get
int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx, ism330dhcx_emb_fsm_enable_t *val)
Embedded final state machine functions mode.
Definition ism330dhcx_reg.c:9738
ism330dhcx_den_mark_axis_x_set
int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
DEN value stored in LSB of X-axis.
Definition ism330dhcx_reg.c:8288
ism330dhcx_acceleration_raw_get
int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
Linear acceleration output register.
Definition ism330dhcx_reg.c:1730
ism330dhcx_fifo_virtual_sens_odr_chg_get
int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, uint8_t *val)
Enables ODR CHANGE virtual sensor to be batched in FIFO.
Definition ism330dhcx_reg.c:6808
ism330dhcx_aux_pw_on_ctrl_get
int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, ism330dhcx_ois_on_t *val)
OIS chain on aux interface power on mode[get].
Definition ism330dhcx_reg.c:3360
ism330dhcx_sh_batch_slave_0_get
int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable FIFO batching data of first slave.
Definition ism330dhcx_reg.c:7845
ism330dhcx_h_lactive_t
ism330dhcx_h_lactive_t
Definition ism330dhcx_reg.h:3436
ism330dhcx_fifo_timestamp_decimation_get
int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, ism330dhcx_odr_ts_batch_t *val)
Selects decimation for timestamp batching in FIFO.
Definition ism330dhcx_reg.c:7303
ism330dhcx_fs_xl_t
ism330dhcx_fs_xl_t
Definition ism330dhcx_reg.h:2849
ism330dhcx_fsm_init_set
int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
FSM initialization request.
Definition ism330dhcx_reg.c:10037
ism330dhcx_tap_quiet_set
int32_t ism330dhcx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
Quiet time is the time after the first detected tap in which there must not be any overthreshold even...
Definition ism330dhcx_reg.c:6088
ism330dhcx_from_lsb_to_nsec
float ism330dhcx_from_lsb_to_nsec(int32_t lsb)
Definition ism330dhcx_reg.c:146
ism330dhcx_mag_sensitivity_get
int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
External magnetometer sensitivity value register.
Definition ism330dhcx_reg.c:8935
ism330dhcx_i2c_interface_set
int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx, ism330dhcx_i2c_disable_t val)
Disable / Enable I2C interface.
Definition ism330dhcx_reg.c:4494
ism330dhcx_mem_bank_set
int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx, ism330dhcx_reg_access_t val)
Enable access to the embedded functions/sensor hub configuration registers.
Definition ism330dhcx_reg.c:1964
ism330dhcx_sh_pass_through_get
int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
I2C interface pass-through.
Definition ism330dhcx_reg.c:10770
ism330dhcx_st_xl_ois_t
ism330dhcx_st_xl_ois_t
Definition ism330dhcx_reg.h:3223
ism330dhcx_mlc_status_get
int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx, ism330dhcx_mlc_status_mainpage_t *val)
Machine Learning Core status register[get].
Definition ism330dhcx_reg.c:10360
ism330dhcx_write_reg
int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len)
Write generic device register.
Definition ism330dhcx_reg.c:69
ism330dhcx_st_g_t
ism330dhcx_st_g_t
Definition ism330dhcx_reg.h:3091
ism330dhcx_aux_gy_full_scale_set
int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, ism330dhcx_fs_g_ois_t val)
Selects gyroscope OIS chain full-scale.
Definition ism330dhcx_reg.c:3807
ism330dhcx_gy_hp_path_internal_set
int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, ism330dhcx_hpm_g_t val)
Enables gyroscope digital high-pass filter.
Definition ism330dhcx_reg.c:3184
ism330dhcx_spi_mode_set
int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, ism330dhcx_sim_t val)
SPI Serial Interface Mode selection.
Definition ism330dhcx_reg.c:4434
ism330dhcx_all_sources_get
int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx, ism330dhcx_all_sources_t *val)
Read all the interrupt flag of the device.
Definition ism330dhcx_reg.c:1204
ism330dhcx_ff_ths_t
ism330dhcx_ff_ths_t
Definition ism330dhcx_reg.h:3589
ism330dhcx_number_of_steps_get
int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
Step counter output register.
Definition ism330dhcx_reg.c:1770
ism330dhcx_sh_read_data_raw_get
int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx, ism330dhcx_emb_sh_read_t *val, uint8_t len)
Sensor hub output registers.
Definition ism330dhcx_reg.c:10476
ism330dhcx_sh_syncro_mode_set
int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx, ism330dhcx_start_config_t val)
Sensor hub trigger signal selection.
Definition ism330dhcx_reg.c:10800
ism330dhcx_device_conf_set
int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val)
DEVICE_CONF bit configuration[set].
Definition ism330dhcx_reg.c:1871
ism330dhcx_odr_cal_reg_get
int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical.
Definition ism330dhcx_reg.c:1944
ism330dhcx_den_polarity_get
int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx, ism330dhcx_den_lh_t *val)
DEN active level configuration.
Definition ism330dhcx_reg.c:8190
ism330dhcx_xl_usr_offset_get
int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
Get user offset on out flag.
Definition ism330dhcx_reg.c:1490
ism330dhcx_long_cnt_get
int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
FSM long counter status register.
Definition ism330dhcx_reg.c:9804
ism330dhcx_fsm_lc_clr_t
ism330dhcx_fsm_lc_clr_t
Definition ism330dhcx_reg.h:3971
ism330dhcx_long_cnt_int_value_set
int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
FSM long counter timeout register (r/w).
Definition ism330dhcx_reg.c:10104
ism330dhcx_st_xl_t
ism330dhcx_st_xl_t
Definition ism330dhcx_reg.h:3080
ism330dhcx_sh_batch_slave_3_set
int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
Enable FIFO batching data of fourth slave.
Definition ism330dhcx_reg.c:8012
ism330dhcx_aux_gy_hp_bandwidth_set
int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, ism330dhcx_hpm_ois_t val)
Selects gyroscope OIS chain digital high-pass filter cutoff.
Definition ism330dhcx_reg.c:4008
ism330dhcx_long_clr_set
int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx, ism330dhcx_fsm_lc_clr_t val)
Clear FSM long counter value.
Definition ism330dhcx_reg.c:9835
ism330dhcx_den_mode_t
ism330dhcx_den_mode_t
Definition ism330dhcx_reg.h:3810
ism330dhcx_aux_xl_full_scale_set
int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, ism330dhcx_fs_xl_ois_t val)
Selects accelerometer OIS channel full-scale.
Definition ism330dhcx_reg.c:4293
ism330dhcx_i2c_interface_get
int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx, ism330dhcx_i2c_disable_t *val)
Disable / Enable I2C interface.
Definition ism330dhcx_reg.c:4520
ism330dhcx_act_sleep_dur_set
int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
Duration to go in sleep mode (1 LSb = 512 / ODR).
Definition ism330dhcx_reg.c:5626
ism330dhcx_ln_pg_write
int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
Write buffer in a page.
Definition ism330dhcx_reg.c:2109
ism330dhcx_fs_g_ois_t
ism330dhcx_fs_g_ois_t
Definition ism330dhcx_reg.h:3271
ism330dhcx_pedo_sens_get
int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
Enable pedometer algorithm.
Definition ism330dhcx_reg.c:8470
ISM330DHCX_DRIVE_SLEEP_CHG_EVENT
@ ISM330DHCX_DRIVE_SLEEP_CHG_EVENT
Definition ism330dhcx_reg.h:3487
ISM330DHCX_DRIVE_SLEEP_STATUS
@ ISM330DHCX_DRIVE_SLEEP_STATUS
Definition ism330dhcx_reg.h:3488
ISM330DHCX_COUNT_OVERFLOW
@ ISM330DHCX_COUNT_OVERFLOW
Definition ism330dhcx_reg.h:3877
ISM330DHCX_EVERY_STEP
@ ISM330DHCX_EVERY_STEP
Definition ism330dhcx_reg.h:3876
ISM330DHCX_DEN_ACT_HIGH
@ ISM330DHCX_DEN_ACT_HIGH
Definition ism330dhcx_reg.h:3825
ISM330DHCX_DEN_ACT_LOW
@ ISM330DHCX_DEN_ACT_LOW
Definition ism330dhcx_reg.h:3824
ISM330DHCX_AUX_DEN_ACTIVE_HIGH
@ ISM330DHCX_AUX_DEN_ACTIVE_HIGH
Definition ism330dhcx_reg.h:3236
ISM330DHCX_AUX_DEN_ACTIVE_LOW
@ ISM330DHCX_AUX_DEN_ACTIVE_LOW
Definition ism330dhcx_reg.h:3235
ISM330DHCX_AUX_ON_BY_AUX_INTERFACE
@ ISM330DHCX_AUX_ON_BY_AUX_INTERFACE
Definition ism330dhcx_reg.h:3203
ISM330DHCX_AUX_ON
@ ISM330DHCX_AUX_ON
Definition ism330dhcx_reg.h:3202
ISM330DHCX_AUX_SPI_3_WIRE
@ ISM330DHCX_AUX_SPI_3_WIRE
Definition ism330dhcx_reg.h:3286
ISM330DHCX_AUX_SPI_4_WIRE
@ ISM330DHCX_AUX_SPI_4_WIRE
Definition ism330dhcx_reg.h:3285
ISM330DHCX_GYRO_BATCH_EVENT
@ ISM330DHCX_GYRO_BATCH_EVENT
Definition ism330dhcx_reg.h:3726
ISM330DHCX_XL_BATCH_EVENT
@ ISM330DHCX_XL_BATCH_EVENT
Definition ism330dhcx_reg.h:3725
ISM330DHCX_LSb_FS_DIV_64
@ ISM330DHCX_LSb_FS_DIV_64
Definition ism330dhcx_reg.h:3462
ISM330DHCX_LSb_FS_DIV_256
@ ISM330DHCX_LSb_FS_DIV_256
Definition ism330dhcx_reg.h:3463
ISM330DHCX_GY_BATCHED_AT_208Hz
@ ISM330DHCX_GY_BATCHED_AT_208Hz
Definition ism330dhcx_reg.h:3672
ISM330DHCX_GY_NOT_BATCHED
@ ISM330DHCX_GY_NOT_BATCHED
Definition ism330dhcx_reg.h:3667
ISM330DHCX_GY_BATCHED_6Hz5
@ ISM330DHCX_GY_BATCHED_6Hz5
Definition ism330dhcx_reg.h:3678
ISM330DHCX_GY_BATCHED_AT_104Hz
@ ISM330DHCX_GY_BATCHED_AT_104Hz
Definition ism330dhcx_reg.h:3671
ISM330DHCX_GY_BATCHED_AT_12Hz5
@ ISM330DHCX_GY_BATCHED_AT_12Hz5
Definition ism330dhcx_reg.h:3668
ISM330DHCX_GY_BATCHED_AT_6667Hz
@ ISM330DHCX_GY_BATCHED_AT_6667Hz
Definition ism330dhcx_reg.h:3677
ISM330DHCX_GY_BATCHED_AT_3333Hz
@ ISM330DHCX_GY_BATCHED_AT_3333Hz
Definition ism330dhcx_reg.h:3676
ISM330DHCX_GY_BATCHED_AT_52Hz
@ ISM330DHCX_GY_BATCHED_AT_52Hz
Definition ism330dhcx_reg.h:3670
ISM330DHCX_GY_BATCHED_AT_833Hz
@ ISM330DHCX_GY_BATCHED_AT_833Hz
Definition ism330dhcx_reg.h:3674
ISM330DHCX_GY_BATCHED_AT_26Hz
@ ISM330DHCX_GY_BATCHED_AT_26Hz
Definition ism330dhcx_reg.h:3669
ISM330DHCX_GY_BATCHED_AT_417Hz
@ ISM330DHCX_GY_BATCHED_AT_417Hz
Definition ism330dhcx_reg.h:3673
ISM330DHCX_GY_BATCHED_AT_1667Hz
@ ISM330DHCX_GY_BATCHED_AT_1667Hz
Definition ism330dhcx_reg.h:3675
ISM330DHCX_SLV_0_1_2
@ ISM330DHCX_SLV_0_1_2
Definition ism330dhcx_reg.h:4080
ISM330DHCX_SLV_0_1
@ ISM330DHCX_SLV_0_1
Definition ism330dhcx_reg.h:4079
ISM330DHCX_SLV_0
@ ISM330DHCX_SLV_0
Definition ism330dhcx_reg.h:4078
ISM330DHCX_SLV_0_1_2_3
@ ISM330DHCX_SLV_0_1_2_3
Definition ism330dhcx_reg.h:4081
ISM330DHCX_500dps
@ ISM330DHCX_500dps
Definition ism330dhcx_reg.h:2884
ISM330DHCX_2000dps
@ ISM330DHCX_2000dps
Definition ism330dhcx_reg.h:2886
ISM330DHCX_1000dps
@ ISM330DHCX_1000dps
Definition ism330dhcx_reg.h:2885
ISM330DHCX_250dps
@ ISM330DHCX_250dps
Definition ism330dhcx_reg.h:2883
ISM330DHCX_4000dps
@ ISM330DHCX_4000dps
Definition ism330dhcx_reg.h:2887
ISM330DHCX_125dps
@ ISM330DHCX_125dps
Definition ism330dhcx_reg.h:2882
ISM330DHCX_AUX_DEN_LEVEL_TRIG
@ ISM330DHCX_AUX_DEN_LEVEL_TRIG
Definition ism330dhcx_reg.h:3247
ISM330DHCX_AUX_DEN_LEVEL_LATCH
@ ISM330DHCX_AUX_DEN_LEVEL_LATCH
Definition ism330dhcx_reg.h:3246
ISM330DHCX_AUX_DEN_DISABLE
@ ISM330DHCX_AUX_DEN_DISABLE
Definition ism330dhcx_reg.h:3245
ISM330DHCX_STEP_CPUNTER_TAG
@ ISM330DHCX_STEP_CPUNTER_TAG
Definition ism330dhcx_reg.h:3775
ISM330DHCX_GEOMAG_ROTATION_TAG
@ ISM330DHCX_GEOMAG_ROTATION_TAG
Definition ism330dhcx_reg.h:3777
ISM330DHCX_SENSORHUB_SLAVE1_TAG
@ ISM330DHCX_SENSORHUB_SLAVE1_TAG
Definition ism330dhcx_reg.h:3772
ISM330DHCX_GYRO_3XC_TAG
@ ISM330DHCX_GYRO_3XC_TAG
Definition ism330dhcx_reg.h:3770
ISM330DHCX_TEMPERATURE_TAG
@ ISM330DHCX_TEMPERATURE_TAG
Definition ism330dhcx_reg.h:3760
ISM330DHCX_XL_NC_T_2_TAG
@ ISM330DHCX_XL_NC_T_2_TAG
Definition ism330dhcx_reg.h:3763
ISM330DHCX_CFG_CHANGE_TAG
@ ISM330DHCX_CFG_CHANGE_TAG
Definition ism330dhcx_reg.h:3762
ISM330DHCX_XL_NC_TAG
@ ISM330DHCX_XL_NC_TAG
Definition ism330dhcx_reg.h:3759
ISM330DHCX_SENSORHUB_SLAVE0_TAG
@ ISM330DHCX_SENSORHUB_SLAVE0_TAG
Definition ism330dhcx_reg.h:3771
ISM330DHCX_ROTATION_TAG
@ ISM330DHCX_ROTATION_TAG
Definition ism330dhcx_reg.h:3778
ISM330DHCX_GYRO_NC_T_2_TAG
@ ISM330DHCX_GYRO_NC_T_2_TAG
Definition ism330dhcx_reg.h:3767
ISM330DHCX_XL_NC_T_1_TAG
@ ISM330DHCX_XL_NC_T_1_TAG
Definition ism330dhcx_reg.h:3764
ISM330DHCX_XL_3XC_TAG
@ ISM330DHCX_XL_3XC_TAG
Definition ism330dhcx_reg.h:3766
ISM330DHCX_SENSORHUB_SLAVE2_TAG
@ ISM330DHCX_SENSORHUB_SLAVE2_TAG
Definition ism330dhcx_reg.h:3773
ISM330DHCX_GYRO_NC_TAG
@ ISM330DHCX_GYRO_NC_TAG
Definition ism330dhcx_reg.h:3758
ISM330DHCX_GAME_ROTATION_TAG
@ ISM330DHCX_GAME_ROTATION_TAG
Definition ism330dhcx_reg.h:3776
ISM330DHCX_TIMESTAMP_TAG
@ ISM330DHCX_TIMESTAMP_TAG
Definition ism330dhcx_reg.h:3761
ISM330DHCX_GYRO_2XC_TAG
@ ISM330DHCX_GYRO_2XC_TAG
Definition ism330dhcx_reg.h:3769
ISM330DHCX_SENSORHUB_SLAVE3_TAG
@ ISM330DHCX_SENSORHUB_SLAVE3_TAG
Definition ism330dhcx_reg.h:3774
ISM330DHCX_GYRO_NC_T_1_TAG
@ ISM330DHCX_GYRO_NC_T_1_TAG
Definition ism330dhcx_reg.h:3768
ISM330DHCX_XL_2XC_TAG
@ ISM330DHCX_XL_2XC_TAG
Definition ism330dhcx_reg.h:3765
ISM330DHCX_SENSORHUB_NACK_TAG
@ ISM330DHCX_SENSORHUB_NACK_TAG
Definition ism330dhcx_reg.h:3779
ISM330DHCX_GY_ODR_104Hz
@ ISM330DHCX_GY_ODR_104Hz
Definition ism330dhcx_reg.h:2900
ISM330DHCX_GY_ODR_3332Hz
@ ISM330DHCX_GY_ODR_3332Hz
Definition ism330dhcx_reg.h:2905
ISM330DHCX_GY_ODR_416Hz
@ ISM330DHCX_GY_ODR_416Hz
Definition ism330dhcx_reg.h:2902
ISM330DHCX_GY_ODR_OFF
@ ISM330DHCX_GY_ODR_OFF
Definition ism330dhcx_reg.h:2896
ISM330DHCX_GY_ODR_1666Hz
@ ISM330DHCX_GY_ODR_1666Hz
Definition ism330dhcx_reg.h:2904
ISM330DHCX_GY_ODR_6667Hz
@ ISM330DHCX_GY_ODR_6667Hz
Definition ism330dhcx_reg.h:2906
ISM330DHCX_GY_ODR_833Hz
@ ISM330DHCX_GY_ODR_833Hz
Definition ism330dhcx_reg.h:2903
ISM330DHCX_GY_ODR_208Hz
@ ISM330DHCX_GY_ODR_208Hz
Definition ism330dhcx_reg.h:2901
ISM330DHCX_GY_ODR_52Hz
@ ISM330DHCX_GY_ODR_52Hz
Definition ism330dhcx_reg.h:2899
ISM330DHCX_GY_ODR_26Hz
@ ISM330DHCX_GY_ODR_26Hz
Definition ism330dhcx_reg.h:2898
ISM330DHCX_GY_ODR_12Hz5
@ ISM330DHCX_GY_ODR_12Hz5
Definition ism330dhcx_reg.h:2897
ISM330DHCX_ONLY_SINGLE
@ ISM330DHCX_ONLY_SINGLE
Definition ism330dhcx_reg.h:3565
ISM330DHCX_BOTH_SINGLE_DOUBLE
@ ISM330DHCX_BOTH_SINGLE_DOUBLE
Definition ism330dhcx_reg.h:3566
ISM330DHCX_XL_AND_GY_NOT_AFFECTED
@ ISM330DHCX_XL_AND_GY_NOT_AFFECTED
Definition ism330dhcx_reg.h:3497
ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED
@ ISM330DHCX_XL_12Hz5_GY_NOT_AFFECTED
Definition ism330dhcx_reg.h:3498
ISM330DHCX_XL_12Hz5_GY_SLEEP
@ ISM330DHCX_XL_12Hz5_GY_SLEEP
Definition ism330dhcx_reg.h:3499
ISM330DHCX_XL_12Hz5_GY_PD
@ ISM330DHCX_XL_12Hz5_GY_PD
Definition ism330dhcx_reg.h:3500
ISM330DHCX_CMP_DISABLE
@ ISM330DHCX_CMP_DISABLE
Definition ism330dhcx_reg.h:3619
ISM330DHCX_CMP_8_TO_1
@ ISM330DHCX_CMP_8_TO_1
Definition ism330dhcx_reg.h:3621
ISM330DHCX_CMP_16_TO_1
@ ISM330DHCX_CMP_16_TO_1
Definition ism330dhcx_reg.h:3622
ISM330DHCX_CMP_32_TO_1
@ ISM330DHCX_CMP_32_TO_1
Definition ism330dhcx_reg.h:3623
ISM330DHCX_CMP_ALWAYS
@ ISM330DHCX_CMP_ALWAYS
Definition ism330dhcx_reg.h:3620
ISM330DHCX_STAMP_IN_XL_DATA
@ ISM330DHCX_STAMP_IN_XL_DATA
Definition ism330dhcx_reg.h:3835
ISM330DHCX_STAMP_IN_GY_DATA
@ ISM330DHCX_STAMP_IN_GY_DATA
Definition ism330dhcx_reg.h:3834
ISM330DHCX_STAMP_IN_GY_XL_DATA
@ ISM330DHCX_STAMP_IN_GY_XL_DATA
Definition ism330dhcx_reg.h:3836
ISM330DHCX_STRONG
@ ISM330DHCX_STRONG
Definition ism330dhcx_reg.h:3118
ISM330DHCX_LIGHT
@ ISM330DHCX_LIGHT
Definition ism330dhcx_reg.h:3116
ISM330DHCX_AGGRESSIVE
@ ISM330DHCX_AGGRESSIVE
Definition ism330dhcx_reg.h:3120
ISM330DHCX_VERY_LIGHT
@ ISM330DHCX_VERY_LIGHT
Definition ism330dhcx_reg.h:3115
ISM330DHCX_MEDIUM
@ ISM330DHCX_MEDIUM
Definition ism330dhcx_reg.h:3117
ISM330DHCX_ULTRA_LIGHT
@ ISM330DHCX_ULTRA_LIGHT
Definition ism330dhcx_reg.h:3114
ISM330DHCX_XTREME
@ ISM330DHCX_XTREME
Definition ism330dhcx_reg.h:3121
ISM330DHCX_VERY_STRONG
@ ISM330DHCX_VERY_STRONG
Definition ism330dhcx_reg.h:3119
ISM330DHCX_HP_REF_MD_ODR_DIV_20
@ ISM330DHCX_HP_REF_MD_ODR_DIV_20
Definition ism330dhcx_reg.h:3143
ISM330DHCX_HP_REF_MD_ODR_DIV_200
@ ISM330DHCX_HP_REF_MD_ODR_DIV_200
Definition ism330dhcx_reg.h:3146
ISM330DHCX_SLOPE_ODR_DIV_4
@ ISM330DHCX_SLOPE_ODR_DIV_4
Definition ism330dhcx_reg.h:3134
ISM330DHCX_HP_ODR_DIV_45
@ ISM330DHCX_HP_ODR_DIV_45
Definition ism330dhcx_reg.h:3137
ISM330DHCX_LP_ODR_DIV_200
@ ISM330DHCX_LP_ODR_DIV_200
Definition ism330dhcx_reg.h:3153
ISM330DHCX_LP_ODR_DIV_45
@ ISM330DHCX_LP_ODR_DIV_45
Definition ism330dhcx_reg.h:3151
ISM330DHCX_HP_PATH_DISABLE_ON_OUT
@ ISM330DHCX_HP_PATH_DISABLE_ON_OUT
Definition ism330dhcx_reg.h:3133
ISM330DHCX_HP_REF_MD_ODR_DIV_800
@ ISM330DHCX_HP_REF_MD_ODR_DIV_800
Definition ism330dhcx_reg.h:3148
ISM330DHCX_HP_REF_MD_ODR_DIV_100
@ ISM330DHCX_HP_REF_MD_ODR_DIV_100
Definition ism330dhcx_reg.h:3145
ISM330DHCX_HP_ODR_DIV_10
@ ISM330DHCX_HP_ODR_DIV_10
Definition ism330dhcx_reg.h:3135
ISM330DHCX_HP_REF_MD_ODR_DIV_10
@ ISM330DHCX_HP_REF_MD_ODR_DIV_10
Definition ism330dhcx_reg.h:3142
ISM330DHCX_HP_REF_MD_ODR_DIV_400
@ ISM330DHCX_HP_REF_MD_ODR_DIV_400
Definition ism330dhcx_reg.h:3147
ISM330DHCX_HP_ODR_DIV_20
@ ISM330DHCX_HP_ODR_DIV_20
Definition ism330dhcx_reg.h:3136
ISM330DHCX_LP_ODR_DIV_400
@ ISM330DHCX_LP_ODR_DIV_400
Definition ism330dhcx_reg.h:3154
ISM330DHCX_HP_REF_MD_ODR_DIV_45
@ ISM330DHCX_HP_REF_MD_ODR_DIV_45
Definition ism330dhcx_reg.h:3144
ISM330DHCX_LP_ODR_DIV_10
@ ISM330DHCX_LP_ODR_DIV_10
Definition ism330dhcx_reg.h:3149
ISM330DHCX_LP_ODR_DIV_20
@ ISM330DHCX_LP_ODR_DIV_20
Definition ism330dhcx_reg.h:3150
ISM330DHCX_HP_ODR_DIV_100
@ ISM330DHCX_HP_ODR_DIV_100
Definition ism330dhcx_reg.h:3138
ISM330DHCX_HP_ODR_DIV_800
@ ISM330DHCX_HP_ODR_DIV_800
Definition ism330dhcx_reg.h:3141
ISM330DHCX_HP_ODR_DIV_400
@ ISM330DHCX_HP_ODR_DIV_400
Definition ism330dhcx_reg.h:3140
ISM330DHCX_LP_ODR_DIV_800
@ ISM330DHCX_LP_ODR_DIV_800
Definition ism330dhcx_reg.h:3155
ISM330DHCX_LP_ODR_DIV_100
@ ISM330DHCX_LP_ODR_DIV_100
Definition ism330dhcx_reg.h:3152
ISM330DHCX_HP_ODR_DIV_200
@ ISM330DHCX_HP_ODR_DIV_200
Definition ism330dhcx_reg.h:3139
ISM330DHCX_DRDY_LATCHED
@ ISM330DHCX_DRDY_LATCHED
Definition ism330dhcx_reg.h:3059
ISM330DHCX_DRDY_PULSED
@ ISM330DHCX_DRDY_PULSED
Definition ism330dhcx_reg.h:3060
ISM330DHCX_LSb_1mg
@ ISM330DHCX_LSb_1mg
Definition ism330dhcx_reg.h:2920
ISM330DHCX_LSb_16mg
@ ISM330DHCX_LSb_16mg
Definition ism330dhcx_reg.h:2921
ISM330DHCX_EXT_ON_INT2_PIN
@ ISM330DHCX_EXT_ON_INT2_PIN
Definition ism330dhcx_reg.h:4108
ISM330DHCX_XL_GY_DRDY
@ ISM330DHCX_XL_GY_DRDY
Definition ism330dhcx_reg.h:4109
ISM330DHCX_4Hz11
@ ISM330DHCX_4Hz11
Definition ism330dhcx_reg.h:3348
ISM330DHCX_68Hz2
@ ISM330DHCX_68Hz2
Definition ism330dhcx_reg.h:3344
ISM330DHCX_33Hz6
@ ISM330DHCX_33Hz6
Definition ism330dhcx_reg.h:3345
ISM330DHCX_631Hz
@ ISM330DHCX_631Hz
Definition ism330dhcx_reg.h:3341
ISM330DHCX_140Hz
@ ISM330DHCX_140Hz
Definition ism330dhcx_reg.h:3343
ISM330DHCX_295Hz
@ ISM330DHCX_295Hz
Definition ism330dhcx_reg.h:3342
ISM330DHCX_16Hz7
@ ISM330DHCX_16Hz7
Definition ism330dhcx_reg.h:3346
ISM330DHCX_8Hz3
@ ISM330DHCX_8Hz3
Definition ism330dhcx_reg.h:3347
ISM330DHCX_HIGH_PERFORMANCE_MD
@ ISM330DHCX_HIGH_PERFORMANCE_MD
Definition ism330dhcx_reg.h:2930
ISM330DHCX_LOW_NORMAL_POWER_MD
@ ISM330DHCX_LOW_NORMAL_POWER_MD
Definition ism330dhcx_reg.h:2931
ISM330DHCX_ODR_PRGS_12Hz5
@ ISM330DHCX_ODR_PRGS_12Hz5
Definition ism330dhcx_reg.h:4041
ISM330DHCX_ODR_PRGS_52Hz
@ ISM330DHCX_ODR_PRGS_52Hz
Definition ism330dhcx_reg.h:4043
ISM330DHCX_ODR_PRGS_26Hz
@ ISM330DHCX_ODR_PRGS_26Hz
Definition ism330dhcx_reg.h:4042
ISM330DHCX_ODR_PRGS_104Hz
@ ISM330DHCX_ODR_PRGS_104Hz
Definition ism330dhcx_reg.h:4044
ISM330DHCX_FIFO_MODE
@ ISM330DHCX_FIFO_MODE
Definition ism330dhcx_reg.h:3688
ISM330DHCX_BYPASS_TO_FIFO_MODE
@ ISM330DHCX_BYPASS_TO_FIFO_MODE
Definition ism330dhcx_reg.h:3692
ISM330DHCX_BYPASS_MODE
@ ISM330DHCX_BYPASS_MODE
Definition ism330dhcx_reg.h:3687
ISM330DHCX_STREAM_MODE
@ ISM330DHCX_STREAM_MODE
Definition ism330dhcx_reg.h:3691
ISM330DHCX_BYPASS_TO_STREAM_MODE
@ ISM330DHCX_BYPASS_TO_STREAM_MODE
Definition ism330dhcx_reg.h:3690
ISM330DHCX_STREAM_TO_FIFO_MODE
@ ISM330DHCX_STREAM_TO_FIFO_MODE
Definition ism330dhcx_reg.h:3689
ISM330DHCX_ALL_INT_LATCHED
@ ISM330DHCX_ALL_INT_LATCHED
Definition ism330dhcx_reg.h:3453
ISM330DHCX_BASE_PULSED_EMB_LATCHED
@ ISM330DHCX_BASE_PULSED_EMB_LATCHED
Definition ism330dhcx_reg.h:3452
ISM330DHCX_ALL_INT_PULSED
@ ISM330DHCX_ALL_INT_PULSED
Definition ism330dhcx_reg.h:3450
ISM330DHCX_BASE_LATCHED_EMB_PULSED
@ ISM330DHCX_BASE_LATCHED_EMB_PULSED
Definition ism330dhcx_reg.h:3451
ISM330DHCX_AUX_4g
@ ISM330DHCX_AUX_4g
Definition ism330dhcx_reg.h:3359
ISM330DHCX_AUX_2g
@ ISM330DHCX_AUX_2g
Definition ism330dhcx_reg.h:3357
ISM330DHCX_AUX_16g
@ ISM330DHCX_AUX_16g
Definition ism330dhcx_reg.h:3358
ISM330DHCX_AUX_8g
@ ISM330DHCX_AUX_8g
Definition ism330dhcx_reg.h:3360
ISM330DHCX_HP_FILTER_16mHz
@ ISM330DHCX_HP_FILTER_16mHz
Definition ism330dhcx_reg.h:3180
ISM330DHCX_HP_FILTER_260mHz
@ ISM330DHCX_HP_FILTER_260mHz
Definition ism330dhcx_reg.h:3182
ISM330DHCX_HP_FILTER_1Hz04
@ ISM330DHCX_HP_FILTER_1Hz04
Definition ism330dhcx_reg.h:3183
ISM330DHCX_HP_FILTER_NONE
@ ISM330DHCX_HP_FILTER_NONE
Definition ism330dhcx_reg.h:3179
ISM330DHCX_HP_FILTER_65mHz
@ ISM330DHCX_HP_FILTER_65mHz
Definition ism330dhcx_reg.h:3181
ISM330DHCX_GY_HIGH_PERFORMANCE
@ ISM330DHCX_GY_HIGH_PERFORMANCE
Definition ism330dhcx_reg.h:2940
ISM330DHCX_GY_NORMAL
@ ISM330DHCX_GY_NORMAL
Definition ism330dhcx_reg.h:2941
ISM330DHCX_TEMP_NOT_BATCHED
@ ISM330DHCX_TEMP_NOT_BATCHED
Definition ism330dhcx_reg.h:3701
ISM330DHCX_TEMP_BATCHED_AT_1Hz6
@ ISM330DHCX_TEMP_BATCHED_AT_1Hz6
Definition ism330dhcx_reg.h:3704
ISM330DHCX_TEMP_BATCHED_AT_52Hz
@ ISM330DHCX_TEMP_BATCHED_AT_52Hz
Definition ism330dhcx_reg.h:3702
ISM330DHCX_TEMP_BATCHED_AT_12Hz5
@ ISM330DHCX_TEMP_BATCHED_AT_12Hz5
Definition ism330dhcx_reg.h:3703
ISM330DHCX_DEG_80
@ ISM330DHCX_DEG_80
Definition ism330dhcx_reg.h:3575
ISM330DHCX_DEG_50
@ ISM330DHCX_DEG_50
Definition ism330dhcx_reg.h:3578
ISM330DHCX_DEG_70
@ ISM330DHCX_DEG_70
Definition ism330dhcx_reg.h:3576
ISM330DHCX_DEG_60
@ ISM330DHCX_DEG_60
Definition ism330dhcx_reg.h:3577
ISM330DHCX_MODE_4_GY_XL
@ ISM330DHCX_MODE_4_GY_XL
Definition ism330dhcx_reg.h:3263
ISM330DHCX_AUX_DISABLE
@ ISM330DHCX_AUX_DISABLE
Definition ism330dhcx_reg.h:3261
ISM330DHCX_MODE_3_GY
@ ISM330DHCX_MODE_3_GY
Definition ism330dhcx_reg.h:3262
ISM330DHCX_AUX_HP_Hz065
@ ISM330DHCX_AUX_HP_Hz065
Definition ism330dhcx_reg.h:3309
ISM330DHCX_AUX_HP_Hz260
@ ISM330DHCX_AUX_HP_Hz260
Definition ism330dhcx_reg.h:3310
ISM330DHCX_AUX_HP_Hz016
@ ISM330DHCX_AUX_HP_Hz016
Definition ism330dhcx_reg.h:3308
ISM330DHCX_AUX_HP_DISABLE
@ ISM330DHCX_AUX_HP_DISABLE
Definition ism330dhcx_reg.h:3307
ISM330DHCX_AUX_HP_1Hz040
@ ISM330DHCX_AUX_HP_1Hz040
Definition ism330dhcx_reg.h:3311
ISM330DHCX_SH_ODR_52Hz
@ ISM330DHCX_SH_ODR_52Hz
Definition ism330dhcx_reg.h:4132
ISM330DHCX_SH_ODR_13Hz
@ ISM330DHCX_SH_ODR_13Hz
Definition ism330dhcx_reg.h:4134
ISM330DHCX_SH_ODR_26Hz
@ ISM330DHCX_SH_ODR_26Hz
Definition ism330dhcx_reg.h:4133
ISM330DHCX_SH_ODR_104Hz
@ ISM330DHCX_SH_ODR_104Hz
Definition ism330dhcx_reg.h:4131
ISM330DHCX_ONLY_FIRST_CYCLE
@ ISM330DHCX_ONLY_FIRST_CYCLE
Definition ism330dhcx_reg.h:4119
ISM330DHCX_EACH_SH_CYCLE
@ ISM330DHCX_EACH_SH_CYCLE
Definition ism330dhcx_reg.h:4118
ISM330DHCX_AUX_GY_DISABLE
@ ISM330DHCX_AUX_GY_DISABLE
Definition ism330dhcx_reg.h:3330
ISM330DHCX_AUX_GY_NEG
@ ISM330DHCX_AUX_GY_NEG
Definition ism330dhcx_reg.h:3332
ISM330DHCX_AUX_GY_POS
@ ISM330DHCX_AUX_GY_POS
Definition ism330dhcx_reg.h:3331
ISM330DHCX_ODR_FSM_52Hz
@ ISM330DHCX_ODR_FSM_52Hz
Definition ism330dhcx_reg.h:4007
ISM330DHCX_ODR_FSM_104Hz
@ ISM330DHCX_ODR_FSM_104Hz
Definition ism330dhcx_reg.h:4008
ISM330DHCX_ODR_FSM_12Hz5
@ ISM330DHCX_ODR_FSM_12Hz5
Definition ism330dhcx_reg.h:4005
ISM330DHCX_ODR_FSM_26Hz
@ ISM330DHCX_ODR_FSM_26Hz
Definition ism330dhcx_reg.h:4006
ISM330DHCX_ZYX
@ ISM330DHCX_ZYX
Definition ism330dhcx_reg.h:3535
ISM330DHCX_ZXY
@ ISM330DHCX_ZXY
Definition ism330dhcx_reg.h:3537
ISM330DHCX_XZY
@ ISM330DHCX_XZY
Definition ism330dhcx_reg.h:3534
ISM330DHCX_YXZ
@ ISM330DHCX_YXZ
Definition ism330dhcx_reg.h:3533
ISM330DHCX_YZX
@ ISM330DHCX_YZX
Definition ism330dhcx_reg.h:3536
ISM330DHCX_XYZ
@ ISM330DHCX_XYZ
Definition ism330dhcx_reg.h:3532
ISM330DHCX_USER_BANK
@ ISM330DHCX_USER_BANK
Definition ism330dhcx_reg.h:3038
ISM330DHCX_SENSOR_HUB_BANK
@ ISM330DHCX_SENSOR_HUB_BANK
Definition ism330dhcx_reg.h:3039
ISM330DHCX_EMBEDDED_FUNC_BANK
@ ISM330DHCX_EMBEDDED_FUNC_BANK
Definition ism330dhcx_reg.h:3040
ISM330DHCX_INTERNAL_PULL_UP
@ ISM330DHCX_INTERNAL_PULL_UP
Definition ism330dhcx_reg.h:4094
ISM330DHCX_EXT_PULL_UP
@ ISM330DHCX_EXT_PULL_UP
Definition ism330dhcx_reg.h:4093
ISM330DHCX_X_EQ_MIN_X
@ ISM330DHCX_X_EQ_MIN_X
Definition ism330dhcx_reg.h:3942
ISM330DHCX_X_EQ_Y
@ ISM330DHCX_X_EQ_Y
Definition ism330dhcx_reg.h:3939
ISM330DHCX_X_EQ_Z
@ ISM330DHCX_X_EQ_Z
Definition ism330dhcx_reg.h:3944
ISM330DHCX_X_EQ_X
@ ISM330DHCX_X_EQ_X
Definition ism330dhcx_reg.h:3941
ISM330DHCX_X_EQ_MIN_Y
@ ISM330DHCX_X_EQ_MIN_Y
Definition ism330dhcx_reg.h:3940
ISM330DHCX_X_EQ_MIN_Z
@ ISM330DHCX_X_EQ_MIN_Z
Definition ism330dhcx_reg.h:3943
ISM330DHCX_SPI_4_WIRE
@ ISM330DHCX_SPI_4_WIRE
Definition ism330dhcx_reg.h:3379
ISM330DHCX_SPI_3_WIRE
@ ISM330DHCX_SPI_3_WIRE
Definition ism330dhcx_reg.h:3380
ISM330DHCX_I2C_DISABLE
@ ISM330DHCX_I2C_DISABLE
Definition ism330dhcx_reg.h:3390
ISM330DHCX_I2C_ENABLE
@ ISM330DHCX_I2C_ENABLE
Definition ism330dhcx_reg.h:3389
ISM330DHCX_PULL_UP_DISC
@ ISM330DHCX_PULL_UP_DISC
Definition ism330dhcx_reg.h:3369
ISM330DHCX_PULL_UP_CONNECT
@ ISM330DHCX_PULL_UP_CONNECT
Definition ism330dhcx_reg.h:3370
ISM330DHCX_AUX_PULL_UP_DISC
@ ISM330DHCX_AUX_PULL_UP_DISC
Definition ism330dhcx_reg.h:3192
ISM330DHCX_AUX_PULL_UP_CONNECT
@ ISM330DHCX_AUX_PULL_UP_CONNECT
Definition ism330dhcx_reg.h:3193
ISM330DHCX_USE_HPF
@ ISM330DHCX_USE_HPF
Definition ism330dhcx_reg.h:3170
ISM330DHCX_USE_SLOPE
@ ISM330DHCX_USE_SLOPE
Definition ism330dhcx_reg.h:3169
ISM330DHCX_XL_BATCHED_AT_26Hz
@ ISM330DHCX_XL_BATCHED_AT_26Hz
Definition ism330dhcx_reg.h:3649
ISM330DHCX_XL_BATCHED_AT_3333Hz
@ ISM330DHCX_XL_BATCHED_AT_3333Hz
Definition ism330dhcx_reg.h:3656
ISM330DHCX_XL_BATCHED_AT_6Hz5
@ ISM330DHCX_XL_BATCHED_AT_6Hz5
Definition ism330dhcx_reg.h:3658
ISM330DHCX_XL_BATCHED_AT_833Hz
@ ISM330DHCX_XL_BATCHED_AT_833Hz
Definition ism330dhcx_reg.h:3654
ISM330DHCX_XL_BATCHED_AT_417Hz
@ ISM330DHCX_XL_BATCHED_AT_417Hz
Definition ism330dhcx_reg.h:3653
ISM330DHCX_XL_BATCHED_AT_1667Hz
@ ISM330DHCX_XL_BATCHED_AT_1667Hz
Definition ism330dhcx_reg.h:3655
ISM330DHCX_XL_BATCHED_AT_104Hz
@ ISM330DHCX_XL_BATCHED_AT_104Hz
Definition ism330dhcx_reg.h:3651
ISM330DHCX_XL_NOT_BATCHED
@ ISM330DHCX_XL_NOT_BATCHED
Definition ism330dhcx_reg.h:3647
ISM330DHCX_XL_BATCHED_AT_6667Hz
@ ISM330DHCX_XL_BATCHED_AT_6667Hz
Definition ism330dhcx_reg.h:3657
ISM330DHCX_XL_BATCHED_AT_52Hz
@ ISM330DHCX_XL_BATCHED_AT_52Hz
Definition ism330dhcx_reg.h:3650
ISM330DHCX_XL_BATCHED_AT_12Hz5
@ ISM330DHCX_XL_BATCHED_AT_12Hz5
Definition ism330dhcx_reg.h:3648
ISM330DHCX_XL_BATCHED_AT_208Hz
@ ISM330DHCX_XL_BATCHED_AT_208Hz
Definition ism330dhcx_reg.h:3652
ISM330DHCX_172Hz70
@ ISM330DHCX_172Hz70
Definition ism330dhcx_reg.h:3297
ISM330DHCX_937Hz91
@ ISM330DHCX_937Hz91
Definition ism330dhcx_reg.h:3298
ISM330DHCX_351Hz39
@ ISM330DHCX_351Hz39
Definition ism330dhcx_reg.h:3295
ISM330DHCX_236Hz63
@ ISM330DHCX_236Hz63
Definition ism330dhcx_reg.h:3296
ISM330DHCX_XL_ODR_104Hz
@ ISM330DHCX_XL_ODR_104Hz
Definition ism330dhcx_reg.h:2866
ISM330DHCX_XL_ODR_1666Hz
@ ISM330DHCX_XL_ODR_1666Hz
Definition ism330dhcx_reg.h:2870
ISM330DHCX_XL_ODR_1Hz6
@ ISM330DHCX_XL_ODR_1Hz6
Definition ism330dhcx_reg.h:2873
ISM330DHCX_XL_ODR_208Hz
@ ISM330DHCX_XL_ODR_208Hz
Definition ism330dhcx_reg.h:2867
ISM330DHCX_XL_ODR_52Hz
@ ISM330DHCX_XL_ODR_52Hz
Definition ism330dhcx_reg.h:2865
ISM330DHCX_XL_ODR_833Hz
@ ISM330DHCX_XL_ODR_833Hz
Definition ism330dhcx_reg.h:2869
ISM330DHCX_XL_ODR_26Hz
@ ISM330DHCX_XL_ODR_26Hz
Definition ism330dhcx_reg.h:2864
ISM330DHCX_XL_ODR_6667Hz
@ ISM330DHCX_XL_ODR_6667Hz
Definition ism330dhcx_reg.h:2872
ISM330DHCX_XL_ODR_416Hz
@ ISM330DHCX_XL_ODR_416Hz
Definition ism330dhcx_reg.h:2868
ISM330DHCX_XL_ODR_3332Hz
@ ISM330DHCX_XL_ODR_3332Hz
Definition ism330dhcx_reg.h:2871
ISM330DHCX_XL_ODR_OFF
@ ISM330DHCX_XL_ODR_OFF
Definition ism330dhcx_reg.h:2862
ISM330DHCX_XL_ODR_12Hz5
@ ISM330DHCX_XL_ODR_12Hz5
Definition ism330dhcx_reg.h:2863
ISM330DHCX_ENABLE_CLAMP
@ ISM330DHCX_ENABLE_CLAMP
Definition ism330dhcx_reg.h:3320
ISM330DHCX_DISABLE_CLAMP
@ ISM330DHCX_DISABLE_CLAMP
Definition ism330dhcx_reg.h:3321
ISM330DHCX_DEC_1
@ ISM330DHCX_DEC_1
Definition ism330dhcx_reg.h:3714
ISM330DHCX_NO_DECIMATION
@ ISM330DHCX_NO_DECIMATION
Definition ism330dhcx_reg.h:3713
ISM330DHCX_DEC_32
@ ISM330DHCX_DEC_32
Definition ism330dhcx_reg.h:3716
ISM330DHCX_DEC_8
@ ISM330DHCX_DEC_8
Definition ism330dhcx_reg.h:3715
ISM330DHCX_ROUND_GY
@ ISM330DHCX_ROUND_GY
Definition ism330dhcx_reg.h:3004
ISM330DHCX_ROUND_XL
@ ISM330DHCX_ROUND_XL
Definition ism330dhcx_reg.h:3003
ISM330DHCX_NO_ROUND
@ ISM330DHCX_NO_ROUND
Definition ism330dhcx_reg.h:3002
ISM330DHCX_ROUND_GY_XL
@ ISM330DHCX_ROUND_GY_XL
Definition ism330dhcx_reg.h:3005
ISM330DHCX_Y_EQ_MIN_Z
@ ISM330DHCX_Y_EQ_MIN_Z
Definition ism330dhcx_reg.h:3929
ISM330DHCX_Y_EQ_MIN_X
@ ISM330DHCX_Y_EQ_MIN_X
Definition ism330dhcx_reg.h:3928
ISM330DHCX_Y_EQ_Y
@ ISM330DHCX_Y_EQ_Y
Definition ism330dhcx_reg.h:3925
ISM330DHCX_Y_EQ_X
@ ISM330DHCX_Y_EQ_X
Definition ism330dhcx_reg.h:3927
ISM330DHCX_Y_EQ_Z
@ ISM330DHCX_Y_EQ_Z
Definition ism330dhcx_reg.h:3930
ISM330DHCX_Y_EQ_MIN_Y
@ ISM330DHCX_Y_EQ_MIN_Y
Definition ism330dhcx_reg.h:3926
ISM330DHCX_OPEN_DRAIN
@ ISM330DHCX_OPEN_DRAIN
Definition ism330dhcx_reg.h:3428
ISM330DHCX_PUSH_PULL
@ ISM330DHCX_PUSH_PULL
Definition ism330dhcx_reg.h:3427
ISM330DHCX_Z_EQ_X
@ ISM330DHCX_Z_EQ_X
Definition ism330dhcx_reg.h:3913
ISM330DHCX_Z_EQ_Z
@ ISM330DHCX_Z_EQ_Z
Definition ism330dhcx_reg.h:3916
ISM330DHCX_Z_EQ_MIN_X
@ ISM330DHCX_Z_EQ_MIN_X
Definition ism330dhcx_reg.h:3914
ISM330DHCX_Z_EQ_MIN_Y
@ ISM330DHCX_Z_EQ_MIN_Y
Definition ism330dhcx_reg.h:3912
ISM330DHCX_Z_EQ_MIN_Z
@ ISM330DHCX_Z_EQ_MIN_Z
Definition ism330dhcx_reg.h:3915
ISM330DHCX_Z_EQ_Y
@ ISM330DHCX_Z_EQ_Y
Definition ism330dhcx_reg.h:3911
ISM330DHCX_ACTIVE_LOW
@ ISM330DHCX_ACTIVE_LOW
Definition ism330dhcx_reg.h:3438
ISM330DHCX_ACTIVE_HIGH
@ ISM330DHCX_ACTIVE_HIGH
Definition ism330dhcx_reg.h:3437
ISM330DHCX_16g
@ ISM330DHCX_16g
Definition ism330dhcx_reg.h:2851
ISM330DHCX_8g
@ ISM330DHCX_8g
Definition ism330dhcx_reg.h:2853
ISM330DHCX_4g
@ ISM330DHCX_4g
Definition ism330dhcx_reg.h:2852
ISM330DHCX_2g
@ ISM330DHCX_2g
Definition ism330dhcx_reg.h:2850
ISM330DHCX_AUX_XL_DISABLE
@ ISM330DHCX_AUX_XL_DISABLE
Definition ism330dhcx_reg.h:3224
ISM330DHCX_AUX_XL_POS
@ ISM330DHCX_AUX_XL_POS
Definition ism330dhcx_reg.h:3225
ISM330DHCX_AUX_XL_NEG
@ ISM330DHCX_AUX_XL_NEG
Definition ism330dhcx_reg.h:3226
ISM330DHCX_GY_ST_DISABLE
@ ISM330DHCX_GY_ST_DISABLE
Definition ism330dhcx_reg.h:3092
ISM330DHCX_GY_ST_POSITIVE
@ ISM330DHCX_GY_ST_POSITIVE
Definition ism330dhcx_reg.h:3093
ISM330DHCX_GY_ST_NEGATIVE
@ ISM330DHCX_GY_ST_NEGATIVE
Definition ism330dhcx_reg.h:3094
ISM330DHCX_FF_TSH_219mg
@ ISM330DHCX_FF_TSH_219mg
Definition ism330dhcx_reg.h:3591
ISM330DHCX_FF_TSH_344mg
@ ISM330DHCX_FF_TSH_344mg
Definition ism330dhcx_reg.h:3594
ISM330DHCX_FF_TSH_469mg
@ ISM330DHCX_FF_TSH_469mg
Definition ism330dhcx_reg.h:3596
ISM330DHCX_FF_TSH_500mg
@ ISM330DHCX_FF_TSH_500mg
Definition ism330dhcx_reg.h:3597
ISM330DHCX_FF_TSH_250mg
@ ISM330DHCX_FF_TSH_250mg
Definition ism330dhcx_reg.h:3592
ISM330DHCX_FF_TSH_156mg
@ ISM330DHCX_FF_TSH_156mg
Definition ism330dhcx_reg.h:3590
ISM330DHCX_FF_TSH_312mg
@ ISM330DHCX_FF_TSH_312mg
Definition ism330dhcx_reg.h:3593
ISM330DHCX_FF_TSH_406mg
@ ISM330DHCX_FF_TSH_406mg
Definition ism330dhcx_reg.h:3595
ISM330DHCX_LC_CLEAR_DONE
@ ISM330DHCX_LC_CLEAR_DONE
Definition ism330dhcx_reg.h:3974
ISM330DHCX_LC_NORMAL
@ ISM330DHCX_LC_NORMAL
Definition ism330dhcx_reg.h:3972
ISM330DHCX_LC_CLEAR
@ ISM330DHCX_LC_CLEAR
Definition ism330dhcx_reg.h:3973
ISM330DHCX_XL_ST_NEGATIVE
@ ISM330DHCX_XL_ST_NEGATIVE
Definition ism330dhcx_reg.h:3083
ISM330DHCX_XL_ST_DISABLE
@ ISM330DHCX_XL_ST_DISABLE
Definition ism330dhcx_reg.h:3081
ISM330DHCX_XL_ST_POSITIVE
@ ISM330DHCX_XL_ST_POSITIVE
Definition ism330dhcx_reg.h:3082
ISM330DHCX_LEVEL_TRIGGER
@ ISM330DHCX_LEVEL_TRIGGER
Definition ism330dhcx_reg.h:3814
ISM330DHCX_DEN_DISABLE
@ ISM330DHCX_DEN_DISABLE
Definition ism330dhcx_reg.h:3811
ISM330DHCX_LEVEL_LETCHED
@ ISM330DHCX_LEVEL_LETCHED
Definition ism330dhcx_reg.h:3813
ISM330DHCX_LEVEL_FIFO
@ ISM330DHCX_LEVEL_FIFO
Definition ism330dhcx_reg.h:3812
ISM330DHCX_EDGE_TRIGGER
@ ISM330DHCX_EDGE_TRIGGER
Definition ism330dhcx_reg.h:3815
ISM330DHCX_250dps_AUX
@ ISM330DHCX_250dps_AUX
Definition ism330dhcx_reg.h:3273
ISM330DHCX_500dps_AUX
@ ISM330DHCX_500dps_AUX
Definition ism330dhcx_reg.h:3274
ISM330DHCX_1000dps_AUX
@ ISM330DHCX_1000dps_AUX
Definition ism330dhcx_reg.h:3275
ISM330DHCX_125dps_AUX
@ ISM330DHCX_125dps_AUX
Definition ism330dhcx_reg.h:3272
ISM330DHCX_2000dps_AUX
@ ISM330DHCX_2000dps_AUX
Definition ism330dhcx_reg.h:3276
stmdev_read_ptr
int32_t(* stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t)
Definition ism330dhcx_reg.h:114
stmdev_write_ptr
int32_t(* stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t)
Definition ism330dhcx_reg.h:113
bitwise_t
Definition ism330dhcx_reg.h:80
bitwise_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:97
bitwise_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:92
bitwise_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:96
bitwise_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:95
bitwise_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:91
bitwise_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:94
bitwise_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:98
bitwise_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:93
ism330dhcx_all_int_src_t
Definition ism330dhcx_reg.h:530
ism330dhcx_all_int_src_t::d6d_ia
uint8_t d6d_ia
Definition ism330dhcx_reg.h:544
ism330dhcx_all_int_src_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:542
ism330dhcx_all_int_src_t::ff_ia
uint8_t ff_ia
Definition ism330dhcx_reg.h:548
ism330dhcx_all_int_src_t::double_tap
uint8_t double_tap
Definition ism330dhcx_reg.h:545
ism330dhcx_all_int_src_t::single_tap
uint8_t single_tap
Definition ism330dhcx_reg.h:546
ism330dhcx_all_int_src_t::timestamp_endcount
uint8_t timestamp_endcount
Definition ism330dhcx_reg.h:541
ism330dhcx_all_int_src_t::sleep_change_ia
uint8_t sleep_change_ia
Definition ism330dhcx_reg.h:543
ism330dhcx_all_int_src_t::wu_ia
uint8_t wu_ia
Definition ism330dhcx_reg.h:547
ism330dhcx_all_sources_t
Definition ism330dhcx_reg.h:2949
ism330dhcx_all_sources_t::status_reg
ism330dhcx_status_reg_t status_reg
Definition ism330dhcx_reg.h:2954
ism330dhcx_all_sources_t::wake_up_src
ism330dhcx_wake_up_src_t wake_up_src
Definition ism330dhcx_reg.h:2951
ism330dhcx_all_sources_t::fsm_status_a
ism330dhcx_fsm_status_a_t fsm_status_a
Definition ism330dhcx_reg.h:2956
ism330dhcx_all_sources_t::emb_func_status
ism330dhcx_emb_func_status_t emb_func_status
Definition ism330dhcx_reg.h:2955
ism330dhcx_all_sources_t::d6d_src
ism330dhcx_d6d_src_t d6d_src
Definition ism330dhcx_reg.h:2953
ism330dhcx_all_sources_t::all_int_src
ism330dhcx_all_int_src_t all_int_src
Definition ism330dhcx_reg.h:2950
ism330dhcx_all_sources_t::fsm_status_b
ism330dhcx_fsm_status_b_t fsm_status_b
Definition ism330dhcx_reg.h:2957
ism330dhcx_all_sources_t::tap_src
ism330dhcx_tap_src_t tap_src
Definition ism330dhcx_reg.h:2952
ism330dhcx_counter_bdr_reg1_t
Definition ism330dhcx_reg.h:267
ism330dhcx_counter_bdr_reg1_t::cnt_bdr_th
uint8_t cnt_bdr_th
Definition ism330dhcx_reg.h:279
ism330dhcx_counter_bdr_reg1_t::dataready_pulsed
uint8_t dataready_pulsed
Definition ism330dhcx_reg.h:275
ism330dhcx_counter_bdr_reg1_t::rst_counter_bdr
uint8_t rst_counter_bdr
Definition ism330dhcx_reg.h:276
ism330dhcx_counter_bdr_reg1_t::trig_counter_bdr
uint8_t trig_counter_bdr
Definition ism330dhcx_reg.h:277
ism330dhcx_counter_bdr_reg1_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:278
ism330dhcx_counter_bdr_reg2_t
Definition ism330dhcx_reg.h:285
ism330dhcx_counter_bdr_reg2_t::cnt_bdr_th
uint8_t cnt_bdr_th
Definition ism330dhcx_reg.h:286
ism330dhcx_ctrl10_c_t
Definition ism330dhcx_reg.h:516
ism330dhcx_ctrl10_c_t::timestamp_en
uint8_t timestamp_en
Definition ism330dhcx_reg.h:523
ism330dhcx_ctrl10_c_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:522
ism330dhcx_ctrl10_c_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:524
ism330dhcx_ctrl1_ois_t
Definition ism330dhcx_reg.h:1010
ism330dhcx_ctrl1_ois_t::sim_ois
uint8_t sim_ois
Definition ism330dhcx_reg.h:1022
ism330dhcx_ctrl1_ois_t::lvl1_ois
uint8_t lvl1_ois
Definition ism330dhcx_reg.h:1021
ism330dhcx_ctrl1_ois_t::fs_g_ois
uint8_t fs_g_ois
Definition ism330dhcx_reg.h:1024
ism330dhcx_ctrl1_ois_t::mode4_en
uint8_t mode4_en
Definition ism330dhcx_reg.h:1023
ism330dhcx_ctrl1_ois_t::ois_en_spi2
uint8_t ois_en_spi2
Definition ism330dhcx_reg.h:1026
ism330dhcx_ctrl1_ois_t::fs_125_ois
uint8_t fs_125_ois
Definition ism330dhcx_reg.h:1025
ism330dhcx_ctrl1_ois_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1020
ism330dhcx_ctrl1_xl_t
Definition ism330dhcx_reg.h:340
ism330dhcx_ctrl1_xl_t::lpf2_xl_en
uint8_t lpf2_xl_en
Definition ism330dhcx_reg.h:349
ism330dhcx_ctrl1_xl_t::fs_xl
uint8_t fs_xl
Definition ism330dhcx_reg.h:348
ism330dhcx_ctrl1_xl_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:350
ism330dhcx_ctrl1_xl_t::odr_xl
uint8_t odr_xl
Definition ism330dhcx_reg.h:347
ism330dhcx_ctrl2_g_t
Definition ism330dhcx_reg.h:356
ism330dhcx_ctrl2_g_t::fs_g
uint8_t fs_g
Definition ism330dhcx_reg.h:362
ism330dhcx_ctrl2_g_t::odr_g
uint8_t odr_g
Definition ism330dhcx_reg.h:361
ism330dhcx_ctrl2_ois_t
Definition ism330dhcx_reg.h:1032
ism330dhcx_ctrl2_ois_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1040
ism330dhcx_ctrl2_ois_t::hpm_ois
uint8_t hpm_ois
Definition ism330dhcx_reg.h:1041
ism330dhcx_ctrl2_ois_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1042
ism330dhcx_ctrl2_ois_t::hp_en_ois
uint8_t hp_en_ois
Definition ism330dhcx_reg.h:1044
ism330dhcx_ctrl2_ois_t::ftype_ois
uint8_t ftype_ois
Definition ism330dhcx_reg.h:1043
ism330dhcx_ctrl3_c_t
Definition ism330dhcx_reg.h:368
ism330dhcx_ctrl3_c_t::sw_reset
uint8_t sw_reset
Definition ism330dhcx_reg.h:386
ism330dhcx_ctrl3_c_t::boot
uint8_t boot
Definition ism330dhcx_reg.h:379
ism330dhcx_ctrl3_c_t::h_lactive
uint8_t h_lactive
Definition ism330dhcx_reg.h:381
ism330dhcx_ctrl3_c_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:385
ism330dhcx_ctrl3_c_t::bdu
uint8_t bdu
Definition ism330dhcx_reg.h:380
ism330dhcx_ctrl3_c_t::if_inc
uint8_t if_inc
Definition ism330dhcx_reg.h:384
ism330dhcx_ctrl3_c_t::sim
uint8_t sim
Definition ism330dhcx_reg.h:383
ism330dhcx_ctrl3_c_t::pp_od
uint8_t pp_od
Definition ism330dhcx_reg.h:382
ism330dhcx_ctrl3_ois_t
Definition ism330dhcx_reg.h:1050
ism330dhcx_ctrl3_ois_t::st_ois_clampdis
uint8_t st_ois_clampdis
Definition ism330dhcx_reg.h:1060
ism330dhcx_ctrl3_ois_t::fs_xl_ois
uint8_t fs_xl_ois
Definition ism330dhcx_reg.h:1057
ism330dhcx_ctrl3_ois_t::filter_xl_conf_ois
uint8_t filter_xl_conf_ois
Definition ism330dhcx_reg.h:1058
ism330dhcx_ctrl3_ois_t::st_ois
uint8_t st_ois
Definition ism330dhcx_reg.h:1059
ism330dhcx_ctrl4_c_t
Definition ism330dhcx_reg.h:392
ism330dhcx_ctrl4_c_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:406
ism330dhcx_ctrl4_c_t::not_used_03
uint8_t not_used_03
Definition ism330dhcx_reg.h:403
ism330dhcx_ctrl4_c_t::lpf1_sel_g
uint8_t lpf1_sel_g
Definition ism330dhcx_reg.h:409
ism330dhcx_ctrl4_c_t::sleep_g
uint8_t sleep_g
Definition ism330dhcx_reg.h:404
ism330dhcx_ctrl4_c_t::i2c_disable
uint8_t i2c_disable
Definition ism330dhcx_reg.h:408
ism330dhcx_ctrl4_c_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:410
ism330dhcx_ctrl4_c_t::int2_on_int1
uint8_t int2_on_int1
Definition ism330dhcx_reg.h:405
ism330dhcx_ctrl4_c_t::drdy_mask
uint8_t drdy_mask
Definition ism330dhcx_reg.h:407
ism330dhcx_ctrl5_c_t
Definition ism330dhcx_reg.h:416
ism330dhcx_ctrl5_c_t::st_g
uint8_t st_g
Definition ism330dhcx_reg.h:427
ism330dhcx_ctrl5_c_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:426
ism330dhcx_ctrl5_c_t::rounding
uint8_t rounding
Definition ism330dhcx_reg.h:425
ism330dhcx_ctrl5_c_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:424
ism330dhcx_ctrl5_c_t::st_xl
uint8_t st_xl
Definition ism330dhcx_reg.h:428
ism330dhcx_ctrl6_c_t
Definition ism330dhcx_reg.h:434
ism330dhcx_ctrl6_c_t::den_mode
uint8_t den_mode
Definition ism330dhcx_reg.h:443
ism330dhcx_ctrl6_c_t::usr_off_w
uint8_t usr_off_w
Definition ism330dhcx_reg.h:445
ism330dhcx_ctrl6_c_t::xl_hm_mode
uint8_t xl_hm_mode
Definition ism330dhcx_reg.h:444
ism330dhcx_ctrl6_c_t::ftype
uint8_t ftype
Definition ism330dhcx_reg.h:446
ism330dhcx_ctrl7_g_t
Definition ism330dhcx_reg.h:452
ism330dhcx_ctrl7_g_t::hpm_g
uint8_t hpm_g
Definition ism330dhcx_reg.h:464
ism330dhcx_ctrl7_g_t::hp_en_g
uint8_t hp_en_g
Definition ism330dhcx_reg.h:463
ism330dhcx_ctrl7_g_t::ois_on_en
uint8_t ois_on_en
Definition ism330dhcx_reg.h:466
ism330dhcx_ctrl7_g_t::usr_off_on_out
uint8_t usr_off_on_out
Definition ism330dhcx_reg.h:467
ism330dhcx_ctrl7_g_t::g_hm_mode
uint8_t g_hm_mode
Definition ism330dhcx_reg.h:462
ism330dhcx_ctrl7_g_t::ois_on
uint8_t ois_on
Definition ism330dhcx_reg.h:468
ism330dhcx_ctrl7_g_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:465
ism330dhcx_ctrl8_xl_t
Definition ism330dhcx_reg.h:474
ism330dhcx_ctrl8_xl_t::fastsettl_mode_xl
uint8_t fastsettl_mode_xl
Definition ism330dhcx_reg.h:485
ism330dhcx_ctrl8_xl_t::low_pass_on_6d
uint8_t low_pass_on_6d
Definition ism330dhcx_reg.h:488
ism330dhcx_ctrl8_xl_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:487
ism330dhcx_ctrl8_xl_t::hpcf_xl
uint8_t hpcf_xl
Definition ism330dhcx_reg.h:483
ism330dhcx_ctrl8_xl_t::hp_ref_mode_xl
uint8_t hp_ref_mode_xl
Definition ism330dhcx_reg.h:484
ism330dhcx_ctrl8_xl_t::hp_slope_xl_en
uint8_t hp_slope_xl_en
Definition ism330dhcx_reg.h:486
ism330dhcx_ctrl9_xl_t
Definition ism330dhcx_reg.h:494
ism330dhcx_ctrl9_xl_t::device_conf
uint8_t device_conf
Definition ism330dhcx_reg.h:509
ism330dhcx_ctrl9_xl_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:510
ism330dhcx_ctrl9_xl_t::den_z
uint8_t den_z
Definition ism330dhcx_reg.h:506
ism330dhcx_ctrl9_xl_t::den_y
uint8_t den_y
Definition ism330dhcx_reg.h:505
ism330dhcx_ctrl9_xl_t::den_lh
uint8_t den_lh
Definition ism330dhcx_reg.h:508
ism330dhcx_ctrl9_xl_t::den_xl_g
uint8_t den_xl_g
Definition ism330dhcx_reg.h:507
ism330dhcx_ctrl9_xl_t::den_x
uint8_t den_x
Definition ism330dhcx_reg.h:504
ism330dhcx_d6d_src_t
Definition ism330dhcx_reg.h:602
ism330dhcx_d6d_src_t::xh
uint8_t xh
Definition ism330dhcx_reg.h:619
ism330dhcx_d6d_src_t::yh
uint8_t yh
Definition ism330dhcx_reg.h:617
ism330dhcx_d6d_src_t::den_drdy
uint8_t den_drdy
Definition ism330dhcx_reg.h:613
ism330dhcx_d6d_src_t::yl
uint8_t yl
Definition ism330dhcx_reg.h:618
ism330dhcx_d6d_src_t::xl
uint8_t xl
Definition ism330dhcx_reg.h:620
ism330dhcx_d6d_src_t::zl
uint8_t zl
Definition ism330dhcx_reg.h:616
ism330dhcx_d6d_src_t::d6d_ia
uint8_t d6d_ia
Definition ism330dhcx_reg.h:614
ism330dhcx_d6d_src_t::zh
uint8_t zh
Definition ism330dhcx_reg.h:615
ism330dhcx_datawrite_slv0_t
Definition ism330dhcx_reg.h:2656
ism330dhcx_datawrite_slv0_t::slave0_dataw
uint8_t slave0_dataw
Definition ism330dhcx_reg.h:2657
ism330dhcx_emb_fsm_enable_t
Definition ism330dhcx_reg.h:3958
ism330dhcx_emb_fsm_enable_t::fsm_enable_b
ism330dhcx_fsm_enable_b_t fsm_enable_b
Definition ism330dhcx_reg.h:3960
ism330dhcx_emb_fsm_enable_t::fsm_enable_a
ism330dhcx_fsm_enable_a_t fsm_enable_a
Definition ism330dhcx_reg.h:3959
ism330dhcx_emb_func_en_a_t
Definition ism330dhcx_reg.h:1101
ism330dhcx_emb_func_en_a_t::tilt_en
uint8_t tilt_en
Definition ism330dhcx_reg.h:1111
ism330dhcx_emb_func_en_a_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1109
ism330dhcx_emb_func_en_a_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1113
ism330dhcx_emb_func_en_a_t::sign_motion_en
uint8_t sign_motion_en
Definition ism330dhcx_reg.h:1110
ism330dhcx_emb_func_en_a_t::pedo_en
uint8_t pedo_en
Definition ism330dhcx_reg.h:1112
ism330dhcx_emb_func_en_b_t
Definition ism330dhcx_reg.h:1119
ism330dhcx_emb_func_en_b_t::fsm_en
uint8_t fsm_en
Definition ism330dhcx_reg.h:1131
ism330dhcx_emb_func_en_b_t::mlc_en
uint8_t mlc_en
Definition ism330dhcx_reg.h:1128
ism330dhcx_emb_func_en_b_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1127
ism330dhcx_emb_func_en_b_t::fifo_compr_en
uint8_t fifo_compr_en
Definition ism330dhcx_reg.h:1129
ism330dhcx_emb_func_en_b_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1130
ism330dhcx_emb_func_fifo_cfg_t
Definition ism330dhcx_reg.h:1439
ism330dhcx_emb_func_fifo_cfg_t::pedo_fifo_en
uint8_t pedo_fifo_en
Definition ism330dhcx_reg.h:1446
ism330dhcx_emb_func_fifo_cfg_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1447
ism330dhcx_emb_func_fifo_cfg_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1445
ism330dhcx_emb_func_init_a_t
Definition ism330dhcx_reg.h:1953
ism330dhcx_emb_func_init_a_t::tilt_init
uint8_t tilt_init
Definition ism330dhcx_reg.h:1963
ism330dhcx_emb_func_init_a_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1965
ism330dhcx_emb_func_init_a_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1961
ism330dhcx_emb_func_init_a_t::sig_mot_init
uint8_t sig_mot_init
Definition ism330dhcx_reg.h:1962
ism330dhcx_emb_func_init_a_t::step_det_init
uint8_t step_det_init
Definition ism330dhcx_reg.h:1964
ism330dhcx_emb_func_init_b_t
Definition ism330dhcx_reg.h:1971
ism330dhcx_emb_func_init_b_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1982
ism330dhcx_emb_func_init_b_t::fsm_init
uint8_t fsm_init
Definition ism330dhcx_reg.h:1983
ism330dhcx_emb_func_init_b_t::fifo_compr_init
uint8_t fifo_compr_init
Definition ism330dhcx_reg.h:1981
ism330dhcx_emb_func_init_b_t::mlc_init
uint8_t mlc_init
Definition ism330dhcx_reg.h:1980
ism330dhcx_emb_func_init_b_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1979
ism330dhcx_emb_func_int1_t
Definition ism330dhcx_reg.h:1149
ism330dhcx_emb_func_int1_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1163
ism330dhcx_emb_func_int1_t::int1_sig_mot
uint8_t int1_sig_mot
Definition ism330dhcx_reg.h:1160
ism330dhcx_emb_func_int1_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1159
ism330dhcx_emb_func_int1_t::int1_step_detector
uint8_t int1_step_detector
Definition ism330dhcx_reg.h:1162
ism330dhcx_emb_func_int1_t::int1_tilt
uint8_t int1_tilt
Definition ism330dhcx_reg.h:1161
ism330dhcx_emb_func_int1_t::int1_fsm_lc
uint8_t int1_fsm_lc
Definition ism330dhcx_reg.h:1158
ism330dhcx_emb_func_int2_t
Definition ism330dhcx_reg.h:1241
ism330dhcx_emb_func_int2_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1255
ism330dhcx_emb_func_int2_t::int2_fsm_lc
uint8_t int2_fsm_lc
Definition ism330dhcx_reg.h:1250
ism330dhcx_emb_func_int2_t::int2_step_detector
uint8_t int2_step_detector
Definition ism330dhcx_reg.h:1254
ism330dhcx_emb_func_int2_t::int2_sig_mot
uint8_t int2_sig_mot
Definition ism330dhcx_reg.h:1252
ism330dhcx_emb_func_int2_t::int2_tilt
uint8_t int2_tilt
Definition ism330dhcx_reg.h:1253
ism330dhcx_emb_func_int2_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1251
ism330dhcx_emb_func_odr_cfg_b_t
Definition ism330dhcx_reg.h:1901
ism330dhcx_emb_func_odr_cfg_b_t::fsm_odr
uint8_t fsm_odr
Definition ism330dhcx_reg.h:1908
ism330dhcx_emb_func_odr_cfg_b_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1909
ism330dhcx_emb_func_odr_cfg_b_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1907
ism330dhcx_emb_func_odr_cfg_c_t
Definition ism330dhcx_reg.h:1915
ism330dhcx_emb_func_odr_cfg_c_t::mlc_odr
uint8_t mlc_odr
Definition ism330dhcx_reg.h:1922
ism330dhcx_emb_func_odr_cfg_c_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1921
ism330dhcx_emb_func_odr_cfg_c_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1923
ism330dhcx_emb_func_src_t
Definition ism330dhcx_reg.h:1931
ism330dhcx_emb_func_src_t::step_detected
uint8_t step_detected
Definition ism330dhcx_reg.h:1943
ism330dhcx_emb_func_src_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1942
ism330dhcx_emb_func_src_t::stepcounter_bit_set
uint8_t stepcounter_bit_set
Definition ism330dhcx_reg.h:1946
ism330dhcx_emb_func_src_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1947
ism330dhcx_emb_func_src_t::pedo_rst_step
uint8_t pedo_rst_step
Definition ism330dhcx_reg.h:1941
ism330dhcx_emb_func_src_t::step_overflow
uint8_t step_overflow
Definition ism330dhcx_reg.h:1945
ism330dhcx_emb_func_src_t::step_count_delta_ia
uint8_t step_count_delta_ia
Definition ism330dhcx_reg.h:1944
ism330dhcx_emb_func_status_mainpage_t
Definition ism330dhcx_reg.h:672
ism330dhcx_emb_func_status_mainpage_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:686
ism330dhcx_emb_func_status_mainpage_t::is_step_det
uint8_t is_step_det
Definition ism330dhcx_reg.h:685
ism330dhcx_emb_func_status_mainpage_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:682
ism330dhcx_emb_func_status_mainpage_t::is_fsm_lc
uint8_t is_fsm_lc
Definition ism330dhcx_reg.h:681
ism330dhcx_emb_func_status_mainpage_t::is_sigmot
uint8_t is_sigmot
Definition ism330dhcx_reg.h:683
ism330dhcx_emb_func_status_mainpage_t::is_tilt
uint8_t is_tilt
Definition ism330dhcx_reg.h:684
ism330dhcx_emb_func_status_t
Definition ism330dhcx_reg.h:1333
ism330dhcx_emb_func_status_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:1343
ism330dhcx_emb_func_status_t::is_step_det
uint8_t is_step_det
Definition ism330dhcx_reg.h:1346
ism330dhcx_emb_func_status_t::is_tilt
uint8_t is_tilt
Definition ism330dhcx_reg.h:1345
ism330dhcx_emb_func_status_t::is_fsm_lc
uint8_t is_fsm_lc
Definition ism330dhcx_reg.h:1342
ism330dhcx_emb_func_status_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1347
ism330dhcx_emb_func_status_t::is_sigmot
uint8_t is_sigmot
Definition ism330dhcx_reg.h:1344
ism330dhcx_emb_sh_read_t
Definition ism330dhcx_reg.h:4052
ism330dhcx_emb_sh_read_t::sh_byte_15
ism330dhcx_sensor_hub_15_t sh_byte_15
Definition ism330dhcx_reg.h:4067
ism330dhcx_emb_sh_read_t::sh_byte_2
ism330dhcx_sensor_hub_2_t sh_byte_2
Definition ism330dhcx_reg.h:4054
ism330dhcx_emb_sh_read_t::sh_byte_17
ism330dhcx_sensor_hub_17_t sh_byte_17
Definition ism330dhcx_reg.h:4069
ism330dhcx_emb_sh_read_t::sh_byte_10
ism330dhcx_sensor_hub_10_t sh_byte_10
Definition ism330dhcx_reg.h:4062
ism330dhcx_emb_sh_read_t::sh_byte_14
ism330dhcx_sensor_hub_14_t sh_byte_14
Definition ism330dhcx_reg.h:4066
ism330dhcx_emb_sh_read_t::sh_byte_5
ism330dhcx_sensor_hub_5_t sh_byte_5
Definition ism330dhcx_reg.h:4057
ism330dhcx_emb_sh_read_t::sh_byte_8
ism330dhcx_sensor_hub_8_t sh_byte_8
Definition ism330dhcx_reg.h:4060
ism330dhcx_emb_sh_read_t::sh_byte_4
ism330dhcx_sensor_hub_4_t sh_byte_4
Definition ism330dhcx_reg.h:4056
ism330dhcx_emb_sh_read_t::sh_byte_13
ism330dhcx_sensor_hub_13_t sh_byte_13
Definition ism330dhcx_reg.h:4065
ism330dhcx_emb_sh_read_t::sh_byte_1
ism330dhcx_sensor_hub_1_t sh_byte_1
Definition ism330dhcx_reg.h:4053
ism330dhcx_emb_sh_read_t::sh_byte_18
ism330dhcx_sensor_hub_18_t sh_byte_18
Definition ism330dhcx_reg.h:4070
ism330dhcx_emb_sh_read_t::sh_byte_9
ism330dhcx_sensor_hub_9_t sh_byte_9
Definition ism330dhcx_reg.h:4061
ism330dhcx_emb_sh_read_t::sh_byte_6
ism330dhcx_sensor_hub_6_t sh_byte_6
Definition ism330dhcx_reg.h:4058
ism330dhcx_emb_sh_read_t::sh_byte_12
ism330dhcx_sensor_hub_12_t sh_byte_12
Definition ism330dhcx_reg.h:4064
ism330dhcx_emb_sh_read_t::sh_byte_3
ism330dhcx_sensor_hub_3_t sh_byte_3
Definition ism330dhcx_reg.h:4055
ism330dhcx_emb_sh_read_t::sh_byte_16
ism330dhcx_sensor_hub_16_t sh_byte_16
Definition ism330dhcx_reg.h:4068
ism330dhcx_emb_sh_read_t::sh_byte_7
ism330dhcx_sensor_hub_7_t sh_byte_7
Definition ism330dhcx_reg.h:4059
ism330dhcx_emb_sh_read_t::sh_byte_11
ism330dhcx_sensor_hub_11_t sh_byte_11
Definition ism330dhcx_reg.h:4063
ism330dhcx_fifo_ctrl1_t
Definition ism330dhcx_reg.h:211
ism330dhcx_fifo_ctrl1_t::wtm
uint8_t wtm
Definition ism330dhcx_reg.h:212
ism330dhcx_fifo_ctrl2_t
Definition ism330dhcx_reg.h:217
ism330dhcx_fifo_ctrl2_t::wtm
uint8_t wtm
Definition ism330dhcx_reg.h:233
ism330dhcx_fifo_ctrl2_t::fifo_compr_rt_en
uint8_t fifo_compr_rt_en
Definition ism330dhcx_reg.h:228
ism330dhcx_fifo_ctrl2_t::uncoptr_rate
uint8_t uncoptr_rate
Definition ism330dhcx_reg.h:232
ism330dhcx_fifo_ctrl2_t::stop_on_wtm
uint8_t stop_on_wtm
Definition ism330dhcx_reg.h:227
ism330dhcx_fifo_ctrl2_t::odrchg_en
uint8_t odrchg_en
Definition ism330dhcx_reg.h:230
ism330dhcx_fifo_ctrl2_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:229
ism330dhcx_fifo_ctrl2_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:231
ism330dhcx_fifo_ctrl3_t
Definition ism330dhcx_reg.h:239
ism330dhcx_fifo_ctrl3_t::bdr_gy
uint8_t bdr_gy
Definition ism330dhcx_reg.h:244
ism330dhcx_fifo_ctrl3_t::bdr_xl
uint8_t bdr_xl
Definition ism330dhcx_reg.h:245
ism330dhcx_fifo_ctrl4_t
Definition ism330dhcx_reg.h:251
ism330dhcx_fifo_ctrl4_t::odr_ts_batch
uint8_t odr_ts_batch
Definition ism330dhcx_reg.h:258
ism330dhcx_fifo_ctrl4_t::fifo_mode
uint8_t fifo_mode
Definition ism330dhcx_reg.h:261
ism330dhcx_fifo_ctrl4_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:260
ism330dhcx_fifo_ctrl4_t::odr_t_batch
uint8_t odr_t_batch
Definition ism330dhcx_reg.h:259
ism330dhcx_fifo_data_out_tag_t
Definition ism330dhcx_reg.h:1069
ism330dhcx_fifo_data_out_tag_t::tag_parity
uint8_t tag_parity
Definition ism330dhcx_reg.h:1077
ism330dhcx_fifo_data_out_tag_t::tag_cnt
uint8_t tag_cnt
Definition ism330dhcx_reg.h:1076
ism330dhcx_fifo_data_out_tag_t::tag_sensor
uint8_t tag_sensor
Definition ism330dhcx_reg.h:1075
ism330dhcx_fifo_status1_t
Definition ism330dhcx_reg.h:786
ism330dhcx_fifo_status1_t::diff_fifo
uint8_t diff_fifo
Definition ism330dhcx_reg.h:787
ism330dhcx_fifo_status2_t
Definition ism330dhcx_reg.h:792
ism330dhcx_fifo_status2_t::diff_fifo
uint8_t diff_fifo
Definition ism330dhcx_reg.h:808
ism330dhcx_fifo_status2_t::fifo_wtm_ia
uint8_t fifo_wtm_ia
Definition ism330dhcx_reg.h:802
ism330dhcx_fifo_status2_t::fifo_full_ia
uint8_t fifo_full_ia
Definition ism330dhcx_reg.h:804
ism330dhcx_fifo_status2_t::over_run_latched
uint8_t over_run_latched
Definition ism330dhcx_reg.h:806
ism330dhcx_fifo_status2_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:807
ism330dhcx_fifo_status2_t::counter_bdr_ia
uint8_t counter_bdr_ia
Definition ism330dhcx_reg.h:805
ism330dhcx_fifo_status2_t::fifo_ovr_ia
uint8_t fifo_ovr_ia
Definition ism330dhcx_reg.h:803
ism330dhcx_free_fall_t
Definition ism330dhcx_reg.h:926
ism330dhcx_free_fall_t::ff_ths
uint8_t ff_ths
Definition ism330dhcx_reg.h:932
ism330dhcx_free_fall_t::ff_dur
uint8_t ff_dur
Definition ism330dhcx_reg.h:931
ism330dhcx_fsm_enable_a_t
Definition ism330dhcx_reg.h:1453
ism330dhcx_fsm_enable_a_t::fsm1_en
uint8_t fsm1_en
Definition ism330dhcx_reg.h:1471
ism330dhcx_fsm_enable_a_t::fsm4_en
uint8_t fsm4_en
Definition ism330dhcx_reg.h:1468
ism330dhcx_fsm_enable_a_t::fsm2_en
uint8_t fsm2_en
Definition ism330dhcx_reg.h:1470
ism330dhcx_fsm_enable_a_t::fsm3_en
uint8_t fsm3_en
Definition ism330dhcx_reg.h:1469
ism330dhcx_fsm_enable_a_t::fsm5_en
uint8_t fsm5_en
Definition ism330dhcx_reg.h:1467
ism330dhcx_fsm_enable_a_t::fsm7_en
uint8_t fsm7_en
Definition ism330dhcx_reg.h:1465
ism330dhcx_fsm_enable_a_t::fsm6_en
uint8_t fsm6_en
Definition ism330dhcx_reg.h:1466
ism330dhcx_fsm_enable_a_t::fsm8_en
uint8_t fsm8_en
Definition ism330dhcx_reg.h:1464
ism330dhcx_fsm_enable_b_t
Definition ism330dhcx_reg.h:1477
ism330dhcx_fsm_enable_b_t::fsm10_en
uint8_t fsm10_en
Definition ism330dhcx_reg.h:1494
ism330dhcx_fsm_enable_b_t::fsm13_en
uint8_t fsm13_en
Definition ism330dhcx_reg.h:1491
ism330dhcx_fsm_enable_b_t::fsm9_en
uint8_t fsm9_en
Definition ism330dhcx_reg.h:1495
ism330dhcx_fsm_enable_b_t::fsm14_en
uint8_t fsm14_en
Definition ism330dhcx_reg.h:1490
ism330dhcx_fsm_enable_b_t::fsm11_en
uint8_t fsm11_en
Definition ism330dhcx_reg.h:1493
ism330dhcx_fsm_enable_b_t::fsm16_en
uint8_t fsm16_en
Definition ism330dhcx_reg.h:1488
ism330dhcx_fsm_enable_b_t::fsm12_en
uint8_t fsm12_en
Definition ism330dhcx_reg.h:1492
ism330dhcx_fsm_enable_b_t::fsm15_en
uint8_t fsm15_en
Definition ism330dhcx_reg.h:1489
ism330dhcx_fsm_int1_a_t
Definition ism330dhcx_reg.h:1169
ism330dhcx_fsm_int1_a_t::int1_fsm1
uint8_t int1_fsm1
Definition ism330dhcx_reg.h:1187
ism330dhcx_fsm_int1_a_t::int1_fsm3
uint8_t int1_fsm3
Definition ism330dhcx_reg.h:1185
ism330dhcx_fsm_int1_a_t::int1_fsm8
uint8_t int1_fsm8
Definition ism330dhcx_reg.h:1180
ism330dhcx_fsm_int1_a_t::int1_fsm7
uint8_t int1_fsm7
Definition ism330dhcx_reg.h:1181
ism330dhcx_fsm_int1_a_t::int1_fsm6
uint8_t int1_fsm6
Definition ism330dhcx_reg.h:1182
ism330dhcx_fsm_int1_a_t::int1_fsm4
uint8_t int1_fsm4
Definition ism330dhcx_reg.h:1184
ism330dhcx_fsm_int1_a_t::int1_fsm5
uint8_t int1_fsm5
Definition ism330dhcx_reg.h:1183
ism330dhcx_fsm_int1_a_t::int1_fsm2
uint8_t int1_fsm2
Definition ism330dhcx_reg.h:1186
ism330dhcx_fsm_int1_b_t
Definition ism330dhcx_reg.h:1193
ism330dhcx_fsm_int1_b_t::int1_fsm12
uint8_t int1_fsm12
Definition ism330dhcx_reg.h:1208
ism330dhcx_fsm_int1_b_t::int1_fsm9
uint8_t int1_fsm9
Definition ism330dhcx_reg.h:1211
ism330dhcx_fsm_int1_b_t::int1_fsm15
uint8_t int1_fsm15
Definition ism330dhcx_reg.h:1205
ism330dhcx_fsm_int1_b_t::int1_fsm10
uint8_t int1_fsm10
Definition ism330dhcx_reg.h:1210
ism330dhcx_fsm_int1_b_t::int1_fsm14
uint8_t int1_fsm14
Definition ism330dhcx_reg.h:1206
ism330dhcx_fsm_int1_b_t::int1_fsm13
uint8_t int1_fsm13
Definition ism330dhcx_reg.h:1207
ism330dhcx_fsm_int1_b_t::int1_fsm11
uint8_t int1_fsm11
Definition ism330dhcx_reg.h:1209
ism330dhcx_fsm_int1_b_t::int1_fsm16
uint8_t int1_fsm16
Definition ism330dhcx_reg.h:1204
ism330dhcx_fsm_int2_a_t
Definition ism330dhcx_reg.h:1261
ism330dhcx_fsm_int2_a_t::int2_fsm8
uint8_t int2_fsm8
Definition ism330dhcx_reg.h:1272
ism330dhcx_fsm_int2_a_t::int2_fsm6
uint8_t int2_fsm6
Definition ism330dhcx_reg.h:1274
ism330dhcx_fsm_int2_a_t::int2_fsm5
uint8_t int2_fsm5
Definition ism330dhcx_reg.h:1275
ism330dhcx_fsm_int2_a_t::int2_fsm3
uint8_t int2_fsm3
Definition ism330dhcx_reg.h:1277
ism330dhcx_fsm_int2_a_t::int2_fsm1
uint8_t int2_fsm1
Definition ism330dhcx_reg.h:1279
ism330dhcx_fsm_int2_a_t::int2_fsm4
uint8_t int2_fsm4
Definition ism330dhcx_reg.h:1276
ism330dhcx_fsm_int2_a_t::int2_fsm2
uint8_t int2_fsm2
Definition ism330dhcx_reg.h:1278
ism330dhcx_fsm_int2_a_t::int2_fsm7
uint8_t int2_fsm7
Definition ism330dhcx_reg.h:1273
ism330dhcx_fsm_int2_b_t
Definition ism330dhcx_reg.h:1285
ism330dhcx_fsm_int2_b_t::int2_fsm10
uint8_t int2_fsm10
Definition ism330dhcx_reg.h:1302
ism330dhcx_fsm_int2_b_t::int2_fsm11
uint8_t int2_fsm11
Definition ism330dhcx_reg.h:1301
ism330dhcx_fsm_int2_b_t::int2_fsm13
uint8_t int2_fsm13
Definition ism330dhcx_reg.h:1299
ism330dhcx_fsm_int2_b_t::int2_fsm15
uint8_t int2_fsm15
Definition ism330dhcx_reg.h:1297
ism330dhcx_fsm_int2_b_t::int2_fsm9
uint8_t int2_fsm9
Definition ism330dhcx_reg.h:1303
ism330dhcx_fsm_int2_b_t::int2_fsm14
uint8_t int2_fsm14
Definition ism330dhcx_reg.h:1298
ism330dhcx_fsm_int2_b_t::int2_fsm12
uint8_t int2_fsm12
Definition ism330dhcx_reg.h:1300
ism330dhcx_fsm_int2_b_t::int2_fsm16
uint8_t int2_fsm16
Definition ism330dhcx_reg.h:1296
ism330dhcx_fsm_long_counter_clear_t
Definition ism330dhcx_reg.h:1503
ism330dhcx_fsm_long_counter_clear_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1509
ism330dhcx_fsm_long_counter_clear_t::fsm_lc_clr
uint8_t fsm_lc_clr
Definition ism330dhcx_reg.h:1511
ism330dhcx_fsm_out_t
Definition ism330dhcx_reg.h:3982
ism330dhcx_fsm_out_t::fsm_outs5
ism330dhcx_fsm_outs5_t fsm_outs5
Definition ism330dhcx_reg.h:3987
ism330dhcx_fsm_out_t::fsm_outs8
ism330dhcx_fsm_outs8_t fsm_outs8
Definition ism330dhcx_reg.h:3990
ism330dhcx_fsm_out_t::fsm_outs13
ism330dhcx_fsm_outs13_t fsm_outs13
Definition ism330dhcx_reg.h:3995
ism330dhcx_fsm_out_t::fsm_outs10
ism330dhcx_fsm_outs10_t fsm_outs10
Definition ism330dhcx_reg.h:3992
ism330dhcx_fsm_out_t::fsm_outs15
ism330dhcx_fsm_outs15_t fsm_outs15
Definition ism330dhcx_reg.h:3997
ism330dhcx_fsm_out_t::fsm_outs9
ism330dhcx_fsm_outs9_t fsm_outs9
Definition ism330dhcx_reg.h:3991
ism330dhcx_fsm_out_t::fsm_outs16
ism330dhcx_fsm_outs16_t fsm_outs16
Definition ism330dhcx_reg.h:3998
ism330dhcx_fsm_out_t::fsm_outs3
ism330dhcx_fsm_outs3_t fsm_outs3
Definition ism330dhcx_reg.h:3985
ism330dhcx_fsm_out_t::fsm_outs6
ism330dhcx_fsm_outs6_t fsm_outs6
Definition ism330dhcx_reg.h:3988
ism330dhcx_fsm_out_t::fsm_outs1
ism330dhcx_fsm_outs1_t fsm_outs1
Definition ism330dhcx_reg.h:3983
ism330dhcx_fsm_out_t::fsm_outs14
ism330dhcx_fsm_outs14_t fsm_outs14
Definition ism330dhcx_reg.h:3996
ism330dhcx_fsm_out_t::fsm_outs12
ism330dhcx_fsm_outs12_t fsm_outs12
Definition ism330dhcx_reg.h:3994
ism330dhcx_fsm_out_t::fsm_outs4
ism330dhcx_fsm_outs4_t fsm_outs4
Definition ism330dhcx_reg.h:3986
ism330dhcx_fsm_out_t::fsm_outs7
ism330dhcx_fsm_outs7_t fsm_outs7
Definition ism330dhcx_reg.h:3989
ism330dhcx_fsm_out_t::fsm_outs11
ism330dhcx_fsm_outs11_t fsm_outs11
Definition ism330dhcx_reg.h:3993
ism330dhcx_fsm_out_t::fsm_outs2
ism330dhcx_fsm_outs2_t fsm_outs2
Definition ism330dhcx_reg.h:3984
ism330dhcx_fsm_outs10_t
Definition ism330dhcx_reg.h:1733
ism330dhcx_fsm_outs10_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1744
ism330dhcx_fsm_outs10_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1745
ism330dhcx_fsm_outs10_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1750
ism330dhcx_fsm_outs10_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1747
ism330dhcx_fsm_outs10_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1749
ism330dhcx_fsm_outs10_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1746
ism330dhcx_fsm_outs10_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1751
ism330dhcx_fsm_outs10_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1748
ism330dhcx_fsm_outs11_t
Definition ism330dhcx_reg.h:1757
ism330dhcx_fsm_outs11_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1771
ism330dhcx_fsm_outs11_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1773
ism330dhcx_fsm_outs11_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1769
ism330dhcx_fsm_outs11_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1774
ism330dhcx_fsm_outs11_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1768
ism330dhcx_fsm_outs11_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1775
ism330dhcx_fsm_outs11_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1772
ism330dhcx_fsm_outs11_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1770
ism330dhcx_fsm_outs12_t
Definition ism330dhcx_reg.h:1781
ism330dhcx_fsm_outs12_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1794
ism330dhcx_fsm_outs12_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1797
ism330dhcx_fsm_outs12_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1798
ism330dhcx_fsm_outs12_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1793
ism330dhcx_fsm_outs12_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1799
ism330dhcx_fsm_outs12_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1795
ism330dhcx_fsm_outs12_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1792
ism330dhcx_fsm_outs12_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1796
ism330dhcx_fsm_outs13_t
Definition ism330dhcx_reg.h:1805
ism330dhcx_fsm_outs13_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1823
ism330dhcx_fsm_outs13_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1816
ism330dhcx_fsm_outs13_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1818
ism330dhcx_fsm_outs13_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1819
ism330dhcx_fsm_outs13_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1821
ism330dhcx_fsm_outs13_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1822
ism330dhcx_fsm_outs13_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1817
ism330dhcx_fsm_outs13_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1820
ism330dhcx_fsm_outs14_t
Definition ism330dhcx_reg.h:1829
ism330dhcx_fsm_outs14_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1846
ism330dhcx_fsm_outs14_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1842
ism330dhcx_fsm_outs14_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1840
ism330dhcx_fsm_outs14_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1845
ism330dhcx_fsm_outs14_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1844
ism330dhcx_fsm_outs14_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1843
ism330dhcx_fsm_outs14_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1847
ism330dhcx_fsm_outs14_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1841
ism330dhcx_fsm_outs15_t
Definition ism330dhcx_reg.h:1853
ism330dhcx_fsm_outs15_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1867
ism330dhcx_fsm_outs15_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1865
ism330dhcx_fsm_outs15_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1870
ism330dhcx_fsm_outs15_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1871
ism330dhcx_fsm_outs15_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1864
ism330dhcx_fsm_outs15_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1869
ism330dhcx_fsm_outs15_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1868
ism330dhcx_fsm_outs15_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1866
ism330dhcx_fsm_outs16_t
Definition ism330dhcx_reg.h:1877
ism330dhcx_fsm_outs16_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1895
ism330dhcx_fsm_outs16_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1893
ism330dhcx_fsm_outs16_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1888
ism330dhcx_fsm_outs16_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1891
ism330dhcx_fsm_outs16_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1892
ism330dhcx_fsm_outs16_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1894
ism330dhcx_fsm_outs16_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1890
ism330dhcx_fsm_outs16_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1889
ism330dhcx_fsm_outs1_t
Definition ism330dhcx_reg.h:1517
ism330dhcx_fsm_outs1_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1534
ism330dhcx_fsm_outs1_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1532
ism330dhcx_fsm_outs1_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1531
ism330dhcx_fsm_outs1_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1528
ism330dhcx_fsm_outs1_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1529
ism330dhcx_fsm_outs1_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1533
ism330dhcx_fsm_outs1_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1530
ism330dhcx_fsm_outs1_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1535
ism330dhcx_fsm_outs2_t
Definition ism330dhcx_reg.h:1541
ism330dhcx_fsm_outs2_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1552
ism330dhcx_fsm_outs2_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1553
ism330dhcx_fsm_outs2_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1558
ism330dhcx_fsm_outs2_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1555
ism330dhcx_fsm_outs2_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1554
ism330dhcx_fsm_outs2_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1557
ism330dhcx_fsm_outs2_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1556
ism330dhcx_fsm_outs2_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1559
ism330dhcx_fsm_outs3_t
Definition ism330dhcx_reg.h:1565
ism330dhcx_fsm_outs3_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1580
ism330dhcx_fsm_outs3_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1583
ism330dhcx_fsm_outs3_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1579
ism330dhcx_fsm_outs3_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1582
ism330dhcx_fsm_outs3_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1578
ism330dhcx_fsm_outs3_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1576
ism330dhcx_fsm_outs3_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1581
ism330dhcx_fsm_outs3_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1577
ism330dhcx_fsm_outs4_t
Definition ism330dhcx_reg.h:1589
ism330dhcx_fsm_outs4_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1603
ism330dhcx_fsm_outs4_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1600
ism330dhcx_fsm_outs4_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1601
ism330dhcx_fsm_outs4_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1602
ism330dhcx_fsm_outs4_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1604
ism330dhcx_fsm_outs4_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1605
ism330dhcx_fsm_outs4_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1607
ism330dhcx_fsm_outs4_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1606
ism330dhcx_fsm_outs5_t
Definition ism330dhcx_reg.h:1613
ism330dhcx_fsm_outs5_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1625
ism330dhcx_fsm_outs5_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1627
ism330dhcx_fsm_outs5_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1629
ism330dhcx_fsm_outs5_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1631
ism330dhcx_fsm_outs5_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1626
ism330dhcx_fsm_outs5_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1628
ism330dhcx_fsm_outs5_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1624
ism330dhcx_fsm_outs5_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1630
ism330dhcx_fsm_outs6_t
Definition ism330dhcx_reg.h:1637
ism330dhcx_fsm_outs6_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1655
ism330dhcx_fsm_outs6_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1649
ism330dhcx_fsm_outs6_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1654
ism330dhcx_fsm_outs6_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1653
ism330dhcx_fsm_outs6_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1650
ism330dhcx_fsm_outs6_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1648
ism330dhcx_fsm_outs6_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1651
ism330dhcx_fsm_outs6_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1652
ism330dhcx_fsm_outs7_t
Definition ism330dhcx_reg.h:1661
ism330dhcx_fsm_outs7_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1677
ism330dhcx_fsm_outs7_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1673
ism330dhcx_fsm_outs7_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1674
ism330dhcx_fsm_outs7_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1676
ism330dhcx_fsm_outs7_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1675
ism330dhcx_fsm_outs7_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1672
ism330dhcx_fsm_outs7_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1679
ism330dhcx_fsm_outs7_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1678
ism330dhcx_fsm_outs8_t
Definition ism330dhcx_reg.h:1685
ism330dhcx_fsm_outs8_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1699
ism330dhcx_fsm_outs8_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1701
ism330dhcx_fsm_outs8_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1698
ism330dhcx_fsm_outs8_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1696
ism330dhcx_fsm_outs8_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1702
ism330dhcx_fsm_outs8_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1697
ism330dhcx_fsm_outs8_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1703
ism330dhcx_fsm_outs8_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1700
ism330dhcx_fsm_outs9_t
Definition ism330dhcx_reg.h:1709
ism330dhcx_fsm_outs9_t::n_z
uint8_t n_z
Definition ism330dhcx_reg.h:1725
ism330dhcx_fsm_outs9_t::n_v
uint8_t n_v
Definition ism330dhcx_reg.h:1727
ism330dhcx_fsm_outs9_t::p_y
uint8_t p_y
Definition ism330dhcx_reg.h:1722
ism330dhcx_fsm_outs9_t::n_x
uint8_t n_x
Definition ism330dhcx_reg.h:1721
ism330dhcx_fsm_outs9_t::n_y
uint8_t n_y
Definition ism330dhcx_reg.h:1723
ism330dhcx_fsm_outs9_t::p_x
uint8_t p_x
Definition ism330dhcx_reg.h:1720
ism330dhcx_fsm_outs9_t::p_z
uint8_t p_z
Definition ism330dhcx_reg.h:1724
ism330dhcx_fsm_outs9_t::p_v
uint8_t p_v
Definition ism330dhcx_reg.h:1726
ism330dhcx_fsm_status_a_mainpage_t
Definition ism330dhcx_reg.h:692
ism330dhcx_fsm_status_a_mainpage_t::is_fsm8
uint8_t is_fsm8
Definition ism330dhcx_reg.h:703
ism330dhcx_fsm_status_a_mainpage_t::is_fsm1
uint8_t is_fsm1
Definition ism330dhcx_reg.h:710
ism330dhcx_fsm_status_a_mainpage_t::is_fsm5
uint8_t is_fsm5
Definition ism330dhcx_reg.h:706
ism330dhcx_fsm_status_a_mainpage_t::is_fsm3
uint8_t is_fsm3
Definition ism330dhcx_reg.h:708
ism330dhcx_fsm_status_a_mainpage_t::is_fsm6
uint8_t is_fsm6
Definition ism330dhcx_reg.h:705
ism330dhcx_fsm_status_a_mainpage_t::is_fsm2
uint8_t is_fsm2
Definition ism330dhcx_reg.h:709
ism330dhcx_fsm_status_a_mainpage_t::is_fsm4
uint8_t is_fsm4
Definition ism330dhcx_reg.h:707
ism330dhcx_fsm_status_a_mainpage_t::is_fsm7
uint8_t is_fsm7
Definition ism330dhcx_reg.h:704
ism330dhcx_fsm_status_a_t
Definition ism330dhcx_reg.h:1353
ism330dhcx_fsm_status_a_t::is_fsm8
uint8_t is_fsm8
Definition ism330dhcx_reg.h:1364
ism330dhcx_fsm_status_a_t::is_fsm6
uint8_t is_fsm6
Definition ism330dhcx_reg.h:1366
ism330dhcx_fsm_status_a_t::is_fsm3
uint8_t is_fsm3
Definition ism330dhcx_reg.h:1369
ism330dhcx_fsm_status_a_t::is_fsm4
uint8_t is_fsm4
Definition ism330dhcx_reg.h:1368
ism330dhcx_fsm_status_a_t::is_fsm7
uint8_t is_fsm7
Definition ism330dhcx_reg.h:1365
ism330dhcx_fsm_status_a_t::is_fsm2
uint8_t is_fsm2
Definition ism330dhcx_reg.h:1370
ism330dhcx_fsm_status_a_t::is_fsm1
uint8_t is_fsm1
Definition ism330dhcx_reg.h:1371
ism330dhcx_fsm_status_a_t::is_fsm5
uint8_t is_fsm5
Definition ism330dhcx_reg.h:1367
ism330dhcx_fsm_status_b_mainpage_t
Definition ism330dhcx_reg.h:716
ism330dhcx_fsm_status_b_mainpage_t::is_fsm16
uint8_t is_fsm16
Definition ism330dhcx_reg.h:727
ism330dhcx_fsm_status_b_mainpage_t::is_fsm14
uint8_t is_fsm14
Definition ism330dhcx_reg.h:729
ism330dhcx_fsm_status_b_mainpage_t::is_fsm13
uint8_t is_fsm13
Definition ism330dhcx_reg.h:730
ism330dhcx_fsm_status_b_mainpage_t::is_fsm12
uint8_t is_fsm12
Definition ism330dhcx_reg.h:731
ism330dhcx_fsm_status_b_mainpage_t::is_fsm10
uint8_t is_fsm10
Definition ism330dhcx_reg.h:733
ism330dhcx_fsm_status_b_mainpage_t::is_fsm9
uint8_t is_fsm9
Definition ism330dhcx_reg.h:734
ism330dhcx_fsm_status_b_mainpage_t::is_fsm15
uint8_t is_fsm15
Definition ism330dhcx_reg.h:728
ism330dhcx_fsm_status_b_mainpage_t::is_fsm11
uint8_t is_fsm11
Definition ism330dhcx_reg.h:732
ism330dhcx_fsm_status_b_t
Definition ism330dhcx_reg.h:1377
ism330dhcx_fsm_status_b_t::is_fsm11
uint8_t is_fsm11
Definition ism330dhcx_reg.h:1393
ism330dhcx_fsm_status_b_t::is_fsm16
uint8_t is_fsm16
Definition ism330dhcx_reg.h:1388
ism330dhcx_fsm_status_b_t::is_fsm14
uint8_t is_fsm14
Definition ism330dhcx_reg.h:1390
ism330dhcx_fsm_status_b_t::is_fsm12
uint8_t is_fsm12
Definition ism330dhcx_reg.h:1392
ism330dhcx_fsm_status_b_t::is_fsm9
uint8_t is_fsm9
Definition ism330dhcx_reg.h:1395
ism330dhcx_fsm_status_b_t::is_fsm10
uint8_t is_fsm10
Definition ism330dhcx_reg.h:1394
ism330dhcx_fsm_status_b_t::is_fsm15
uint8_t is_fsm15
Definition ism330dhcx_reg.h:1389
ism330dhcx_fsm_status_b_t::is_fsm13
uint8_t is_fsm13
Definition ism330dhcx_reg.h:1391
ism330dhcx_func_cfg_access_t
Definition ism330dhcx_reg.h:183
ism330dhcx_func_cfg_access_t::reg_access
uint8_t reg_access
Definition ism330dhcx_reg.h:190
ism330dhcx_func_cfg_access_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:191
ism330dhcx_int1_ctrl_t
Definition ism330dhcx_reg.h:291
ism330dhcx_int1_ctrl_t::den_drdy_flag
uint8_t den_drdy_flag
Definition ism330dhcx_reg.h:302
ism330dhcx_int1_ctrl_t::int1_drdy_g
uint8_t int1_drdy_g
Definition ism330dhcx_reg.h:308
ism330dhcx_int1_ctrl_t::int1_cnt_bdr
uint8_t int1_cnt_bdr
Definition ism330dhcx_reg.h:303
ism330dhcx_int1_ctrl_t::int1_fifo_ovr
uint8_t int1_fifo_ovr
Definition ism330dhcx_reg.h:305
ism330dhcx_int1_ctrl_t::int1_drdy_xl
uint8_t int1_drdy_xl
Definition ism330dhcx_reg.h:309
ism330dhcx_int1_ctrl_t::int1_fifo_th
uint8_t int1_fifo_th
Definition ism330dhcx_reg.h:306
ism330dhcx_int1_ctrl_t::int1_boot
uint8_t int1_boot
Definition ism330dhcx_reg.h:307
ism330dhcx_int1_ctrl_t::int1_fifo_full
uint8_t int1_fifo_full
Definition ism330dhcx_reg.h:304
ism330dhcx_int2_ctrl_t
Definition ism330dhcx_reg.h:315
ism330dhcx_int2_ctrl_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:326
ism330dhcx_int2_ctrl_t::int2_fifo_th
uint8_t int2_fifo_th
Definition ism330dhcx_reg.h:330
ism330dhcx_int2_ctrl_t::int2_drdy_g
uint8_t int2_drdy_g
Definition ism330dhcx_reg.h:332
ism330dhcx_int2_ctrl_t::int2_drdy_temp
uint8_t int2_drdy_temp
Definition ism330dhcx_reg.h:331
ism330dhcx_int2_ctrl_t::int2_cnt_bdr
uint8_t int2_cnt_bdr
Definition ism330dhcx_reg.h:327
ism330dhcx_int2_ctrl_t::int2_fifo_ovr
uint8_t int2_fifo_ovr
Definition ism330dhcx_reg.h:329
ism330dhcx_int2_ctrl_t::int2_fifo_full
uint8_t int2_fifo_full
Definition ism330dhcx_reg.h:328
ism330dhcx_int2_ctrl_t::int2_drdy_xl
uint8_t int2_drdy_xl
Definition ism330dhcx_reg.h:333
ism330dhcx_int_dur2_t
Definition ism330dhcx_reg.h:882
ism330dhcx_int_dur2_t::dur
uint8_t dur
Definition ism330dhcx_reg.h:888
ism330dhcx_int_dur2_t::quiet
uint8_t quiet
Definition ism330dhcx_reg.h:889
ism330dhcx_int_dur2_t::shock
uint8_t shock
Definition ism330dhcx_reg.h:890
ism330dhcx_int_ois_t
Definition ism330dhcx_reg.h:992
ism330dhcx_int_ois_t::den_lh_ois
uint8_t den_lh_ois
Definition ism330dhcx_reg.h:1002
ism330dhcx_int_ois_t::st_xl_ois
uint8_t st_xl_ois
Definition ism330dhcx_reg.h:1004
ism330dhcx_int_ois_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1003
ism330dhcx_int_ois_t::lvl2_ois
uint8_t lvl2_ois
Definition ism330dhcx_reg.h:1001
ism330dhcx_int_ois_t::int2_drdy_ois
uint8_t int2_drdy_ois
Definition ism330dhcx_reg.h:1000
ism330dhcx_internal_freq_fine_t
Definition ism330dhcx_reg.h:986
ism330dhcx_internal_freq_fine_t::freq_fine
uint8_t freq_fine
Definition ism330dhcx_reg.h:987
ism330dhcx_mag_cfg_a_t
Definition ism330dhcx_reg.h:2017
ism330dhcx_mag_cfg_a_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:2024
ism330dhcx_mag_cfg_a_t::mag_z_axis
uint8_t mag_z_axis
Definition ism330dhcx_reg.h:2027
ism330dhcx_mag_cfg_a_t::mag_y_axis
uint8_t mag_y_axis
Definition ism330dhcx_reg.h:2025
ism330dhcx_mag_cfg_a_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2026
ism330dhcx_mag_cfg_b_t
Definition ism330dhcx_reg.h:2033
ism330dhcx_mag_cfg_b_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2038
ism330dhcx_mag_cfg_b_t::mag_x_axis
uint8_t mag_x_axis
Definition ism330dhcx_reg.h:2039
ism330dhcx_master_config_t
Definition ism330dhcx_reg.h:2501
ism330dhcx_master_config_t::rst_master_regs
uint8_t rst_master_regs
Definition ism330dhcx_reg.h:2511
ism330dhcx_master_config_t::aux_sens_on
uint8_t aux_sens_on
Definition ism330dhcx_reg.h:2517
ism330dhcx_master_config_t::shub_pu_en
uint8_t shub_pu_en
Definition ism330dhcx_reg.h:2515
ism330dhcx_master_config_t::pass_through_mode
uint8_t pass_through_mode
Definition ism330dhcx_reg.h:2514
ism330dhcx_master_config_t::master_on
uint8_t master_on
Definition ism330dhcx_reg.h:2516
ism330dhcx_master_config_t::start_config
uint8_t start_config
Definition ism330dhcx_reg.h:2513
ism330dhcx_master_config_t::write_once
uint8_t write_once
Definition ism330dhcx_reg.h:2512
ism330dhcx_md1_cfg_t
Definition ism330dhcx_reg.h:938
ism330dhcx_md1_cfg_t::int1_ff
uint8_t int1_ff
Definition ism330dhcx_reg.h:952
ism330dhcx_md1_cfg_t::int1_wu
uint8_t int1_wu
Definition ism330dhcx_reg.h:951
ism330dhcx_md1_cfg_t::int1_emb_func
uint8_t int1_emb_func
Definition ism330dhcx_reg.h:955
ism330dhcx_md1_cfg_t::int1_sleep_change
uint8_t int1_sleep_change
Definition ism330dhcx_reg.h:949
ism330dhcx_md1_cfg_t::int1_double_tap
uint8_t int1_double_tap
Definition ism330dhcx_reg.h:953
ism330dhcx_md1_cfg_t::int1_shub
uint8_t int1_shub
Definition ism330dhcx_reg.h:956
ism330dhcx_md1_cfg_t::int1_6d
uint8_t int1_6d
Definition ism330dhcx_reg.h:954
ism330dhcx_md1_cfg_t::int1_single_tap
uint8_t int1_single_tap
Definition ism330dhcx_reg.h:950
ism330dhcx_md2_cfg_t
Definition ism330dhcx_reg.h:962
ism330dhcx_md2_cfg_t::int2_emb_func
uint8_t int2_emb_func
Definition ism330dhcx_reg.h:979
ism330dhcx_md2_cfg_t::int2_ff
uint8_t int2_ff
Definition ism330dhcx_reg.h:976
ism330dhcx_md2_cfg_t::int2_double_tap
uint8_t int2_double_tap
Definition ism330dhcx_reg.h:977
ism330dhcx_md2_cfg_t::int2_timestamp
uint8_t int2_timestamp
Definition ism330dhcx_reg.h:980
ism330dhcx_md2_cfg_t::int2_sleep_change
uint8_t int2_sleep_change
Definition ism330dhcx_reg.h:973
ism330dhcx_md2_cfg_t::int2_wu
uint8_t int2_wu
Definition ism330dhcx_reg.h:975
ism330dhcx_md2_cfg_t::int2_single_tap
uint8_t int2_single_tap
Definition ism330dhcx_reg.h:974
ism330dhcx_md2_cfg_t::int2_6d
uint8_t int2_6d
Definition ism330dhcx_reg.h:978
ism330dhcx_mlc_int1_t
Definition ism330dhcx_reg.h:1217
ism330dhcx_mlc_int1_t::int1_mlc2
uint8_t int1_mlc2
Definition ism330dhcx_reg.h:1234
ism330dhcx_mlc_int1_t::int1_mlc3
uint8_t int1_mlc3
Definition ism330dhcx_reg.h:1233
ism330dhcx_mlc_int1_t::int1_mlc8
uint8_t int1_mlc8
Definition ism330dhcx_reg.h:1228
ism330dhcx_mlc_int1_t::int1_mlc1
uint8_t int1_mlc1
Definition ism330dhcx_reg.h:1235
ism330dhcx_mlc_int1_t::int1_mlc6
uint8_t int1_mlc6
Definition ism330dhcx_reg.h:1230
ism330dhcx_mlc_int1_t::int1_mlc4
uint8_t int1_mlc4
Definition ism330dhcx_reg.h:1232
ism330dhcx_mlc_int1_t::int1_mlc5
uint8_t int1_mlc5
Definition ism330dhcx_reg.h:1231
ism330dhcx_mlc_int1_t::int1_mlc7
uint8_t int1_mlc7
Definition ism330dhcx_reg.h:1229
ism330dhcx_mlc_int2_t
Definition ism330dhcx_reg.h:1309
ism330dhcx_mlc_int2_t::int2_mlc1
uint8_t int2_mlc1
Definition ism330dhcx_reg.h:1327
ism330dhcx_mlc_int2_t::int2_mlc3
uint8_t int2_mlc3
Definition ism330dhcx_reg.h:1325
ism330dhcx_mlc_int2_t::int2_mlc5
uint8_t int2_mlc5
Definition ism330dhcx_reg.h:1323
ism330dhcx_mlc_int2_t::int2_mlc2
uint8_t int2_mlc2
Definition ism330dhcx_reg.h:1326
ism330dhcx_mlc_int2_t::int2_mlc7
uint8_t int2_mlc7
Definition ism330dhcx_reg.h:1321
ism330dhcx_mlc_int2_t::int2_mlc4
uint8_t int2_mlc4
Definition ism330dhcx_reg.h:1324
ism330dhcx_mlc_int2_t::int2_mlc6
uint8_t int2_mlc6
Definition ism330dhcx_reg.h:1322
ism330dhcx_mlc_int2_t::int2_mlc8
uint8_t int2_mlc8
Definition ism330dhcx_reg.h:1320
ism330dhcx_mlc_status_mainpage_t
Definition ism330dhcx_reg.h:740
ism330dhcx_mlc_status_mainpage_t::is_mlc4
uint8_t is_mlc4
Definition ism330dhcx_reg.h:755
ism330dhcx_mlc_status_mainpage_t::is_mlc2
uint8_t is_mlc2
Definition ism330dhcx_reg.h:757
ism330dhcx_mlc_status_mainpage_t::is_mlc5
uint8_t is_mlc5
Definition ism330dhcx_reg.h:754
ism330dhcx_mlc_status_mainpage_t::is_mlc6
uint8_t is_mlc6
Definition ism330dhcx_reg.h:753
ism330dhcx_mlc_status_mainpage_t::is_mlc8
uint8_t is_mlc8
Definition ism330dhcx_reg.h:751
ism330dhcx_mlc_status_mainpage_t::is_mlc3
uint8_t is_mlc3
Definition ism330dhcx_reg.h:756
ism330dhcx_mlc_status_mainpage_t::is_mlc7
uint8_t is_mlc7
Definition ism330dhcx_reg.h:752
ism330dhcx_mlc_status_mainpage_t::is_mlc1
uint8_t is_mlc1
Definition ism330dhcx_reg.h:758
ism330dhcx_mlc_status_t
Definition ism330dhcx_reg.h:1401
ism330dhcx_mlc_status_t::is_mlc5
uint8_t is_mlc5
Definition ism330dhcx_reg.h:1415
ism330dhcx_mlc_status_t::is_mlc4
uint8_t is_mlc4
Definition ism330dhcx_reg.h:1416
ism330dhcx_mlc_status_t::is_mlc6
uint8_t is_mlc6
Definition ism330dhcx_reg.h:1414
ism330dhcx_mlc_status_t::is_mlc1
uint8_t is_mlc1
Definition ism330dhcx_reg.h:1419
ism330dhcx_mlc_status_t::is_mlc3
uint8_t is_mlc3
Definition ism330dhcx_reg.h:1417
ism330dhcx_mlc_status_t::is_mlc2
uint8_t is_mlc2
Definition ism330dhcx_reg.h:1418
ism330dhcx_mlc_status_t::is_mlc8
uint8_t is_mlc8
Definition ism330dhcx_reg.h:1412
ism330dhcx_mlc_status_t::is_mlc7
uint8_t is_mlc7
Definition ism330dhcx_reg.h:1413
ism330dhcx_page_address_t
Definition ism330dhcx_reg.h:1137
ism330dhcx_page_address_t::page_addr
uint8_t page_addr
Definition ism330dhcx_reg.h:1138
ism330dhcx_page_rw_t
Definition ism330dhcx_reg.h:1425
ism330dhcx_page_rw_t::emb_func_lir
uint8_t emb_func_lir
Definition ism330dhcx_reg.h:1431
ism330dhcx_page_rw_t::page_rw
uint8_t page_rw
Definition ism330dhcx_reg.h:1432
ism330dhcx_page_rw_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1433
ism330dhcx_page_sel_t
Definition ism330dhcx_reg.h:1089
ism330dhcx_page_sel_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:1095
ism330dhcx_page_sel_t::page_sel
uint8_t page_sel
Definition ism330dhcx_reg.h:1094
ism330dhcx_page_value_t
Definition ism330dhcx_reg.h:1143
ism330dhcx_page_value_t::page_value
uint8_t page_value
Definition ism330dhcx_reg.h:1144
ism330dhcx_pedo_cmd_reg_t
Definition ism330dhcx_reg.h:2050
ism330dhcx_pedo_cmd_reg_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2058
ism330dhcx_pedo_cmd_reg_t::carry_count_en
uint8_t carry_count_en
Definition ism330dhcx_reg.h:2057
ism330dhcx_pedo_cmd_reg_t::not_used_02
uint8_t not_used_02
Definition ism330dhcx_reg.h:2056
ism330dhcx_pin_ctrl_t
Definition ism330dhcx_reg.h:197
ism330dhcx_pin_ctrl_t::sdo_pu_en
uint8_t sdo_pu_en
Definition ism330dhcx_reg.h:204
ism330dhcx_pin_ctrl_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:205
ism330dhcx_pin_ctrl_t::ois_pu_dis
uint8_t ois_pu_dis
Definition ism330dhcx_reg.h:203
ism330dhcx_pin_int1_route_t
Definition ism330dhcx_reg.h:3398
ism330dhcx_pin_int1_route_t::int1_ctrl
ism330dhcx_int1_ctrl_t int1_ctrl
Definition ism330dhcx_reg.h:3399
ism330dhcx_pin_int1_route_t::md1_cfg
ism330dhcx_md1_cfg_t md1_cfg
Definition ism330dhcx_reg.h:3400
ism330dhcx_pin_int1_route_t::fsm_int1_b
ism330dhcx_fsm_int1_b_t fsm_int1_b
Definition ism330dhcx_reg.h:3403
ism330dhcx_pin_int1_route_t::emb_func_int1
ism330dhcx_emb_func_int1_t emb_func_int1
Definition ism330dhcx_reg.h:3401
ism330dhcx_pin_int1_route_t::mlc_int1
ism330dhcx_mlc_int1_t mlc_int1
Definition ism330dhcx_reg.h:3404
ism330dhcx_pin_int1_route_t::fsm_int1_a
ism330dhcx_fsm_int1_a_t fsm_int1_a
Definition ism330dhcx_reg.h:3402
ism330dhcx_pin_int2_route_t
Definition ism330dhcx_reg.h:3412
ism330dhcx_pin_int2_route_t::emb_func_int2
ism330dhcx_emb_func_int2_t emb_func_int2
Definition ism330dhcx_reg.h:3415
ism330dhcx_pin_int2_route_t::md2_cfg
ism330dhcx_md2_cfg_t md2_cfg
Definition ism330dhcx_reg.h:3414
ism330dhcx_pin_int2_route_t::fsm_int2_a
ism330dhcx_fsm_int2_a_t fsm_int2_a
Definition ism330dhcx_reg.h:3416
ism330dhcx_pin_int2_route_t::fsm_int2_b
ism330dhcx_fsm_int2_b_t fsm_int2_b
Definition ism330dhcx_reg.h:3417
ism330dhcx_pin_int2_route_t::int2_ctrl
ism330dhcx_int2_ctrl_t int2_ctrl
Definition ism330dhcx_reg.h:3413
ism330dhcx_pin_int2_route_t::mlc_int2
ism330dhcx_mlc_int2_t mlc_int2
Definition ism330dhcx_reg.h:3418
ism330dhcx_sensor_hub_10_t
Definition ism330dhcx_reg.h:2285
ism330dhcx_sensor_hub_10_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2303
ism330dhcx_sensor_hub_10_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2297
ism330dhcx_sensor_hub_10_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2301
ism330dhcx_sensor_hub_10_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2300
ism330dhcx_sensor_hub_10_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2302
ism330dhcx_sensor_hub_10_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2298
ism330dhcx_sensor_hub_10_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2296
ism330dhcx_sensor_hub_10_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2299
ism330dhcx_sensor_hub_11_t
Definition ism330dhcx_reg.h:2309
ism330dhcx_sensor_hub_11_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2320
ism330dhcx_sensor_hub_11_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2326
ism330dhcx_sensor_hub_11_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2322
ism330dhcx_sensor_hub_11_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2325
ism330dhcx_sensor_hub_11_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2323
ism330dhcx_sensor_hub_11_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2324
ism330dhcx_sensor_hub_11_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2321
ism330dhcx_sensor_hub_11_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2327
ism330dhcx_sensor_hub_12_t
Definition ism330dhcx_reg.h:2333
ism330dhcx_sensor_hub_12_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2346
ism330dhcx_sensor_hub_12_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2345
ism330dhcx_sensor_hub_12_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2351
ism330dhcx_sensor_hub_12_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2349
ism330dhcx_sensor_hub_12_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2350
ism330dhcx_sensor_hub_12_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2348
ism330dhcx_sensor_hub_12_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2347
ism330dhcx_sensor_hub_12_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2344
ism330dhcx_sensor_hub_13_t
Definition ism330dhcx_reg.h:2357
ism330dhcx_sensor_hub_13_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2369
ism330dhcx_sensor_hub_13_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2374
ism330dhcx_sensor_hub_13_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2368
ism330dhcx_sensor_hub_13_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2375
ism330dhcx_sensor_hub_13_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2373
ism330dhcx_sensor_hub_13_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2371
ism330dhcx_sensor_hub_13_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2370
ism330dhcx_sensor_hub_13_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2372
ism330dhcx_sensor_hub_14_t
Definition ism330dhcx_reg.h:2381
ism330dhcx_sensor_hub_14_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2399
ism330dhcx_sensor_hub_14_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2392
ism330dhcx_sensor_hub_14_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2395
ism330dhcx_sensor_hub_14_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2397
ism330dhcx_sensor_hub_14_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2398
ism330dhcx_sensor_hub_14_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2393
ism330dhcx_sensor_hub_14_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2394
ism330dhcx_sensor_hub_14_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2396
ism330dhcx_sensor_hub_15_t
Definition ism330dhcx_reg.h:2405
ism330dhcx_sensor_hub_15_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2422
ism330dhcx_sensor_hub_15_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2420
ism330dhcx_sensor_hub_15_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2417
ism330dhcx_sensor_hub_15_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2418
ism330dhcx_sensor_hub_15_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2419
ism330dhcx_sensor_hub_15_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2423
ism330dhcx_sensor_hub_15_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2416
ism330dhcx_sensor_hub_15_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2421
ism330dhcx_sensor_hub_16_t
Definition ism330dhcx_reg.h:2429
ism330dhcx_sensor_hub_16_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2444
ism330dhcx_sensor_hub_16_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2442
ism330dhcx_sensor_hub_16_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2447
ism330dhcx_sensor_hub_16_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2445
ism330dhcx_sensor_hub_16_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2440
ism330dhcx_sensor_hub_16_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2443
ism330dhcx_sensor_hub_16_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2446
ism330dhcx_sensor_hub_16_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2441
ism330dhcx_sensor_hub_17_t
Definition ism330dhcx_reg.h:2453
ism330dhcx_sensor_hub_17_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2470
ism330dhcx_sensor_hub_17_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2464
ism330dhcx_sensor_hub_17_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2468
ism330dhcx_sensor_hub_17_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2466
ism330dhcx_sensor_hub_17_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2469
ism330dhcx_sensor_hub_17_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2465
ism330dhcx_sensor_hub_17_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2467
ism330dhcx_sensor_hub_17_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2471
ism330dhcx_sensor_hub_18_t
Definition ism330dhcx_reg.h:2477
ism330dhcx_sensor_hub_18_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2492
ism330dhcx_sensor_hub_18_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2489
ism330dhcx_sensor_hub_18_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2490
ism330dhcx_sensor_hub_18_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2493
ism330dhcx_sensor_hub_18_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2494
ism330dhcx_sensor_hub_18_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2488
ism330dhcx_sensor_hub_18_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2491
ism330dhcx_sensor_hub_18_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2495
ism330dhcx_sensor_hub_1_t
Definition ism330dhcx_reg.h:2069
ism330dhcx_sensor_hub_1_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2084
ism330dhcx_sensor_hub_1_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2087
ism330dhcx_sensor_hub_1_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2086
ism330dhcx_sensor_hub_1_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2085
ism330dhcx_sensor_hub_1_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2083
ism330dhcx_sensor_hub_1_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2081
ism330dhcx_sensor_hub_1_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2080
ism330dhcx_sensor_hub_1_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2082
ism330dhcx_sensor_hub_2_t
Definition ism330dhcx_reg.h:2093
ism330dhcx_sensor_hub_2_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2105
ism330dhcx_sensor_hub_2_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2106
ism330dhcx_sensor_hub_2_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2111
ism330dhcx_sensor_hub_2_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2109
ism330dhcx_sensor_hub_2_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2108
ism330dhcx_sensor_hub_2_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2110
ism330dhcx_sensor_hub_2_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2107
ism330dhcx_sensor_hub_2_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2104
ism330dhcx_sensor_hub_3_t
Definition ism330dhcx_reg.h:2117
ism330dhcx_sensor_hub_3_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2129
ism330dhcx_sensor_hub_3_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2131
ism330dhcx_sensor_hub_3_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2134
ism330dhcx_sensor_hub_3_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2132
ism330dhcx_sensor_hub_3_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2135
ism330dhcx_sensor_hub_3_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2130
ism330dhcx_sensor_hub_3_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2128
ism330dhcx_sensor_hub_3_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2133
ism330dhcx_sensor_hub_4_t
Definition ism330dhcx_reg.h:2141
ism330dhcx_sensor_hub_4_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2154
ism330dhcx_sensor_hub_4_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2153
ism330dhcx_sensor_hub_4_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2159
ism330dhcx_sensor_hub_4_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2156
ism330dhcx_sensor_hub_4_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2158
ism330dhcx_sensor_hub_4_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2155
ism330dhcx_sensor_hub_4_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2157
ism330dhcx_sensor_hub_4_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2152
ism330dhcx_sensor_hub_5_t
Definition ism330dhcx_reg.h:2165
ism330dhcx_sensor_hub_5_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2178
ism330dhcx_sensor_hub_5_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2181
ism330dhcx_sensor_hub_5_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2177
ism330dhcx_sensor_hub_5_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2182
ism330dhcx_sensor_hub_5_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2179
ism330dhcx_sensor_hub_5_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2180
ism330dhcx_sensor_hub_5_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2183
ism330dhcx_sensor_hub_5_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2176
ism330dhcx_sensor_hub_6_t
Definition ism330dhcx_reg.h:2189
ism330dhcx_sensor_hub_6_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2200
ism330dhcx_sensor_hub_6_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2202
ism330dhcx_sensor_hub_6_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2205
ism330dhcx_sensor_hub_6_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2206
ism330dhcx_sensor_hub_6_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2201
ism330dhcx_sensor_hub_6_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2207
ism330dhcx_sensor_hub_6_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2204
ism330dhcx_sensor_hub_6_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2203
ism330dhcx_sensor_hub_7_t
Definition ism330dhcx_reg.h:2213
ism330dhcx_sensor_hub_7_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2228
ism330dhcx_sensor_hub_7_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2225
ism330dhcx_sensor_hub_7_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2224
ism330dhcx_sensor_hub_7_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2226
ism330dhcx_sensor_hub_7_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2230
ism330dhcx_sensor_hub_7_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2227
ism330dhcx_sensor_hub_7_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2229
ism330dhcx_sensor_hub_7_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2231
ism330dhcx_sensor_hub_8_t
Definition ism330dhcx_reg.h:2237
ism330dhcx_sensor_hub_8_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2248
ism330dhcx_sensor_hub_8_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2249
ism330dhcx_sensor_hub_8_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2254
ism330dhcx_sensor_hub_8_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2253
ism330dhcx_sensor_hub_8_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2252
ism330dhcx_sensor_hub_8_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2251
ism330dhcx_sensor_hub_8_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2250
ism330dhcx_sensor_hub_8_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2255
ism330dhcx_sensor_hub_9_t
Definition ism330dhcx_reg.h:2261
ism330dhcx_sensor_hub_9_t::bit5
uint8_t bit5
Definition ism330dhcx_reg.h:2274
ism330dhcx_sensor_hub_9_t::bit0
uint8_t bit0
Definition ism330dhcx_reg.h:2279
ism330dhcx_sensor_hub_9_t::bit2
uint8_t bit2
Definition ism330dhcx_reg.h:2277
ism330dhcx_sensor_hub_9_t::bit4
uint8_t bit4
Definition ism330dhcx_reg.h:2275
ism330dhcx_sensor_hub_9_t::bit6
uint8_t bit6
Definition ism330dhcx_reg.h:2273
ism330dhcx_sensor_hub_9_t::bit7
uint8_t bit7
Definition ism330dhcx_reg.h:2272
ism330dhcx_sensor_hub_9_t::bit3
uint8_t bit3
Definition ism330dhcx_reg.h:2276
ism330dhcx_sensor_hub_9_t::bit1
uint8_t bit1
Definition ism330dhcx_reg.h:2278
ism330dhcx_sh_cfg_read_t
Definition ism330dhcx_reg.h:4151
ism330dhcx_sh_cfg_read_t::slv_len
uint8_t slv_len
Definition ism330dhcx_reg.h:4154
ism330dhcx_sh_cfg_read_t::slv_subadd
uint8_t slv_subadd
Definition ism330dhcx_reg.h:4153
ism330dhcx_sh_cfg_read_t::slv_add
uint8_t slv_add
Definition ism330dhcx_reg.h:4152
ism330dhcx_sh_cfg_write_t
Definition ism330dhcx_reg.h:4142
ism330dhcx_sh_cfg_write_t::slv0_data
uint8_t slv0_data
Definition ism330dhcx_reg.h:4145
ism330dhcx_sh_cfg_write_t::slv0_subadd
uint8_t slv0_subadd
Definition ism330dhcx_reg.h:4144
ism330dhcx_sh_cfg_write_t::slv0_add
uint8_t slv0_add
Definition ism330dhcx_reg.h:4143
ism330dhcx_slv0_add_t
Definition ism330dhcx_reg.h:2524
ism330dhcx_slv0_add_t::slave0
uint8_t slave0
Definition ism330dhcx_reg.h:2529
ism330dhcx_slv0_add_t::rw_0
uint8_t rw_0
Definition ism330dhcx_reg.h:2530
ism330dhcx_slv0_config_t
Definition ism330dhcx_reg.h:2543
ism330dhcx_slv0_config_t::slave0_numop
uint8_t slave0_numop
Definition ism330dhcx_reg.h:2553
ism330dhcx_slv0_config_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2551
ism330dhcx_slv0_config_t::batch_ext_sens_0_en
uint8_t batch_ext_sens_0_en
Definition ism330dhcx_reg.h:2552
ism330dhcx_slv0_config_t::shub_odr
uint8_t shub_odr
Definition ism330dhcx_reg.h:2550
ism330dhcx_slv0_subadd_t
Definition ism330dhcx_reg.h:2537
ism330dhcx_slv0_subadd_t::slave0_reg
uint8_t slave0_reg
Definition ism330dhcx_reg.h:2538
ism330dhcx_slv1_add_t
Definition ism330dhcx_reg.h:2560
ism330dhcx_slv1_add_t::slave1_add
uint8_t slave1_add
Definition ism330dhcx_reg.h:2565
ism330dhcx_slv1_add_t::r_1
uint8_t r_1
Definition ism330dhcx_reg.h:2566
ism330dhcx_slv1_config_t
Definition ism330dhcx_reg.h:2578
ism330dhcx_slv1_config_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2584
ism330dhcx_slv1_config_t::slave1_numop
uint8_t slave1_numop
Definition ism330dhcx_reg.h:2586
ism330dhcx_slv1_config_t::batch_ext_sens_1_en
uint8_t batch_ext_sens_1_en
Definition ism330dhcx_reg.h:2585
ism330dhcx_slv1_subadd_t
Definition ism330dhcx_reg.h:2572
ism330dhcx_slv1_subadd_t::slave1_reg
uint8_t slave1_reg
Definition ism330dhcx_reg.h:2573
ism330dhcx_slv2_add_t
Definition ism330dhcx_reg.h:2592
ism330dhcx_slv2_add_t::r_2
uint8_t r_2
Definition ism330dhcx_reg.h:2598
ism330dhcx_slv2_add_t::slave2_add
uint8_t slave2_add
Definition ism330dhcx_reg.h:2597
ism330dhcx_slv2_config_t
Definition ism330dhcx_reg.h:2610
ism330dhcx_slv2_config_t::slave2_numop
uint8_t slave2_numop
Definition ism330dhcx_reg.h:2618
ism330dhcx_slv2_config_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2616
ism330dhcx_slv2_config_t::batch_ext_sens_2_en
uint8_t batch_ext_sens_2_en
Definition ism330dhcx_reg.h:2617
ism330dhcx_slv2_subadd_t
Definition ism330dhcx_reg.h:2604
ism330dhcx_slv2_subadd_t::slave2_reg
uint8_t slave2_reg
Definition ism330dhcx_reg.h:2605
ism330dhcx_slv3_add_t
Definition ism330dhcx_reg.h:2624
ism330dhcx_slv3_add_t::slave3_add
uint8_t slave3_add
Definition ism330dhcx_reg.h:2629
ism330dhcx_slv3_add_t::r_3
uint8_t r_3
Definition ism330dhcx_reg.h:2630
ism330dhcx_slv3_config_t
Definition ism330dhcx_reg.h:2642
ism330dhcx_slv3_config_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2648
ism330dhcx_slv3_config_t::slave3_numop
uint8_t slave3_numop
Definition ism330dhcx_reg.h:2650
ism330dhcx_slv3_config_t::batch_ext_sens_3_en
uint8_t batch_ext_sens_3_en
Definition ism330dhcx_reg.h:2649
ism330dhcx_slv3_subadd_t
Definition ism330dhcx_reg.h:2636
ism330dhcx_slv3_subadd_t::slave3_reg
uint8_t slave3_reg
Definition ism330dhcx_reg.h:2637
ism330dhcx_status_master_mainpage_t
Definition ism330dhcx_reg.h:764
ism330dhcx_status_master_mainpage_t::slave0_nack
uint8_t slave0_nack
Definition ism330dhcx_reg.h:778
ism330dhcx_status_master_mainpage_t::wr_once_done
uint8_t wr_once_done
Definition ism330dhcx_reg.h:774
ism330dhcx_status_master_mainpage_t::slave3_nack
uint8_t slave3_nack
Definition ism330dhcx_reg.h:775
ism330dhcx_status_master_mainpage_t::slave1_nack
uint8_t slave1_nack
Definition ism330dhcx_reg.h:777
ism330dhcx_status_master_mainpage_t::sens_hub_endop
uint8_t sens_hub_endop
Definition ism330dhcx_reg.h:780
ism330dhcx_status_master_mainpage_t::slave2_nack
uint8_t slave2_nack
Definition ism330dhcx_reg.h:776
ism330dhcx_status_master_mainpage_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:779
ism330dhcx_status_master_t
Definition ism330dhcx_reg.h:2662
ism330dhcx_status_master_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:2677
ism330dhcx_status_master_t::slave2_nack
uint8_t slave2_nack
Definition ism330dhcx_reg.h:2674
ism330dhcx_status_master_t::sens_hub_endop
uint8_t sens_hub_endop
Definition ism330dhcx_reg.h:2678
ism330dhcx_status_master_t::slave3_nack
uint8_t slave3_nack
Definition ism330dhcx_reg.h:2673
ism330dhcx_status_master_t::wr_once_done
uint8_t wr_once_done
Definition ism330dhcx_reg.h:2672
ism330dhcx_status_master_t::slave1_nack
uint8_t slave1_nack
Definition ism330dhcx_reg.h:2675
ism330dhcx_status_master_t::slave0_nack
uint8_t slave0_nack
Definition ism330dhcx_reg.h:2676
ism330dhcx_status_reg_t
Definition ism330dhcx_reg.h:626
ism330dhcx_status_reg_t::gda
uint8_t gda
Definition ism330dhcx_reg.h:635
ism330dhcx_status_reg_t::tda
uint8_t tda
Definition ism330dhcx_reg.h:634
ism330dhcx_status_reg_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:633
ism330dhcx_status_reg_t::xlda
uint8_t xlda
Definition ism330dhcx_reg.h:636
ism330dhcx_status_spiaux_t
Definition ism330dhcx_reg.h:642
ism330dhcx_status_spiaux_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:649
ism330dhcx_status_spiaux_t::gyro_settling
uint8_t gyro_settling
Definition ism330dhcx_reg.h:650
ism330dhcx_status_spiaux_t::gda
uint8_t gda
Definition ism330dhcx_reg.h:651
ism330dhcx_status_spiaux_t::xlda
uint8_t xlda
Definition ism330dhcx_reg.h:652
ism330dhcx_tap_cfg0_t
Definition ism330dhcx_reg.h:818
ism330dhcx_tap_cfg0_t::int_clr_on_read
uint8_t int_clr_on_read
Definition ism330dhcx_reg.h:830
ism330dhcx_tap_cfg0_t::sleep_status_on_int
uint8_t sleep_status_on_int
Definition ism330dhcx_reg.h:831
ism330dhcx_tap_cfg0_t::lir
uint8_t lir
Definition ism330dhcx_reg.h:836
ism330dhcx_tap_cfg0_t::tap_y_en
uint8_t tap_y_en
Definition ism330dhcx_reg.h:834
ism330dhcx_tap_cfg0_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:829
ism330dhcx_tap_cfg0_t::tap_z_en
uint8_t tap_z_en
Definition ism330dhcx_reg.h:835
ism330dhcx_tap_cfg0_t::slope_fds
uint8_t slope_fds
Definition ism330dhcx_reg.h:832
ism330dhcx_tap_cfg0_t::tap_x_en
uint8_t tap_x_en
Definition ism330dhcx_reg.h:833
ism330dhcx_tap_cfg1_t
Definition ism330dhcx_reg.h:842
ism330dhcx_tap_cfg1_t::tap_ths_x
uint8_t tap_ths_x
Definition ism330dhcx_reg.h:848
ism330dhcx_tap_cfg1_t::tap_priority
uint8_t tap_priority
Definition ism330dhcx_reg.h:847
ism330dhcx_tap_cfg2_t
Definition ism330dhcx_reg.h:854
ism330dhcx_tap_cfg2_t::interrupts_enable
uint8_t interrupts_enable
Definition ism330dhcx_reg.h:860
ism330dhcx_tap_cfg2_t::inact_en
uint8_t inact_en
Definition ism330dhcx_reg.h:861
ism330dhcx_tap_cfg2_t::tap_ths_y
uint8_t tap_ths_y
Definition ism330dhcx_reg.h:862
ism330dhcx_tap_src_t
Definition ism330dhcx_reg.h:578
ism330dhcx_tap_src_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:589
ism330dhcx_tap_src_t::y_tap
uint8_t y_tap
Definition ism330dhcx_reg.h:595
ism330dhcx_tap_src_t::single_tap
uint8_t single_tap
Definition ism330dhcx_reg.h:591
ism330dhcx_tap_src_t::tap_ia
uint8_t tap_ia
Definition ism330dhcx_reg.h:590
ism330dhcx_tap_src_t::tap_sign
uint8_t tap_sign
Definition ism330dhcx_reg.h:593
ism330dhcx_tap_src_t::z_tap
uint8_t z_tap
Definition ism330dhcx_reg.h:596
ism330dhcx_tap_src_t::x_tap
uint8_t x_tap
Definition ism330dhcx_reg.h:594
ism330dhcx_tap_src_t::double_tap
uint8_t double_tap
Definition ism330dhcx_reg.h:592
ism330dhcx_tap_ths_6d_t
Definition ism330dhcx_reg.h:868
ism330dhcx_tap_ths_6d_t::d4d_en
uint8_t d4d_en
Definition ism330dhcx_reg.h:874
ism330dhcx_tap_ths_6d_t::tap_ths_z
uint8_t tap_ths_z
Definition ism330dhcx_reg.h:876
ism330dhcx_tap_ths_6d_t::sixd_ths
uint8_t sixd_ths
Definition ism330dhcx_reg.h:875
ism330dhcx_wake_up_dur_t
Definition ism330dhcx_reg.h:910
ism330dhcx_wake_up_dur_t::wake_dur
uint8_t wake_dur
Definition ism330dhcx_reg.h:918
ism330dhcx_wake_up_dur_t::ff_dur
uint8_t ff_dur
Definition ism330dhcx_reg.h:917
ism330dhcx_wake_up_dur_t::sleep_dur
uint8_t sleep_dur
Definition ism330dhcx_reg.h:920
ism330dhcx_wake_up_dur_t::wake_ths_w
uint8_t wake_ths_w
Definition ism330dhcx_reg.h:919
ism330dhcx_wake_up_src_t
Definition ism330dhcx_reg.h:554
ism330dhcx_wake_up_src_t::x_wu
uint8_t x_wu
Definition ism330dhcx_reg.h:570
ism330dhcx_wake_up_src_t::y_wu
uint8_t y_wu
Definition ism330dhcx_reg.h:571
ism330dhcx_wake_up_src_t::not_used_01
uint8_t not_used_01
Definition ism330dhcx_reg.h:565
ism330dhcx_wake_up_src_t::ff_ia
uint8_t ff_ia
Definition ism330dhcx_reg.h:567
ism330dhcx_wake_up_src_t::sleep_state
uint8_t sleep_state
Definition ism330dhcx_reg.h:568
ism330dhcx_wake_up_src_t::wu_ia
uint8_t wu_ia
Definition ism330dhcx_reg.h:569
ism330dhcx_wake_up_src_t::z_wu
uint8_t z_wu
Definition ism330dhcx_reg.h:572
ism330dhcx_wake_up_src_t::sleep_change_ia
uint8_t sleep_change_ia
Definition ism330dhcx_reg.h:566
ism330dhcx_wake_up_ths_t
Definition ism330dhcx_reg.h:896
ism330dhcx_wake_up_ths_t::usr_off_on_wu
uint8_t usr_off_on_wu
Definition ism330dhcx_reg.h:903
ism330dhcx_wake_up_ths_t::single_double_tap
uint8_t single_double_tap
Definition ism330dhcx_reg.h:902
ism330dhcx_wake_up_ths_t::wk_ths
uint8_t wk_ths
Definition ism330dhcx_reg.h:904
stmdev_ctx_t
Definition ism330dhcx_reg.h:117
stmdev_ctx_t::read_reg
stmdev_read_ptr read_reg
Definition ism330dhcx_reg.h:120
stmdev_ctx_t::write_reg
stmdev_write_ptr write_reg
Component mandatory fields.
Definition ism330dhcx_reg.h:119
stmdev_ctx_t::handle
void * handle
Customizable optional pointer.
Definition ism330dhcx_reg.h:122
ucf_line_t
Definition ism330dhcx_reg.h:147
ucf_line_t::address
uint8_t address
Definition ism330dhcx_reg.h:148
ucf_line_t::data
uint8_t data
Definition ism330dhcx_reg.h:149
ism330dhcx_reg_t
Definition ism330dhcx_reg.h:2695
ism330dhcx_reg_t::int_dur2
ism330dhcx_int_dur2_t int_dur2
Definition ism330dhcx_reg.h:2728
ism330dhcx_reg_t::slv3_add
ism330dhcx_slv3_add_t slv3_add
Definition ism330dhcx_reg.h:2811
ism330dhcx_reg_t::datawrite_slv0
ism330dhcx_datawrite_slv0_t datawrite_slv0
Definition ism330dhcx_reg.h:2814
ism330dhcx_reg_t::sensor_hub_17
ism330dhcx_sensor_hub_17_t sensor_hub_17
Definition ism330dhcx_reg.h:2799
ism330dhcx_reg_t::sensor_hub_11
ism330dhcx_sensor_hub_11_t sensor_hub_11
Definition ism330dhcx_reg.h:2793
ism330dhcx_reg_t::slv2_add
ism330dhcx_slv2_add_t slv2_add
Definition ism330dhcx_reg.h:2808
ism330dhcx_reg_t::emb_func_status
ism330dhcx_emb_func_status_t emb_func_status
Definition ism330dhcx_reg.h:2751
ism330dhcx_reg_t::slv0_config
ism330dhcx_slv0_config_t slv0_config
Definition ism330dhcx_reg.h:2804
ism330dhcx_reg_t::int1_ctrl
ism330dhcx_int1_ctrl_t int1_ctrl
Definition ism330dhcx_reg.h:2704
ism330dhcx_reg_t::byte
uint8_t byte
Definition ism330dhcx_reg.h:2817
ism330dhcx_reg_t::fsm_status_b
ism330dhcx_fsm_status_b_t fsm_status_b
Definition ism330dhcx_reg.h:2753
ism330dhcx_reg_t::slv2_config
ism330dhcx_slv2_config_t slv2_config
Definition ism330dhcx_reg.h:2810
ism330dhcx_reg_t::wake_up_ths
ism330dhcx_wake_up_ths_t wake_up_ths
Definition ism330dhcx_reg.h:2729
ism330dhcx_reg_t::emb_func_odr_cfg_b
ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b
Definition ism330dhcx_reg.h:2775
ism330dhcx_reg_t::slv0_subadd
ism330dhcx_slv0_subadd_t slv0_subadd
Definition ism330dhcx_reg.h:2803
ism330dhcx_reg_t::sensor_hub_4
ism330dhcx_sensor_hub_4_t sensor_hub_4
Definition ism330dhcx_reg.h:2786
ism330dhcx_reg_t::ctrl9_xl
ism330dhcx_ctrl9_xl_t ctrl9_xl
Definition ism330dhcx_reg.h:2714
ism330dhcx_reg_t::fsm_outs14
ism330dhcx_fsm_outs14_t fsm_outs14
Definition ism330dhcx_reg.h:2772
ism330dhcx_reg_t::ctrl2_g
ism330dhcx_ctrl2_g_t ctrl2_g
Definition ism330dhcx_reg.h:2707
ism330dhcx_reg_t::fsm_int1_b
ism330dhcx_fsm_int1_b_t fsm_int1_b
Definition ism330dhcx_reg.h:2747
ism330dhcx_reg_t::fifo_ctrl4
ism330dhcx_fifo_ctrl4_t fifo_ctrl4
Definition ism330dhcx_reg.h:2701
ism330dhcx_reg_t::func_cfg_access
ism330dhcx_func_cfg_access_t func_cfg_access
Definition ism330dhcx_reg.h:2696
ism330dhcx_reg_t::fsm_outs11
ism330dhcx_fsm_outs11_t fsm_outs11
Definition ism330dhcx_reg.h:2769
ism330dhcx_reg_t::slv3_config
ism330dhcx_slv3_config_t slv3_config
Definition ism330dhcx_reg.h:2813
ism330dhcx_reg_t::page_address
ism330dhcx_page_address_t page_address
Definition ism330dhcx_reg.h:2743
ism330dhcx_reg_t::page_value
ism330dhcx_page_value_t page_value
Definition ism330dhcx_reg.h:2744
ism330dhcx_reg_t::sensor_hub_2
ism330dhcx_sensor_hub_2_t sensor_hub_2
Definition ism330dhcx_reg.h:2784
ism330dhcx_reg_t::sensor_hub_18
ism330dhcx_sensor_hub_18_t sensor_hub_18
Definition ism330dhcx_reg.h:2800
ism330dhcx_reg_t::ctrl6_c
ism330dhcx_ctrl6_c_t ctrl6_c
Definition ism330dhcx_reg.h:2711
ism330dhcx_reg_t::internal_freq_fine
ism330dhcx_internal_freq_fine_t internal_freq_fine
Definition ism330dhcx_reg.h:2734
ism330dhcx_reg_t::mag_cfg_b
ism330dhcx_mag_cfg_b_t mag_cfg_b
Definition ism330dhcx_reg.h:2781
ism330dhcx_reg_t::fsm_outs7
ism330dhcx_fsm_outs7_t fsm_outs7
Definition ism330dhcx_reg.h:2765
ism330dhcx_reg_t::int2_ctrl
ism330dhcx_int2_ctrl_t int2_ctrl
Definition ism330dhcx_reg.h:2705
ism330dhcx_reg_t::fifo_status1
ism330dhcx_fifo_status1_t fifo_status1
Definition ism330dhcx_reg.h:2722
ism330dhcx_reg_t::counter_bdr_reg1
ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1
Definition ism330dhcx_reg.h:2702
ism330dhcx_reg_t::status_reg
ism330dhcx_status_reg_t status_reg
Definition ism330dhcx_reg.h:2720
ism330dhcx_reg_t::slv1_subadd
ism330dhcx_slv1_subadd_t slv1_subadd
Definition ism330dhcx_reg.h:2806
ism330dhcx_reg_t::ctrl2_ois
ism330dhcx_ctrl2_ois_t ctrl2_ois
Definition ism330dhcx_reg.h:2737
ism330dhcx_reg_t::status_spiaux
ism330dhcx_status_spiaux_t status_spiaux
Definition ism330dhcx_reg.h:2721
ism330dhcx_reg_t::fsm_outs8
ism330dhcx_fsm_outs8_t fsm_outs8
Definition ism330dhcx_reg.h:2766
ism330dhcx_reg_t::ctrl5_c
ism330dhcx_ctrl5_c_t ctrl5_c
Definition ism330dhcx_reg.h:2710
ism330dhcx_reg_t::fsm_int2_b
ism330dhcx_fsm_int2_b_t fsm_int2_b
Definition ism330dhcx_reg.h:2750
ism330dhcx_reg_t::sensor_hub_3
ism330dhcx_sensor_hub_3_t sensor_hub_3
Definition ism330dhcx_reg.h:2785
ism330dhcx_reg_t::emb_func_int2
ism330dhcx_emb_func_int2_t emb_func_int2
Definition ism330dhcx_reg.h:2748
ism330dhcx_reg_t::sensor_hub_14
ism330dhcx_sensor_hub_14_t sensor_hub_14
Definition ism330dhcx_reg.h:2796
ism330dhcx_reg_t::fsm_enable_a
ism330dhcx_fsm_enable_a_t fsm_enable_a
Definition ism330dhcx_reg.h:2756
ism330dhcx_reg_t::emb_func_src
ism330dhcx_emb_func_src_t emb_func_src
Definition ism330dhcx_reg.h:2777
ism330dhcx_reg_t::sensor_hub_12
ism330dhcx_sensor_hub_12_t sensor_hub_12
Definition ism330dhcx_reg.h:2794
ism330dhcx_reg_t::fsm_outs4
ism330dhcx_fsm_outs4_t fsm_outs4
Definition ism330dhcx_reg.h:2762
ism330dhcx_reg_t::ctrl10_c
ism330dhcx_ctrl10_c_t ctrl10_c
Definition ism330dhcx_reg.h:2715
ism330dhcx_reg_t::fsm_outs12
ism330dhcx_fsm_outs12_t fsm_outs12
Definition ism330dhcx_reg.h:2770
ism330dhcx_reg_t::sensor_hub_16
ism330dhcx_sensor_hub_16_t sensor_hub_16
Definition ism330dhcx_reg.h:2798
ism330dhcx_reg_t::wake_up_dur
ism330dhcx_wake_up_dur_t wake_up_dur
Definition ism330dhcx_reg.h:2730
ism330dhcx_reg_t::ctrl3_ois
ism330dhcx_ctrl3_ois_t ctrl3_ois
Definition ism330dhcx_reg.h:2738
ism330dhcx_reg_t::fifo_data_out_tag
ism330dhcx_fifo_data_out_tag_t fifo_data_out_tag
Definition ism330dhcx_reg.h:2739
ism330dhcx_reg_t::emb_func_fifo_cfg
ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg
Definition ism330dhcx_reg.h:2755
ism330dhcx_reg_t::ctrl3_c
ism330dhcx_ctrl3_c_t ctrl3_c
Definition ism330dhcx_reg.h:2708
ism330dhcx_reg_t::tap_cfg1
ism330dhcx_tap_cfg1_t tap_cfg1
Definition ism330dhcx_reg.h:2725
ism330dhcx_reg_t::tap_cfg2
ism330dhcx_tap_cfg2_t tap_cfg2
Definition ism330dhcx_reg.h:2726
ism330dhcx_reg_t::fsm_outs2
ism330dhcx_fsm_outs2_t fsm_outs2
Definition ism330dhcx_reg.h:2760
ism330dhcx_reg_t::int_ois
ism330dhcx_int_ois_t int_ois
Definition ism330dhcx_reg.h:2735
ism330dhcx_reg_t::free_fall
ism330dhcx_free_fall_t free_fall
Definition ism330dhcx_reg.h:2731
ism330dhcx_reg_t::fsm_int2_a
ism330dhcx_fsm_int2_a_t fsm_int2_a
Definition ism330dhcx_reg.h:2749
ism330dhcx_reg_t::fifo_ctrl3
ism330dhcx_fifo_ctrl3_t fifo_ctrl3
Definition ism330dhcx_reg.h:2700
ism330dhcx_reg_t::fsm_outs9
ism330dhcx_fsm_outs9_t fsm_outs9
Definition ism330dhcx_reg.h:2767
ism330dhcx_reg_t::wake_up_src
ism330dhcx_wake_up_src_t wake_up_src
Definition ism330dhcx_reg.h:2717
ism330dhcx_reg_t::ctrl1_ois
ism330dhcx_ctrl1_ois_t ctrl1_ois
Definition ism330dhcx_reg.h:2736
ism330dhcx_reg_t::slv0_add
ism330dhcx_slv0_add_t slv0_add
Definition ism330dhcx_reg.h:2802
ism330dhcx_reg_t::ctrl8_xl
ism330dhcx_ctrl8_xl_t ctrl8_xl
Definition ism330dhcx_reg.h:2713
ism330dhcx_reg_t::sensor_hub_5
ism330dhcx_sensor_hub_5_t sensor_hub_5
Definition ism330dhcx_reg.h:2787
ism330dhcx_reg_t::page_sel
ism330dhcx_page_sel_t page_sel
Definition ism330dhcx_reg.h:2740
ism330dhcx_reg_t::emb_func_int1
ism330dhcx_emb_func_int1_t emb_func_int1
Definition ism330dhcx_reg.h:2745
ism330dhcx_reg_t::fifo_ctrl1
ism330dhcx_fifo_ctrl1_t fifo_ctrl1
Definition ism330dhcx_reg.h:2698
ism330dhcx_reg_t::sensor_hub_15
ism330dhcx_sensor_hub_15_t sensor_hub_15
Definition ism330dhcx_reg.h:2797
ism330dhcx_reg_t::fsm_outs10
ism330dhcx_fsm_outs10_t fsm_outs10
Definition ism330dhcx_reg.h:2768
ism330dhcx_reg_t::emb_func_init_b
ism330dhcx_emb_func_init_b_t emb_func_init_b
Definition ism330dhcx_reg.h:2779
ism330dhcx_reg_t::fsm_outs5
ism330dhcx_fsm_outs5_t fsm_outs5
Definition ism330dhcx_reg.h:2763
ism330dhcx_reg_t::fsm_outs15
ism330dhcx_fsm_outs15_t fsm_outs15
Definition ism330dhcx_reg.h:2773
ism330dhcx_reg_t::sensor_hub_8
ism330dhcx_sensor_hub_8_t sensor_hub_8
Definition ism330dhcx_reg.h:2790
ism330dhcx_reg_t::fifo_status2
ism330dhcx_fifo_status2_t fifo_status2
Definition ism330dhcx_reg.h:2723
ism330dhcx_reg_t::fsm_outs6
ism330dhcx_fsm_outs6_t fsm_outs6
Definition ism330dhcx_reg.h:2764
ism330dhcx_reg_t::md1_cfg
ism330dhcx_md1_cfg_t md1_cfg
Definition ism330dhcx_reg.h:2732
ism330dhcx_reg_t::slv3_subadd
ism330dhcx_slv3_subadd_t slv3_subadd
Definition ism330dhcx_reg.h:2812
ism330dhcx_reg_t::tap_src
ism330dhcx_tap_src_t tap_src
Definition ism330dhcx_reg.h:2718
ism330dhcx_reg_t::page_rw
ism330dhcx_page_rw_t page_rw
Definition ism330dhcx_reg.h:2754
ism330dhcx_reg_t::tap_ths_6d
ism330dhcx_tap_ths_6d_t tap_ths_6d
Definition ism330dhcx_reg.h:2727
ism330dhcx_reg_t::md2_cfg
ism330dhcx_md2_cfg_t md2_cfg
Definition ism330dhcx_reg.h:2733
ism330dhcx_reg_t::d6d_src
ism330dhcx_d6d_src_t d6d_src
Definition ism330dhcx_reg.h:2719
ism330dhcx_reg_t::fsm_status_a
ism330dhcx_fsm_status_a_t fsm_status_a
Definition ism330dhcx_reg.h:2752
ism330dhcx_reg_t::fsm_outs1
ism330dhcx_fsm_outs1_t fsm_outs1
Definition ism330dhcx_reg.h:2759
ism330dhcx_reg_t::sensor_hub_1
ism330dhcx_sensor_hub_1_t sensor_hub_1
Definition ism330dhcx_reg.h:2783
ism330dhcx_reg_t::fsm_outs13
ism330dhcx_fsm_outs13_t fsm_outs13
Definition ism330dhcx_reg.h:2771
ism330dhcx_reg_t::sensor_hub_10
ism330dhcx_sensor_hub_10_t sensor_hub_10
Definition ism330dhcx_reg.h:2792
ism330dhcx_reg_t::slv1_config
ism330dhcx_slv1_config_t slv1_config
Definition ism330dhcx_reg.h:2807
ism330dhcx_reg_t::tap_cfg0
ism330dhcx_tap_cfg0_t tap_cfg0
Definition ism330dhcx_reg.h:2724
ism330dhcx_reg_t::ctrl1_xl
ism330dhcx_ctrl1_xl_t ctrl1_xl
Definition ism330dhcx_reg.h:2706
ism330dhcx_reg_t::pin_ctrl
ism330dhcx_pin_ctrl_t pin_ctrl
Definition ism330dhcx_reg.h:2697
ism330dhcx_reg_t::fsm_enable_b
ism330dhcx_fsm_enable_b_t fsm_enable_b
Definition ism330dhcx_reg.h:2757
ism330dhcx_reg_t::emb_func_en_b
ism330dhcx_emb_func_en_b_t emb_func_en_b
Definition ism330dhcx_reg.h:2742
ism330dhcx_reg_t::master_config
ism330dhcx_master_config_t master_config
Definition ism330dhcx_reg.h:2801
ism330dhcx_reg_t::ctrl7_g
ism330dhcx_ctrl7_g_t ctrl7_g
Definition ism330dhcx_reg.h:2712
ism330dhcx_reg_t::emb_func_odr_cfg_c_t
ism330dhcx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c_t
Definition ism330dhcx_reg.h:2776
ism330dhcx_reg_t::fsm_long_counter_clear
ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear
Definition ism330dhcx_reg.h:2758
ism330dhcx_reg_t::fsm_int1_a
ism330dhcx_fsm_int1_a_t fsm_int1_a
Definition ism330dhcx_reg.h:2746
ism330dhcx_reg_t::sensor_hub_6
ism330dhcx_sensor_hub_6_t sensor_hub_6
Definition ism330dhcx_reg.h:2788
ism330dhcx_reg_t::sensor_hub_7
ism330dhcx_sensor_hub_7_t sensor_hub_7
Definition ism330dhcx_reg.h:2789
ism330dhcx_reg_t::sensor_hub_9
ism330dhcx_sensor_hub_9_t sensor_hub_9
Definition ism330dhcx_reg.h:2791
ism330dhcx_reg_t::fifo_ctrl2
ism330dhcx_fifo_ctrl2_t fifo_ctrl2
Definition ism330dhcx_reg.h:2699
ism330dhcx_reg_t::mag_cfg_a
ism330dhcx_mag_cfg_a_t mag_cfg_a
Definition ism330dhcx_reg.h:2780
ism330dhcx_reg_t::ctrl4_c
ism330dhcx_ctrl4_c_t ctrl4_c
Definition ism330dhcx_reg.h:2709
ism330dhcx_reg_t::slv2_subadd
ism330dhcx_slv2_subadd_t slv2_subadd
Definition ism330dhcx_reg.h:2809
ism330dhcx_reg_t::all_int_src
ism330dhcx_all_int_src_t all_int_src
Definition ism330dhcx_reg.h:2716
ism330dhcx_reg_t::pedo_cmd_reg
ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg
Definition ism330dhcx_reg.h:2782
ism330dhcx_reg_t::slv1_add
ism330dhcx_slv1_add_t slv1_add
Definition ism330dhcx_reg.h:2805
ism330dhcx_reg_t::fsm_outs3
ism330dhcx_fsm_outs3_t fsm_outs3
Definition ism330dhcx_reg.h:2761
ism330dhcx_reg_t::emb_func_en_a
ism330dhcx_emb_func_en_a_t emb_func_en_a
Definition ism330dhcx_reg.h:2741
ism330dhcx_reg_t::status_master
ism330dhcx_status_master_t status_master
Definition ism330dhcx_reg.h:2815
ism330dhcx_reg_t::sensor_hub_13
ism330dhcx_sensor_hub_13_t sensor_hub_13
Definition ism330dhcx_reg.h:2795
ism330dhcx_reg_t::bitwise
bitwise_t bitwise
Definition ism330dhcx_reg.h:2816
ism330dhcx_reg_t::fsm_outs16
ism330dhcx_fsm_outs16_t fsm_outs16
Definition ism330dhcx_reg.h:2774
ism330dhcx_reg_t::emb_func_init_a
ism330dhcx_emb_func_init_a_t emb_func_init_a
Definition ism330dhcx_reg.h:2778
ism330dhcx_reg_t::counter_bdr_reg2
ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2
Definition ism330dhcx_reg.h:2703