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mpu_armv7.h File Reference
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Classes

struct  ARM_MPU_Region_t
 Struct for a single MPU Region. More...

Macros

#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B   ((uint8_t)0x04U)
#define ARM_MPU_REGION_SIZE_64B   ((uint8_t)0x05U)
#define ARM_MPU_REGION_SIZE_128B   ((uint8_t)0x06U)
#define ARM_MPU_REGION_SIZE_256B   ((uint8_t)0x07U)
#define ARM_MPU_REGION_SIZE_512B   ((uint8_t)0x08U)
#define ARM_MPU_REGION_SIZE_1KB   ((uint8_t)0x09U)
#define ARM_MPU_REGION_SIZE_2KB   ((uint8_t)0x0AU)
#define ARM_MPU_REGION_SIZE_4KB   ((uint8_t)0x0BU)
#define ARM_MPU_REGION_SIZE_8KB   ((uint8_t)0x0CU)
#define ARM_MPU_REGION_SIZE_16KB   ((uint8_t)0x0DU)
#define ARM_MPU_REGION_SIZE_32KB   ((uint8_t)0x0EU)
#define ARM_MPU_REGION_SIZE_64KB   ((uint8_t)0x0FU)
#define ARM_MPU_REGION_SIZE_128KB   ((uint8_t)0x10U)
#define ARM_MPU_REGION_SIZE_256KB   ((uint8_t)0x11U)
#define ARM_MPU_REGION_SIZE_512KB   ((uint8_t)0x12U)
#define ARM_MPU_REGION_SIZE_1MB   ((uint8_t)0x13U)
#define ARM_MPU_REGION_SIZE_2MB   ((uint8_t)0x14U)
#define ARM_MPU_REGION_SIZE_4MB   ((uint8_t)0x15U)
#define ARM_MPU_REGION_SIZE_8MB   ((uint8_t)0x16U)
#define ARM_MPU_REGION_SIZE_16MB   ((uint8_t)0x17U)
#define ARM_MPU_REGION_SIZE_32MB   ((uint8_t)0x18U)
#define ARM_MPU_REGION_SIZE_64MB   ((uint8_t)0x19U)
#define ARM_MPU_REGION_SIZE_128MB   ((uint8_t)0x1AU)
#define ARM_MPU_REGION_SIZE_256MB   ((uint8_t)0x1BU)
#define ARM_MPU_REGION_SIZE_512MB   ((uint8_t)0x1CU)
#define ARM_MPU_REGION_SIZE_1GB   ((uint8_t)0x1DU)
#define ARM_MPU_REGION_SIZE_2GB   ((uint8_t)0x1EU)
#define ARM_MPU_REGION_SIZE_4GB   ((uint8_t)0x1FU)
#define ARM_MPU_AP_NONE   0U
#define ARM_MPU_AP_PRIV   1U
#define ARM_MPU_AP_URO   2U
#define ARM_MPU_AP_FULL   3U
#define ARM_MPU_AP_PRO   5U
#define ARM_MPU_AP_RO   6U
#define ARM_MPU_RBAR(Region, BaseAddress)
 MPU Region Base Address Register Value.
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)
 MPU Memory Access Attributes.
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)
 MPU Region Attribute and Size Register Value.
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
 MPU Region Attribute and Size Register Value.
#define ARM_MPU_ACCESS_ORDERED   ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
 MPU Memory Access Attribute for strongly ordered memory.
#define ARM_MPU_ACCESS_DEVICE(IsShareable)
 MPU Memory Access Attribute for device memory.
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable)
 MPU Memory Access Attribute for normal memory.
#define ARM_MPU_CACHEP_NOCACHE   0U
 MPU Memory Access Attribute non-cacheable policy.
#define ARM_MPU_CACHEP_WB_WRA   1U
 MPU Memory Access Attribute write-back, write and read allocate policy.
#define ARM_MPU_CACHEP_WT_NWA   2U
 MPU Memory Access Attribute write-through, no write allocate policy.
#define ARM_MPU_CACHEP_WB_NWA   3U
 MPU Memory Access Attribute write-back, no write allocate policy.

Functions

__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_Control)
 Enable the MPU.
__STATIC_INLINE void ARM_MPU_Disable (void)
 Disable the MPU.
__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
 Clear and disable the given MPU region.
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rbar, uint32_t rasr)
 Configure an MPU region.
__STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr, uint32_t rbar, uint32_t rasr)
 Configure the given MPU region.
__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
 Memcpy with strictly ordered memory access, e.g.
__STATIC_INLINE void ARM_MPU_Load (ARM_MPU_Region_t const *table, uint32_t cnt)
 Load the given number of MPU regions from a table.

Macro Definition Documentation

◆ ARM_MPU_ACCESS_

#define ARM_MPU_ACCESS_ ( TypeExtField,
IsShareable,
IsCacheable,
IsBufferable )
Value:
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
MPU_RASR_S_Pos
#define MPU_RASR_S_Pos
MPU RASR: ATTRS.S Position.
Definition core_cm0plus.h:582
MPU_RASR_TEX_Pos
#define MPU_RASR_TEX_Pos
MPU RASR: ATTRS.TEX Position.
Definition core_cm0plus.h:579
MPU_RASR_C_Pos
#define MPU_RASR_C_Pos
MPU RASR: ATTRS.C Position.
Definition core_cm0plus.h:585
MPU_RASR_S_Msk
#define MPU_RASR_S_Msk
MPU RASR: ATTRS.S Mask.
Definition core_cm0plus.h:583
MPU_RASR_TEX_Msk
#define MPU_RASR_TEX_Msk
MPU RASR: ATTRS.TEX Mask.
Definition core_cm0plus.h:580
MPU_RASR_B_Pos
#define MPU_RASR_B_Pos
MPU RASR: ATTRS.B Position.
Definition core_cm0plus.h:588
MPU_RASR_C_Msk
#define MPU_RASR_C_Msk
MPU RASR: ATTRS.C Mask.
Definition core_cm0plus.h:586
MPU_RASR_B_Msk
#define MPU_RASR_B_Msk
MPU RASR: ATTRS.B Mask.
Definition core_cm0plus.h:589

MPU Memory Access Attributes.

Parameters
TypeExtFieldType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
IsShareableRegion is shareable between multiple bus masters.
IsCacheableRegion is cacheable, i.e. its value may be kept in cache.
IsBufferableRegion is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.

Definition at line 88 of file mpu_armv7.h.

◆ ARM_MPU_ACCESS_DEVICE

#define ARM_MPU_ACCESS_DEVICE ( IsShareable)
Value:
((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
ARM_MPU_ACCESS_
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)
MPU Memory Access Attributes.
Definition mpu_armv7.h:88

MPU Memory Access Attribute for device memory.

  • TEX: 000b (if shareable) or 010b (if non-shareable)
  • Shareable or non-shareable
  • Non-cacheable
  • Bufferable (if shareable) or non-bufferable (if non-shareable)
Parameters
IsShareableConfigures the device memory as shareable or non-shareable.

Definition at line 144 of file mpu_armv7.h.

◆ ARM_MPU_ACCESS_NORMAL

#define ARM_MPU_ACCESS_NORMAL ( OuterCp,
InnerCp,
IsShareable )
Value:
ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))

MPU Memory Access Attribute for normal memory.

  • TEX: 1BBb (reflecting outer cacheability rules)
  • Shareable or non-shareable
  • Cacheable or non-cacheable (reflecting inner cacheability rules)
  • Bufferable or non-bufferable (reflecting inner cacheability rules)
Parameters
OuterCpConfigures the outer cache policy.
InnerCpConfigures the inner cache policy.
IsShareableConfigures the memory as shareable or non-shareable.

Definition at line 157 of file mpu_armv7.h.

◆ ARM_MPU_ACCESS_ORDERED

#define ARM_MPU_ACCESS_ORDERED   ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)

MPU Memory Access Attribute for strongly ordered memory.

  • TEX: 000b
  • Shareable
  • Non-cacheable
  • Non-bufferable

Definition at line 133 of file mpu_armv7.h.

◆ ARM_MPU_AP_FULL

#define ARM_MPU_AP_FULL   3U

Definition at line 66 of file mpu_armv7.h.

◆ ARM_MPU_AP_NONE

#define ARM_MPU_AP_NONE   0U

Definition at line 63 of file mpu_armv7.h.

◆ ARM_MPU_AP_PRIV

#define ARM_MPU_AP_PRIV   1U

Definition at line 64 of file mpu_armv7.h.

◆ ARM_MPU_AP_PRO

#define ARM_MPU_AP_PRO   5U

Definition at line 67 of file mpu_armv7.h.

◆ ARM_MPU_AP_RO

#define ARM_MPU_AP_RO   6U

Definition at line 68 of file mpu_armv7.h.

◆ ARM_MPU_AP_URO

#define ARM_MPU_AP_URO   2U

Definition at line 65 of file mpu_armv7.h.

◆ ARM_MPU_ARMV7_H

#define ARM_MPU_ARMV7_H

Definition at line 32 of file mpu_armv7.h.

◆ ARM_MPU_CACHEP_NOCACHE

#define ARM_MPU_CACHEP_NOCACHE   0U

MPU Memory Access Attribute non-cacheable policy.

Definition at line 162 of file mpu_armv7.h.

◆ ARM_MPU_CACHEP_WB_NWA

#define ARM_MPU_CACHEP_WB_NWA   3U

MPU Memory Access Attribute write-back, no write allocate policy.

Definition at line 177 of file mpu_armv7.h.

◆ ARM_MPU_CACHEP_WB_WRA

#define ARM_MPU_CACHEP_WB_WRA   1U

MPU Memory Access Attribute write-back, write and read allocate policy.

Definition at line 167 of file mpu_armv7.h.

◆ ARM_MPU_CACHEP_WT_NWA

#define ARM_MPU_CACHEP_WT_NWA   2U

MPU Memory Access Attribute write-through, no write allocate policy.

Definition at line 172 of file mpu_armv7.h.

◆ ARM_MPU_RASR

#define ARM_MPU_RASR ( DisableExec,
AccessPermission,
TypeExtField,
IsShareable,
IsCacheable,
IsBufferable,
SubRegionDisable,
Size )
Value:
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
ARM_MPU_RASR_EX
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)
MPU Region Attribute and Size Register Value.
Definition mpu_armv7.h:103

MPU Region Attribute and Size Register Value.

Parameters
DisableExecInstruction access disable bit, 1= disable instruction fetches.
AccessPermissionData access permissions, allows you to configure read/write access for User and Privileged mode.
TypeExtFieldType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
IsShareableRegion is shareable between multiple bus masters.
IsCacheableRegion is cacheable, i.e. its value may be kept in cache.
IsBufferableRegion is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
SubRegionDisableSub-region disable field.
SizeRegion size of the region to be configured, for example 4K, 8K.

Definition at line 123 of file mpu_armv7.h.

◆ ARM_MPU_RASR_EX

#define ARM_MPU_RASR_EX ( DisableExec,
AccessPermission,
AccessAttributes,
SubRegionDisable,
Size )
Value:
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
MPU_RASR_SIZE_Msk
#define MPU_RASR_SIZE_Msk
MPU RASR: Region Size Field Mask.
Definition core_cm0plus.h:595
MPU_RASR_SRD_Msk
#define MPU_RASR_SRD_Msk
MPU RASR: Sub-Region Disable Mask.
Definition core_cm0plus.h:592
MPU_RASR_XN_Msk
#define MPU_RASR_XN_Msk
MPU RASR: ATTRS.XN Mask.
Definition core_cm0plus.h:574
MPU_RASR_AP_Msk
#define MPU_RASR_AP_Msk
MPU RASR: ATTRS.AP Mask.
Definition core_cm0plus.h:577
MPU_RASR_XN_Pos
#define MPU_RASR_XN_Pos
MPU RASR: ATTRS.XN Position.
Definition core_cm0plus.h:573
MPU_RASR_AP_Pos
#define MPU_RASR_AP_Pos
MPU RASR: ATTRS.AP Position.
Definition core_cm0plus.h:576
MPU_RASR_SIZE_Pos
#define MPU_RASR_SIZE_Pos
MPU RASR: Region Size Field Position.
Definition core_cm0plus.h:594
MPU_RASR_SRD_Pos
#define MPU_RASR_SRD_Pos
MPU RASR: Sub-Region Disable Position.
Definition core_cm0plus.h:591
MPU_RASR_ENABLE_Msk
#define MPU_RASR_ENABLE_Msk
MPU RASR: Region enable bit Disable Mask.
Definition core_cm0plus.h:598

MPU Region Attribute and Size Register Value.

Parameters
DisableExecInstruction access disable bit, 1= disable instruction fetches.
AccessPermissionData access permissions, allows you to configure read/write access for User and Privileged mode.
AccessAttributesMemory access attribution, see ARM_MPU_ACCESS_.
SubRegionDisableSub-region disable field.
SizeRegion size of the region to be configured, for example 4K, 8K.

Definition at line 103 of file mpu_armv7.h.

◆ ARM_MPU_RBAR

#define ARM_MPU_RBAR ( Region,
BaseAddress )
Value:
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
MPU_RBAR_ADDR_Msk
#define MPU_RBAR_ADDR_Msk
MPU RBAR: ADDR Mask.
Definition core_cm0plus.h:561
MPU_RBAR_REGION_Msk
#define MPU_RBAR_REGION_Msk
MPU RBAR: REGION Mask.
Definition core_cm0plus.h:567
MPU_RBAR_VALID_Msk
#define MPU_RBAR_VALID_Msk
MPU RBAR: VALID Mask.
Definition core_cm0plus.h:564

MPU Region Base Address Register Value.

Parameters
RegionThe region to be configured, number 0 to 15.
BaseAddressThe base address for the region.

Definition at line 75 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_128B

#define ARM_MPU_REGION_SIZE_128B   ((uint8_t)0x06U)

Definition at line 36 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_128KB

#define ARM_MPU_REGION_SIZE_128KB   ((uint8_t)0x10U)

Definition at line 46 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_128MB

#define ARM_MPU_REGION_SIZE_128MB   ((uint8_t)0x1AU)

Definition at line 56 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_16KB

#define ARM_MPU_REGION_SIZE_16KB   ((uint8_t)0x0DU)

Definition at line 43 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_16MB

#define ARM_MPU_REGION_SIZE_16MB   ((uint8_t)0x17U)

Definition at line 53 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_1GB

#define ARM_MPU_REGION_SIZE_1GB   ((uint8_t)0x1DU)

Definition at line 59 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_1KB

#define ARM_MPU_REGION_SIZE_1KB   ((uint8_t)0x09U)

Definition at line 39 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_1MB

#define ARM_MPU_REGION_SIZE_1MB   ((uint8_t)0x13U)

Definition at line 49 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_256B

#define ARM_MPU_REGION_SIZE_256B   ((uint8_t)0x07U)

Definition at line 37 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_256KB

#define ARM_MPU_REGION_SIZE_256KB   ((uint8_t)0x11U)

Definition at line 47 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_256MB

#define ARM_MPU_REGION_SIZE_256MB   ((uint8_t)0x1BU)

Definition at line 57 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_2GB

#define ARM_MPU_REGION_SIZE_2GB   ((uint8_t)0x1EU)

Definition at line 60 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_2KB

#define ARM_MPU_REGION_SIZE_2KB   ((uint8_t)0x0AU)

Definition at line 40 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_2MB

#define ARM_MPU_REGION_SIZE_2MB   ((uint8_t)0x14U)

Definition at line 50 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_32B

#define ARM_MPU_REGION_SIZE_32B   ((uint8_t)0x04U)

Definition at line 34 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_32KB

#define ARM_MPU_REGION_SIZE_32KB   ((uint8_t)0x0EU)

Definition at line 44 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_32MB

#define ARM_MPU_REGION_SIZE_32MB   ((uint8_t)0x18U)

Definition at line 54 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_4GB

#define ARM_MPU_REGION_SIZE_4GB   ((uint8_t)0x1FU)

Definition at line 61 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_4KB

#define ARM_MPU_REGION_SIZE_4KB   ((uint8_t)0x0BU)

Definition at line 41 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_4MB

#define ARM_MPU_REGION_SIZE_4MB   ((uint8_t)0x15U)

Definition at line 51 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_512B

#define ARM_MPU_REGION_SIZE_512B   ((uint8_t)0x08U)

Definition at line 38 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_512KB

#define ARM_MPU_REGION_SIZE_512KB   ((uint8_t)0x12U)

Definition at line 48 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_512MB

#define ARM_MPU_REGION_SIZE_512MB   ((uint8_t)0x1CU)

Definition at line 58 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_64B

#define ARM_MPU_REGION_SIZE_64B   ((uint8_t)0x05U)

Definition at line 35 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_64KB

#define ARM_MPU_REGION_SIZE_64KB   ((uint8_t)0x0FU)

Definition at line 45 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_64MB

#define ARM_MPU_REGION_SIZE_64MB   ((uint8_t)0x19U)

Definition at line 55 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_8KB

#define ARM_MPU_REGION_SIZE_8KB   ((uint8_t)0x0CU)

Definition at line 42 of file mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_8MB

#define ARM_MPU_REGION_SIZE_8MB   ((uint8_t)0x16U)

Definition at line 52 of file mpu_armv7.h.

Function Documentation

◆ ARM_MPU_ClrRegion()

__STATIC_INLINE void ARM_MPU_ClrRegion ( uint32_t rnr)

Clear and disable the given MPU region.

Parameters
rnrRegion number to be cleared.

Definition at line 218 of file mpu_armv7.h.

References __STATIC_INLINE, and MPU.

◆ ARM_MPU_Disable()

__STATIC_INLINE void ARM_MPU_Disable ( void )

Disable the MPU.

Definition at line 204 of file mpu_armv7.h.

References __DMB, __DSB, __ISB, __STATIC_INLINE, MPU, MPU_CTRL_ENABLE_Msk, SCB, and SCB_SHCSR_MEMFAULTENA_Msk.

◆ ARM_MPU_Enable()

__STATIC_INLINE void ARM_MPU_Enable ( uint32_t MPU_Control)

Enable the MPU.

Parameters
MPU_ControlDefault access permissions for unconfigured regions.

Definition at line 191 of file mpu_armv7.h.

References __DMB, __DSB, __ISB, __STATIC_INLINE, MPU, MPU_CTRL_ENABLE_Msk, SCB, and SCB_SHCSR_MEMFAULTENA_Msk.

◆ ARM_MPU_Load()

__STATIC_INLINE void ARM_MPU_Load ( ARM_MPU_Region_t const * table,
uint32_t cnt )

Load the given number of MPU regions from a table.

Parameters
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.

Definition at line 264 of file mpu_armv7.h.

References __STATIC_INLINE, ARM_MPU_OrderedMemcpy(), MPU, and MPU_TYPE_RALIASES.

◆ ARM_MPU_OrderedMemcpy()

__STATIC_INLINE void ARM_MPU_OrderedMemcpy ( volatile uint32_t * dst,
const uint32_t *__RESTRICT src,
uint32_t len )

Memcpy with strictly ordered memory access, e.g.

used by code in ARM_MPU_Load().

Parameters
dstDestination data is copied to.
srcSource data is copied from.
lenAmount of data words to be copied.

Definition at line 251 of file mpu_armv7.h.

References __RESTRICT, and __STATIC_INLINE.

Referenced by ARM_MPU_Load().

◆ ARM_MPU_SetRegion()

__STATIC_INLINE void ARM_MPU_SetRegion ( uint32_t rbar,
uint32_t rasr )

Configure an MPU region.

Parameters
rbarValue for RBAR register.
rasrValue for RASR register.

Definition at line 228 of file mpu_armv7.h.

References __STATIC_INLINE, and MPU.

◆ ARM_MPU_SetRegionEx()

__STATIC_INLINE void ARM_MPU_SetRegionEx ( uint32_t rnr,
uint32_t rbar,
uint32_t rasr )

Configure the given MPU region.

Parameters
rnrRegion number to be configured.
rbarValue for RBAR register.
rasrValue for RASR register.

Definition at line 239 of file mpu_armv7.h.

References __STATIC_INLINE, and MPU.