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pmu_armv8.h File Reference

Go to the source code of this file.

Macros

#define ARM_PMU_ARMV8_H
#define ARM_PMU_SW_INCR   0x0000
 PMU Events.
#define ARM_PMU_L1I_CACHE_REFILL   0x0001
 L1 I-Cache refill.
#define ARM_PMU_L1D_CACHE_REFILL   0x0003
 L1 D-Cache refill.
#define ARM_PMU_L1D_CACHE   0x0004
 L1 D-Cache access.
#define ARM_PMU_LD_RETIRED   0x0006
 Memory-reading instruction architecturally executed and condition code check pass.
#define ARM_PMU_ST_RETIRED   0x0007
 Memory-writing instruction architecturally executed and condition code check pass.
#define ARM_PMU_INST_RETIRED   0x0008
 Instruction architecturally executed.
#define ARM_PMU_EXC_TAKEN   0x0009
 Exception entry.
#define ARM_PMU_EXC_RETURN   0x000A
 Exception return instruction architecturally executed and the condition code check pass.
#define ARM_PMU_PC_WRITE_RETIRED   0x000C
 Software change to the Program Counter (PC).
#define ARM_PMU_BR_IMMED_RETIRED   0x000D
 Immediate branch architecturally executed.
#define ARM_PMU_BR_RETURN_RETIRED   0x000E
 Function return instruction architecturally executed and the condition code check pass.
#define ARM_PMU_UNALIGNED_LDST_RETIRED   0x000F
 Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass.
#define ARM_PMU_BR_MIS_PRED   0x0010
 Mispredicted or not predicted branch speculatively executed.
#define ARM_PMU_CPU_CYCLES   0x0011
 Cycle.
#define ARM_PMU_BR_PRED   0x0012
 Predictable branch speculatively executed.
#define ARM_PMU_MEM_ACCESS   0x0013
 Data memory access.
#define ARM_PMU_L1I_CACHE   0x0014
 Level 1 instruction cache access.
#define ARM_PMU_L1D_CACHE_WB   0x0015
 Level 1 data cache write-back.
#define ARM_PMU_L2D_CACHE   0x0016
 Level 2 data cache access.
#define ARM_PMU_L2D_CACHE_REFILL   0x0017
 Level 2 data cache refill.
#define ARM_PMU_L2D_CACHE_WB   0x0018
 Level 2 data cache write-back.
#define ARM_PMU_BUS_ACCESS   0x0019
 Bus access.
#define ARM_PMU_MEMORY_ERROR   0x001A
 Local memory error.
#define ARM_PMU_INST_SPEC   0x001B
 Instruction speculatively executed.
#define ARM_PMU_BUS_CYCLES   0x001D
 Bus cycles.
#define ARM_PMU_CHAIN   0x001E
 For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE.
#define ARM_PMU_L1D_CACHE_ALLOCATE   0x001F
 Level 1 data cache allocation without refill.
#define ARM_PMU_L2D_CACHE_ALLOCATE   0x0020
 Level 2 data cache allocation without refill.
#define ARM_PMU_BR_RETIRED   0x0021
 Branch instruction architecturally executed.
#define ARM_PMU_BR_MIS_PRED_RETIRED   0x0022
 Mispredicted branch instruction architecturally executed.
#define ARM_PMU_STALL_FRONTEND   0x0023
 No operation issued because of the frontend.
#define ARM_PMU_STALL_BACKEND   0x0024
 No operation issued because of the backend.
#define ARM_PMU_L2I_CACHE   0x0027
 Level 2 instruction cache access.
#define ARM_PMU_L2I_CACHE_REFILL   0x0028
 Level 2 instruction cache refill.
#define ARM_PMU_L3D_CACHE_ALLOCATE   0x0029
 Level 3 data cache allocation without refill.
#define ARM_PMU_L3D_CACHE_REFILL   0x002A
 Level 3 data cache refill.
#define ARM_PMU_L3D_CACHE   0x002B
 Level 3 data cache access.
#define ARM_PMU_L3D_CACHE_WB   0x002C
 Level 3 data cache write-back.
#define ARM_PMU_LL_CACHE_RD   0x0036
 Last level data cache read.
#define ARM_PMU_LL_CACHE_MISS_RD   0x0037
 Last level data cache read miss.
#define ARM_PMU_L1D_CACHE_MISS_RD   0x0039
 Level 1 data cache read miss.
#define ARM_PMU_OP_COMPLETE   0x003A
 Operation retired.
#define ARM_PMU_OP_SPEC   0x003B
 Operation speculatively executed.
#define ARM_PMU_STALL   0x003C
 Stall cycle for instruction or operation not sent for execution.
#define ARM_PMU_STALL_OP_BACKEND   0x003D
 Stall cycle for instruction or operation not sent for execution due to pipeline backend.
#define ARM_PMU_STALL_OP_FRONTEND   0x003E
 Stall cycle for instruction or operation not sent for execution due to pipeline frontend.
#define ARM_PMU_STALL_OP   0x003F
 Instruction or operation slots not occupied each cycle.
#define ARM_PMU_L1D_CACHE_RD   0x0040
 Level 1 data cache read.
#define ARM_PMU_LE_RETIRED   0x0100
 Loop end instruction executed.
#define ARM_PMU_LE_SPEC   0x0101
 Loop end instruction speculatively executed.
#define ARM_PMU_BF_RETIRED   0x0104
 Branch future instruction architecturally executed and condition code check pass.
#define ARM_PMU_BF_SPEC   0x0105
 Branch future instruction speculatively executed and condition code check pass.
#define ARM_PMU_LE_CANCEL   0x0108
 Loop end instruction not taken.
#define ARM_PMU_BF_CANCEL   0x0109
 Branch future instruction not taken.
#define ARM_PMU_SE_CALL_S   0x0114
 Call to secure function, resulting in Security state change.
#define ARM_PMU_SE_CALL_NS   0x0115
 Call to non-secure function, resulting in Security state change.
#define ARM_PMU_DWT_CMPMATCH0   0x0118
 DWT comparator 0 match.
#define ARM_PMU_DWT_CMPMATCH1   0x0119
 DWT comparator 1 match.
#define ARM_PMU_DWT_CMPMATCH2   0x011A
 DWT comparator 2 match.
#define ARM_PMU_DWT_CMPMATCH3   0x011B
 DWT comparator 3 match.
#define ARM_PMU_MVE_INST_RETIRED   0x0200
 MVE instruction architecturally executed.
#define ARM_PMU_MVE_INST_SPEC   0x0201
 MVE instruction speculatively executed.
#define ARM_PMU_MVE_FP_RETIRED   0x0204
 MVE floating-point instruction architecturally executed.
#define ARM_PMU_MVE_FP_SPEC   0x0205
 MVE floating-point instruction speculatively executed.
#define ARM_PMU_MVE_FP_HP_RETIRED   0x0208
 MVE half-precision floating-point instruction architecturally executed.
#define ARM_PMU_MVE_FP_HP_SPEC   0x0209
 MVE half-precision floating-point instruction speculatively executed.
#define ARM_PMU_MVE_FP_SP_RETIRED   0x020C
 MVE single-precision floating-point instruction architecturally executed.
#define ARM_PMU_MVE_FP_SP_SPEC   0x020D
 MVE single-precision floating-point instruction speculatively executed.
#define ARM_PMU_MVE_FP_MAC_RETIRED   0x0214
 MVE floating-point multiply or multiply-accumulate instruction architecturally executed.
#define ARM_PMU_MVE_FP_MAC_SPEC   0x0215
 MVE floating-point multiply or multiply-accumulate instruction speculatively executed.
#define ARM_PMU_MVE_INT_RETIRED   0x0224
 MVE integer instruction architecturally executed.
#define ARM_PMU_MVE_INT_SPEC   0x0225
 MVE integer instruction speculatively executed.
#define ARM_PMU_MVE_INT_MAC_RETIRED   0x0228
 MVE multiply or multiply-accumulate instruction architecturally executed.
#define ARM_PMU_MVE_INT_MAC_SPEC   0x0229
 MVE multiply or multiply-accumulate instruction speculatively executed.
#define ARM_PMU_MVE_LDST_RETIRED   0x0238
 MVE load or store instruction architecturally executed.
#define ARM_PMU_MVE_LDST_SPEC   0x0239
 MVE load or store instruction speculatively executed.
#define ARM_PMU_MVE_LD_RETIRED   0x023C
 MVE load instruction architecturally executed.
#define ARM_PMU_MVE_LD_SPEC   0x023D
 MVE load instruction speculatively executed.
#define ARM_PMU_MVE_ST_RETIRED   0x0240
 MVE store instruction architecturally executed.
#define ARM_PMU_MVE_ST_SPEC   0x0241
 MVE store instruction speculatively executed.
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED   0x0244
 MVE contiguous load or store instruction architecturally executed.
#define ARM_PMU_MVE_LDST_CONTIG_SPEC   0x0245
 MVE contiguous load or store instruction speculatively executed.
#define ARM_PMU_MVE_LD_CONTIG_RETIRED   0x0248
 MVE contiguous load instruction architecturally executed.
#define ARM_PMU_MVE_LD_CONTIG_SPEC   0x0249
 MVE contiguous load instruction speculatively executed.
#define ARM_PMU_MVE_ST_CONTIG_RETIRED   0x024C
 MVE contiguous store instruction architecturally executed.
#define ARM_PMU_MVE_ST_CONTIG_SPEC   0x024D
 MVE contiguous store instruction speculatively executed.
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED   0x0250
 MVE non-contiguous load or store instruction architecturally executed.
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC   0x0251
 MVE non-contiguous load or store instruction speculatively executed.
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED   0x0254
 MVE non-contiguous load instruction architecturally executed.
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC   0x0255
 MVE non-contiguous load instruction speculatively executed.
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED   0x0258
 MVE non-contiguous store instruction architecturally executed.
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC   0x0259
 MVE non-contiguous store instruction speculatively executed.
#define ARM_PMU_MVE_LDST_MULTI_RETIRED   0x025C
 MVE memory instruction targeting multiple registers architecturally executed.
#define ARM_PMU_MVE_LDST_MULTI_SPEC   0x025D
 MVE memory instruction targeting multiple registers speculatively executed.
#define ARM_PMU_MVE_LD_MULTI_RETIRED   0x0260
 MVE memory load instruction targeting multiple registers architecturally executed.
#define ARM_PMU_MVE_LD_MULTI_SPEC   0x0261
 MVE memory load instruction targeting multiple registers speculatively executed.
#define ARM_PMU_MVE_ST_MULTI_RETIRED   0x0261
 MVE memory store instruction targeting multiple registers architecturally executed.
#define ARM_PMU_MVE_ST_MULTI_SPEC   0x0265
 MVE memory store instruction targeting multiple registers speculatively executed.
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED   0x028C
 MVE unaligned memory load or store instruction architecturally executed.
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC   0x028D
 MVE unaligned memory load or store instruction speculatively executed.
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED   0x0290
 MVE unaligned load instruction architecturally executed.
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC   0x0291
 MVE unaligned load instruction speculatively executed.
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED   0x0294
 MVE unaligned store instruction architecturally executed.
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC   0x0295
 MVE unaligned store instruction speculatively executed.
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED   0x0298
 MVE unaligned noncontiguous load or store instruction architecturally executed.
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC   0x0299
 MVE unaligned noncontiguous load or store instruction speculatively executed.
#define ARM_PMU_MVE_VREDUCE_RETIRED   0x02A0
 MVE vector reduction instruction architecturally executed.
#define ARM_PMU_MVE_VREDUCE_SPEC   0x02A1
 MVE vector reduction instruction speculatively executed.
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED   0x02A4
 MVE floating-point vector reduction instruction architecturally executed.
#define ARM_PMU_MVE_VREDUCE_FP_SPEC   0x02A5
 MVE floating-point vector reduction instruction speculatively executed.
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED   0x02A8
 MVE integer vector reduction instruction architecturally executed.
#define ARM_PMU_MVE_VREDUCE_INT_SPEC   0x02A9
 MVE integer vector reduction instruction speculatively executed.
#define ARM_PMU_MVE_PRED   0x02B8
 Cycles where one or more predicated beats architecturally executed.
#define ARM_PMU_MVE_STALL   0x02CC
 Stall cycles caused by an MVE instruction.
#define ARM_PMU_MVE_STALL_RESOURCE   0x02CD
 Stall cycles caused by an MVE instruction because of resource conflicts.
#define ARM_PMU_MVE_STALL_RESOURCE_MEM   0x02CE
 Stall cycles caused by an MVE instruction because of memory resource conflicts.
#define ARM_PMU_MVE_STALL_RESOURCE_FP   0x02CF
 Stall cycles caused by an MVE instruction because of floating-point resource conflicts.
#define ARM_PMU_MVE_STALL_RESOURCE_INT   0x02D0
 Stall cycles caused by an MVE instruction because of integer resource conflicts.
#define ARM_PMU_MVE_STALL_BREAK   0x02D3
 Stall cycles caused by an MVE chain break.
#define ARM_PMU_MVE_STALL_DEPENDENCY   0x02D4
 Stall cycles caused by MVE register dependency.
#define ARM_PMU_ITCM_ACCESS   0x4007
 Instruction TCM access.
#define ARM_PMU_DTCM_ACCESS   0x4008
 Data TCM access.
#define ARM_PMU_TRCEXTOUT0   0x4010
 ETM external output 0.
#define ARM_PMU_TRCEXTOUT1   0x4011
 ETM external output 1.
#define ARM_PMU_TRCEXTOUT2   0x4012
 ETM external output 2.
#define ARM_PMU_TRCEXTOUT3   0x4013
 ETM external output 3.
#define ARM_PMU_CTI_TRIGOUT4   0x4018
 Cross-trigger Interface output trigger 4.
#define ARM_PMU_CTI_TRIGOUT5   0x4019
 Cross-trigger Interface output trigger 5.
#define ARM_PMU_CTI_TRIGOUT6   0x401A
 Cross-trigger Interface output trigger 6.
#define ARM_PMU_CTI_TRIGOUT7   0x401B
 Cross-trigger Interface output trigger 7.

Functions

__STATIC_INLINE void ARM_PMU_Enable (void)
 PMU Functions.
__STATIC_INLINE void ARM_PMU_Disable (void)
 Disable the PMU.
__STATIC_INLINE void ARM_PMU_Set_EVTYPER (uint32_t num, uint32_t type)
 Set event to count for PMU eventer counter.
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset (void)
 Reset cycle counter.
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset (void)
 Reset all event counters.
__STATIC_INLINE void ARM_PMU_CNTR_Enable (uint32_t mask)
 Enable counters.
__STATIC_INLINE void ARM_PMU_CNTR_Disable (uint32_t mask)
 Disable counters.
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR (void)
 Read cycle counter.
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR (uint32_t num)
 Read event counter.
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS (void)
 Read counter overflow status.
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS (uint32_t mask)
 Clear counter overflow status.
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable (uint32_t mask)
 Enable counter overflow interrupt request.
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable (uint32_t mask)
 Disable counter overflow interrupt request.
__STATIC_INLINE void ARM_PMU_CNTR_Increment (uint32_t mask)
 Software increment event counter.

Macro Definition Documentation

◆ ARM_PMU_ARMV8_H

#define ARM_PMU_ARMV8_H

Definition at line 32 of file pmu_armv8.h.

◆ ARM_PMU_BF_CANCEL

#define ARM_PMU_BF_CANCEL   0x0109

Branch future instruction not taken.

Definition at line 93 of file pmu_armv8.h.

◆ ARM_PMU_BF_RETIRED

#define ARM_PMU_BF_RETIRED   0x0104

Branch future instruction architecturally executed and condition code check pass.

Definition at line 90 of file pmu_armv8.h.

◆ ARM_PMU_BF_SPEC

#define ARM_PMU_BF_SPEC   0x0105

Branch future instruction speculatively executed and condition code check pass.

Definition at line 91 of file pmu_armv8.h.

◆ ARM_PMU_BR_IMMED_RETIRED

#define ARM_PMU_BR_IMMED_RETIRED   0x000D

Immediate branch architecturally executed.

Definition at line 49 of file pmu_armv8.h.

◆ ARM_PMU_BR_MIS_PRED

#define ARM_PMU_BR_MIS_PRED   0x0010

Mispredicted or not predicted branch speculatively executed.

Definition at line 52 of file pmu_armv8.h.

◆ ARM_PMU_BR_MIS_PRED_RETIRED

#define ARM_PMU_BR_MIS_PRED_RETIRED   0x0022

Mispredicted branch instruction architecturally executed.

Definition at line 69 of file pmu_armv8.h.

◆ ARM_PMU_BR_PRED

#define ARM_PMU_BR_PRED   0x0012

Predictable branch speculatively executed.

Definition at line 54 of file pmu_armv8.h.

◆ ARM_PMU_BR_RETIRED

#define ARM_PMU_BR_RETIRED   0x0021

Branch instruction architecturally executed.

Definition at line 68 of file pmu_armv8.h.

◆ ARM_PMU_BR_RETURN_RETIRED

#define ARM_PMU_BR_RETURN_RETIRED   0x000E

Function return instruction architecturally executed and the condition code check pass.

Definition at line 50 of file pmu_armv8.h.

◆ ARM_PMU_BUS_ACCESS

#define ARM_PMU_BUS_ACCESS   0x0019

Bus access.

Definition at line 61 of file pmu_armv8.h.

◆ ARM_PMU_BUS_CYCLES

#define ARM_PMU_BUS_CYCLES   0x001D

Bus cycles.

Definition at line 64 of file pmu_armv8.h.

◆ ARM_PMU_CHAIN

#define ARM_PMU_CHAIN   0x001E

For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE.

Definition at line 65 of file pmu_armv8.h.

◆ ARM_PMU_CPU_CYCLES

#define ARM_PMU_CPU_CYCLES   0x0011

Cycle.

Definition at line 53 of file pmu_armv8.h.

◆ ARM_PMU_CTI_TRIGOUT4

#define ARM_PMU_CTI_TRIGOUT4   0x4018

Cross-trigger Interface output trigger 4.

Definition at line 166 of file pmu_armv8.h.

◆ ARM_PMU_CTI_TRIGOUT5

#define ARM_PMU_CTI_TRIGOUT5   0x4019

Cross-trigger Interface output trigger 5.

Definition at line 167 of file pmu_armv8.h.

◆ ARM_PMU_CTI_TRIGOUT6

#define ARM_PMU_CTI_TRIGOUT6   0x401A

Cross-trigger Interface output trigger 6.

Definition at line 168 of file pmu_armv8.h.

◆ ARM_PMU_CTI_TRIGOUT7

#define ARM_PMU_CTI_TRIGOUT7   0x401B

Cross-trigger Interface output trigger 7.

Definition at line 169 of file pmu_armv8.h.

◆ ARM_PMU_DTCM_ACCESS

#define ARM_PMU_DTCM_ACCESS   0x4008

Data TCM access.

Definition at line 161 of file pmu_armv8.h.

◆ ARM_PMU_DWT_CMPMATCH0

#define ARM_PMU_DWT_CMPMATCH0   0x0118

DWT comparator 0 match.

Definition at line 96 of file pmu_armv8.h.

◆ ARM_PMU_DWT_CMPMATCH1

#define ARM_PMU_DWT_CMPMATCH1   0x0119

DWT comparator 1 match.

Definition at line 97 of file pmu_armv8.h.

◆ ARM_PMU_DWT_CMPMATCH2

#define ARM_PMU_DWT_CMPMATCH2   0x011A

DWT comparator 2 match.

Definition at line 98 of file pmu_armv8.h.

◆ ARM_PMU_DWT_CMPMATCH3

#define ARM_PMU_DWT_CMPMATCH3   0x011B

DWT comparator 3 match.

Definition at line 99 of file pmu_armv8.h.

◆ ARM_PMU_EXC_RETURN

#define ARM_PMU_EXC_RETURN   0x000A

Exception return instruction architecturally executed and the condition code check pass.

Definition at line 47 of file pmu_armv8.h.

◆ ARM_PMU_EXC_TAKEN

#define ARM_PMU_EXC_TAKEN   0x0009

Exception entry.

Definition at line 46 of file pmu_armv8.h.

◆ ARM_PMU_INST_RETIRED

#define ARM_PMU_INST_RETIRED   0x0008

Instruction architecturally executed.

Definition at line 45 of file pmu_armv8.h.

◆ ARM_PMU_INST_SPEC

#define ARM_PMU_INST_SPEC   0x001B

Instruction speculatively executed.

Definition at line 63 of file pmu_armv8.h.

◆ ARM_PMU_ITCM_ACCESS

#define ARM_PMU_ITCM_ACCESS   0x4007

Instruction TCM access.

Definition at line 160 of file pmu_armv8.h.

◆ ARM_PMU_L1D_CACHE

#define ARM_PMU_L1D_CACHE   0x0004

L1 D-Cache access.

Definition at line 42 of file pmu_armv8.h.

◆ ARM_PMU_L1D_CACHE_ALLOCATE

#define ARM_PMU_L1D_CACHE_ALLOCATE   0x001F

Level 1 data cache allocation without refill.

Definition at line 66 of file pmu_armv8.h.

◆ ARM_PMU_L1D_CACHE_MISS_RD

#define ARM_PMU_L1D_CACHE_MISS_RD   0x0039

Level 1 data cache read miss.

Definition at line 80 of file pmu_armv8.h.

◆ ARM_PMU_L1D_CACHE_RD

#define ARM_PMU_L1D_CACHE_RD   0x0040

Level 1 data cache read.

Definition at line 87 of file pmu_armv8.h.

◆ ARM_PMU_L1D_CACHE_REFILL

#define ARM_PMU_L1D_CACHE_REFILL   0x0003

L1 D-Cache refill.

Definition at line 41 of file pmu_armv8.h.

◆ ARM_PMU_L1D_CACHE_WB

#define ARM_PMU_L1D_CACHE_WB   0x0015

Level 1 data cache write-back.

Definition at line 57 of file pmu_armv8.h.

◆ ARM_PMU_L1I_CACHE

#define ARM_PMU_L1I_CACHE   0x0014

Level 1 instruction cache access.

Definition at line 56 of file pmu_armv8.h.

◆ ARM_PMU_L1I_CACHE_REFILL

#define ARM_PMU_L1I_CACHE_REFILL   0x0001

L1 I-Cache refill.

Definition at line 40 of file pmu_armv8.h.

◆ ARM_PMU_L2D_CACHE

#define ARM_PMU_L2D_CACHE   0x0016

Level 2 data cache access.

Definition at line 58 of file pmu_armv8.h.

◆ ARM_PMU_L2D_CACHE_ALLOCATE

#define ARM_PMU_L2D_CACHE_ALLOCATE   0x0020

Level 2 data cache allocation without refill.

Definition at line 67 of file pmu_armv8.h.

◆ ARM_PMU_L2D_CACHE_REFILL

#define ARM_PMU_L2D_CACHE_REFILL   0x0017

Level 2 data cache refill.

Definition at line 59 of file pmu_armv8.h.

◆ ARM_PMU_L2D_CACHE_WB

#define ARM_PMU_L2D_CACHE_WB   0x0018

Level 2 data cache write-back.

Definition at line 60 of file pmu_armv8.h.

◆ ARM_PMU_L2I_CACHE

#define ARM_PMU_L2I_CACHE   0x0027

Level 2 instruction cache access.

Definition at line 72 of file pmu_armv8.h.

◆ ARM_PMU_L2I_CACHE_REFILL

#define ARM_PMU_L2I_CACHE_REFILL   0x0028

Level 2 instruction cache refill.

Definition at line 73 of file pmu_armv8.h.

◆ ARM_PMU_L3D_CACHE

#define ARM_PMU_L3D_CACHE   0x002B

Level 3 data cache access.

Definition at line 76 of file pmu_armv8.h.

◆ ARM_PMU_L3D_CACHE_ALLOCATE

#define ARM_PMU_L3D_CACHE_ALLOCATE   0x0029

Level 3 data cache allocation without refill.

Definition at line 74 of file pmu_armv8.h.

◆ ARM_PMU_L3D_CACHE_REFILL

#define ARM_PMU_L3D_CACHE_REFILL   0x002A

Level 3 data cache refill.

Definition at line 75 of file pmu_armv8.h.

◆ ARM_PMU_L3D_CACHE_WB

#define ARM_PMU_L3D_CACHE_WB   0x002C

Level 3 data cache write-back.

Definition at line 77 of file pmu_armv8.h.

◆ ARM_PMU_LD_RETIRED

#define ARM_PMU_LD_RETIRED   0x0006

Memory-reading instruction architecturally executed and condition code check pass.

Definition at line 43 of file pmu_armv8.h.

◆ ARM_PMU_LE_CANCEL

#define ARM_PMU_LE_CANCEL   0x0108

Loop end instruction not taken.

Definition at line 92 of file pmu_armv8.h.

◆ ARM_PMU_LE_RETIRED

#define ARM_PMU_LE_RETIRED   0x0100

Loop end instruction executed.

Definition at line 88 of file pmu_armv8.h.

◆ ARM_PMU_LE_SPEC

#define ARM_PMU_LE_SPEC   0x0101

Loop end instruction speculatively executed.

Definition at line 89 of file pmu_armv8.h.

◆ ARM_PMU_LL_CACHE_MISS_RD

#define ARM_PMU_LL_CACHE_MISS_RD   0x0037

Last level data cache read miss.

Definition at line 79 of file pmu_armv8.h.

◆ ARM_PMU_LL_CACHE_RD

#define ARM_PMU_LL_CACHE_RD   0x0036

Last level data cache read.

Definition at line 78 of file pmu_armv8.h.

◆ ARM_PMU_MEM_ACCESS

#define ARM_PMU_MEM_ACCESS   0x0013

Data memory access.

Definition at line 55 of file pmu_armv8.h.

◆ ARM_PMU_MEMORY_ERROR

#define ARM_PMU_MEMORY_ERROR   0x001A

Local memory error.

Definition at line 62 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_HP_RETIRED

#define ARM_PMU_MVE_FP_HP_RETIRED   0x0208

MVE half-precision floating-point instruction architecturally executed.

Definition at line 104 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_HP_SPEC

#define ARM_PMU_MVE_FP_HP_SPEC   0x0209

MVE half-precision floating-point instruction speculatively executed.

Definition at line 105 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_MAC_RETIRED

#define ARM_PMU_MVE_FP_MAC_RETIRED   0x0214

MVE floating-point multiply or multiply-accumulate instruction architecturally executed.

Definition at line 108 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_MAC_SPEC

#define ARM_PMU_MVE_FP_MAC_SPEC   0x0215

MVE floating-point multiply or multiply-accumulate instruction speculatively executed.

Definition at line 109 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_RETIRED

#define ARM_PMU_MVE_FP_RETIRED   0x0204

MVE floating-point instruction architecturally executed.

Definition at line 102 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_SP_RETIRED

#define ARM_PMU_MVE_FP_SP_RETIRED   0x020C

MVE single-precision floating-point instruction architecturally executed.

Definition at line 106 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_SP_SPEC

#define ARM_PMU_MVE_FP_SP_SPEC   0x020D

MVE single-precision floating-point instruction speculatively executed.

Definition at line 107 of file pmu_armv8.h.

◆ ARM_PMU_MVE_FP_SPEC

#define ARM_PMU_MVE_FP_SPEC   0x0205

MVE floating-point instruction speculatively executed.

Definition at line 103 of file pmu_armv8.h.

◆ ARM_PMU_MVE_INST_RETIRED

#define ARM_PMU_MVE_INST_RETIRED   0x0200

MVE instruction architecturally executed.

Definition at line 100 of file pmu_armv8.h.

◆ ARM_PMU_MVE_INST_SPEC

#define ARM_PMU_MVE_INST_SPEC   0x0201

MVE instruction speculatively executed.

Definition at line 101 of file pmu_armv8.h.

◆ ARM_PMU_MVE_INT_MAC_RETIRED

#define ARM_PMU_MVE_INT_MAC_RETIRED   0x0228

MVE multiply or multiply-accumulate instruction architecturally executed.

Definition at line 112 of file pmu_armv8.h.

◆ ARM_PMU_MVE_INT_MAC_SPEC

#define ARM_PMU_MVE_INT_MAC_SPEC   0x0229

MVE multiply or multiply-accumulate instruction speculatively executed.

Definition at line 113 of file pmu_armv8.h.

◆ ARM_PMU_MVE_INT_RETIRED

#define ARM_PMU_MVE_INT_RETIRED   0x0224

MVE integer instruction architecturally executed.

Definition at line 110 of file pmu_armv8.h.

◆ ARM_PMU_MVE_INT_SPEC

#define ARM_PMU_MVE_INT_SPEC   0x0225

MVE integer instruction speculatively executed.

Definition at line 111 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_CONTIG_RETIRED

#define ARM_PMU_MVE_LD_CONTIG_RETIRED   0x0248

MVE contiguous load instruction architecturally executed.

Definition at line 122 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_CONTIG_SPEC

#define ARM_PMU_MVE_LD_CONTIG_SPEC   0x0249

MVE contiguous load instruction speculatively executed.

Definition at line 123 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_MULTI_RETIRED

#define ARM_PMU_MVE_LD_MULTI_RETIRED   0x0260

MVE memory load instruction targeting multiple registers architecturally executed.

Definition at line 134 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_MULTI_SPEC

#define ARM_PMU_MVE_LD_MULTI_SPEC   0x0261

MVE memory load instruction targeting multiple registers speculatively executed.

Definition at line 135 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_NONCONTIG_RETIRED

#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED   0x0254

MVE non-contiguous load instruction architecturally executed.

Definition at line 128 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_NONCONTIG_SPEC

#define ARM_PMU_MVE_LD_NONCONTIG_SPEC   0x0255

MVE non-contiguous load instruction speculatively executed.

Definition at line 129 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_RETIRED

#define ARM_PMU_MVE_LD_RETIRED   0x023C

MVE load instruction architecturally executed.

Definition at line 116 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_SPEC

#define ARM_PMU_MVE_LD_SPEC   0x023D

MVE load instruction speculatively executed.

Definition at line 117 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_UNALIGNED_RETIRED

#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED   0x0290

MVE unaligned load instruction architecturally executed.

Definition at line 140 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LD_UNALIGNED_SPEC

#define ARM_PMU_MVE_LD_UNALIGNED_SPEC   0x0291

MVE unaligned load instruction speculatively executed.

Definition at line 141 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_CONTIG_RETIRED

#define ARM_PMU_MVE_LDST_CONTIG_RETIRED   0x0244

MVE contiguous load or store instruction architecturally executed.

Definition at line 120 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_CONTIG_SPEC

#define ARM_PMU_MVE_LDST_CONTIG_SPEC   0x0245

MVE contiguous load or store instruction speculatively executed.

Definition at line 121 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_MULTI_RETIRED

#define ARM_PMU_MVE_LDST_MULTI_RETIRED   0x025C

MVE memory instruction targeting multiple registers architecturally executed.

Definition at line 132 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_MULTI_SPEC

#define ARM_PMU_MVE_LDST_MULTI_SPEC   0x025D

MVE memory instruction targeting multiple registers speculatively executed.

Definition at line 133 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_NONCONTIG_RETIRED

#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED   0x0250

MVE non-contiguous load or store instruction architecturally executed.

Definition at line 126 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_NONCONTIG_SPEC

#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC   0x0251

MVE non-contiguous load or store instruction speculatively executed.

Definition at line 127 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_RETIRED

#define ARM_PMU_MVE_LDST_RETIRED   0x0238

MVE load or store instruction architecturally executed.

Definition at line 114 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_SPEC

#define ARM_PMU_MVE_LDST_SPEC   0x0239

MVE load or store instruction speculatively executed.

Definition at line 115 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED

#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED   0x0298

MVE unaligned noncontiguous load or store instruction architecturally executed.

Definition at line 144 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC

#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC   0x0299

MVE unaligned noncontiguous load or store instruction speculatively executed.

Definition at line 145 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_UNALIGNED_RETIRED

#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED   0x028C

MVE unaligned memory load or store instruction architecturally executed.

Definition at line 138 of file pmu_armv8.h.

◆ ARM_PMU_MVE_LDST_UNALIGNED_SPEC

#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC   0x028D

MVE unaligned memory load or store instruction speculatively executed.

Definition at line 139 of file pmu_armv8.h.

◆ ARM_PMU_MVE_PRED

#define ARM_PMU_MVE_PRED   0x02B8

Cycles where one or more predicated beats architecturally executed.

Definition at line 152 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_CONTIG_RETIRED

#define ARM_PMU_MVE_ST_CONTIG_RETIRED   0x024C

MVE contiguous store instruction architecturally executed.

Definition at line 124 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_CONTIG_SPEC

#define ARM_PMU_MVE_ST_CONTIG_SPEC   0x024D

MVE contiguous store instruction speculatively executed.

Definition at line 125 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_MULTI_RETIRED

#define ARM_PMU_MVE_ST_MULTI_RETIRED   0x0261

MVE memory store instruction targeting multiple registers architecturally executed.

Definition at line 136 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_MULTI_SPEC

#define ARM_PMU_MVE_ST_MULTI_SPEC   0x0265

MVE memory store instruction targeting multiple registers speculatively executed.

Definition at line 137 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_NONCONTIG_RETIRED

#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED   0x0258

MVE non-contiguous store instruction architecturally executed.

Definition at line 130 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_NONCONTIG_SPEC

#define ARM_PMU_MVE_ST_NONCONTIG_SPEC   0x0259

MVE non-contiguous store instruction speculatively executed.

Definition at line 131 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_RETIRED

#define ARM_PMU_MVE_ST_RETIRED   0x0240

MVE store instruction architecturally executed.

Definition at line 118 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_SPEC

#define ARM_PMU_MVE_ST_SPEC   0x0241

MVE store instruction speculatively executed.

Definition at line 119 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_UNALIGNED_RETIRED

#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED   0x0294

MVE unaligned store instruction architecturally executed.

Definition at line 142 of file pmu_armv8.h.

◆ ARM_PMU_MVE_ST_UNALIGNED_SPEC

#define ARM_PMU_MVE_ST_UNALIGNED_SPEC   0x0295

MVE unaligned store instruction speculatively executed.

Definition at line 143 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL

#define ARM_PMU_MVE_STALL   0x02CC

Stall cycles caused by an MVE instruction.

Definition at line 153 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL_BREAK

#define ARM_PMU_MVE_STALL_BREAK   0x02D3

Stall cycles caused by an MVE chain break.

Definition at line 158 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL_DEPENDENCY

#define ARM_PMU_MVE_STALL_DEPENDENCY   0x02D4

Stall cycles caused by MVE register dependency.

Definition at line 159 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL_RESOURCE

#define ARM_PMU_MVE_STALL_RESOURCE   0x02CD

Stall cycles caused by an MVE instruction because of resource conflicts.

Definition at line 154 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL_RESOURCE_FP

#define ARM_PMU_MVE_STALL_RESOURCE_FP   0x02CF

Stall cycles caused by an MVE instruction because of floating-point resource conflicts.

Definition at line 156 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL_RESOURCE_INT

#define ARM_PMU_MVE_STALL_RESOURCE_INT   0x02D0

Stall cycles caused by an MVE instruction because of integer resource conflicts.

Definition at line 157 of file pmu_armv8.h.

◆ ARM_PMU_MVE_STALL_RESOURCE_MEM

#define ARM_PMU_MVE_STALL_RESOURCE_MEM   0x02CE

Stall cycles caused by an MVE instruction because of memory resource conflicts.

Definition at line 155 of file pmu_armv8.h.

◆ ARM_PMU_MVE_VREDUCE_FP_RETIRED

#define ARM_PMU_MVE_VREDUCE_FP_RETIRED   0x02A4

MVE floating-point vector reduction instruction architecturally executed.

Definition at line 148 of file pmu_armv8.h.

◆ ARM_PMU_MVE_VREDUCE_FP_SPEC

#define ARM_PMU_MVE_VREDUCE_FP_SPEC   0x02A5

MVE floating-point vector reduction instruction speculatively executed.

Definition at line 149 of file pmu_armv8.h.

◆ ARM_PMU_MVE_VREDUCE_INT_RETIRED

#define ARM_PMU_MVE_VREDUCE_INT_RETIRED   0x02A8

MVE integer vector reduction instruction architecturally executed.

Definition at line 150 of file pmu_armv8.h.

◆ ARM_PMU_MVE_VREDUCE_INT_SPEC

#define ARM_PMU_MVE_VREDUCE_INT_SPEC   0x02A9

MVE integer vector reduction instruction speculatively executed.

Definition at line 151 of file pmu_armv8.h.

◆ ARM_PMU_MVE_VREDUCE_RETIRED

#define ARM_PMU_MVE_VREDUCE_RETIRED   0x02A0

MVE vector reduction instruction architecturally executed.

Definition at line 146 of file pmu_armv8.h.

◆ ARM_PMU_MVE_VREDUCE_SPEC

#define ARM_PMU_MVE_VREDUCE_SPEC   0x02A1

MVE vector reduction instruction speculatively executed.

Definition at line 147 of file pmu_armv8.h.

◆ ARM_PMU_OP_COMPLETE

#define ARM_PMU_OP_COMPLETE   0x003A

Operation retired.

Definition at line 81 of file pmu_armv8.h.

◆ ARM_PMU_OP_SPEC

#define ARM_PMU_OP_SPEC   0x003B

Operation speculatively executed.

Definition at line 82 of file pmu_armv8.h.

◆ ARM_PMU_PC_WRITE_RETIRED

#define ARM_PMU_PC_WRITE_RETIRED   0x000C

Software change to the Program Counter (PC).

Instruction is architecturally executed and condition code check pass

Definition at line 48 of file pmu_armv8.h.

◆ ARM_PMU_SE_CALL_NS

#define ARM_PMU_SE_CALL_NS   0x0115

Call to non-secure function, resulting in Security state change.

Definition at line 95 of file pmu_armv8.h.

◆ ARM_PMU_SE_CALL_S

#define ARM_PMU_SE_CALL_S   0x0114

Call to secure function, resulting in Security state change.

Definition at line 94 of file pmu_armv8.h.

◆ ARM_PMU_ST_RETIRED

#define ARM_PMU_ST_RETIRED   0x0007

Memory-writing instruction architecturally executed and condition code check pass.

Definition at line 44 of file pmu_armv8.h.

◆ ARM_PMU_STALL

#define ARM_PMU_STALL   0x003C

Stall cycle for instruction or operation not sent for execution.

Definition at line 83 of file pmu_armv8.h.

◆ ARM_PMU_STALL_BACKEND

#define ARM_PMU_STALL_BACKEND   0x0024

No operation issued because of the backend.

Definition at line 71 of file pmu_armv8.h.

◆ ARM_PMU_STALL_FRONTEND

#define ARM_PMU_STALL_FRONTEND   0x0023

No operation issued because of the frontend.

Definition at line 70 of file pmu_armv8.h.

◆ ARM_PMU_STALL_OP

#define ARM_PMU_STALL_OP   0x003F

Instruction or operation slots not occupied each cycle.

Definition at line 86 of file pmu_armv8.h.

◆ ARM_PMU_STALL_OP_BACKEND

#define ARM_PMU_STALL_OP_BACKEND   0x003D

Stall cycle for instruction or operation not sent for execution due to pipeline backend.

Definition at line 84 of file pmu_armv8.h.

◆ ARM_PMU_STALL_OP_FRONTEND

#define ARM_PMU_STALL_OP_FRONTEND   0x003E

Stall cycle for instruction or operation not sent for execution due to pipeline frontend.

Definition at line 85 of file pmu_armv8.h.

◆ ARM_PMU_SW_INCR

#define ARM_PMU_SW_INCR   0x0000

PMU Events.

Note
See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. Software update to the PMU_SWINC register, architecturally executed and condition code check pass

Definition at line 39 of file pmu_armv8.h.

◆ ARM_PMU_TRCEXTOUT0

#define ARM_PMU_TRCEXTOUT0   0x4010

ETM external output 0.

Definition at line 162 of file pmu_armv8.h.

◆ ARM_PMU_TRCEXTOUT1

#define ARM_PMU_TRCEXTOUT1   0x4011

ETM external output 1.

Definition at line 163 of file pmu_armv8.h.

◆ ARM_PMU_TRCEXTOUT2

#define ARM_PMU_TRCEXTOUT2   0x4012

ETM external output 2.

Definition at line 164 of file pmu_armv8.h.

◆ ARM_PMU_TRCEXTOUT3

#define ARM_PMU_TRCEXTOUT3   0x4013

ETM external output 3.

Definition at line 165 of file pmu_armv8.h.

◆ ARM_PMU_UNALIGNED_LDST_RETIRED

#define ARM_PMU_UNALIGNED_LDST_RETIRED   0x000F

Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass.

Definition at line 51 of file pmu_armv8.h.

Function Documentation

◆ ARM_PMU_CNTR_Disable()

__STATIC_INLINE void ARM_PMU_CNTR_Disable ( uint32_t mask)

Disable counters.

Parameters
[in]maskCounters to enable
Note
Disables one or more of the following:
  • event counters (0-30)
  • cycle counter

Definition at line 256 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_CNTR_Enable()

__STATIC_INLINE void ARM_PMU_CNTR_Enable ( uint32_t mask)

Enable counters.

Parameters
[in]maskCounters to enable
Note
Enables one or more of the following:
  • event counters (0-30)
  • cycle counter

Definition at line 244 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_CNTR_Increment()

__STATIC_INLINE void ARM_PMU_CNTR_Increment ( uint32_t mask)

Software increment event counter.

Parameters
[in]maskCounters to increment
Note
Software increment bits for one or more event counters (0-30)

Definition at line 332 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_CYCCNT_Reset()

__STATIC_INLINE void ARM_PMU_CYCCNT_Reset ( void )

Reset cycle counter.

Definition at line 224 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Disable()

__STATIC_INLINE void ARM_PMU_Disable ( void )

Disable the PMU.

Definition at line 206 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Enable()

__STATIC_INLINE void ARM_PMU_Enable ( void )

PMU Functions.

Enable the PMU.

Definition at line 198 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_EVCNTR_ALL_Reset()

__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset ( void )

Reset all event counters.

Definition at line 232 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Get_CCNTR()

__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR ( void )

Read cycle counter.

Returns
Cycle count

Definition at line 265 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Get_CNTR_OVS()

__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS ( void )

Read counter overflow status.

Returns
Counter overflow status bits for the following:
  • event counters (0-30)
  • cycle counter

Definition at line 286 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Get_EVCNTR()

__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR ( uint32_t num)

Read event counter.

Parameters
[in]numEvent counter (0-30) to read
Returns
Event count

Definition at line 275 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Set_CNTR_IRQ_Disable()

__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable ( uint32_t mask)

Disable counter overflow interrupt request.

Parameters
[in]maskCounter overflow interrupt request bits to clear
Note
Clears overflow interrupt request bits for one or more of the following:
  • event counters (0-30)
  • cycle counter

Definition at line 322 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Set_CNTR_IRQ_Enable()

__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable ( uint32_t mask)

Enable counter overflow interrupt request.

Parameters
[in]maskCounter overflow interrupt request bits to set
Note
Sets overflow interrupt request bits for one or more of the following:
  • event counters (0-30)
  • cycle counter

Definition at line 310 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Set_CNTR_OVS()

__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS ( uint32_t mask)

Clear counter overflow status.

Parameters
[in]maskCounter overflow status bits to clear
Note
Clears overflow status bits for one or more of the following:
  • event counters (0-30)
  • cycle counter

Definition at line 298 of file pmu_armv8.h.

References __STATIC_INLINE.

◆ ARM_PMU_Set_EVTYPER()

__STATIC_INLINE void ARM_PMU_Set_EVTYPER ( uint32_t num,
uint32_t type )

Set event to count for PMU eventer counter.

Parameters
[in]numEvent counter (0-30) to configure
[in]typeEvent to count

Definition at line 216 of file pmu_armv8.h.

References __STATIC_INLINE.