20#ifndef STM32H7xx_HAL_DMA_EX_H
21#define STM32H7xx_HAL_DMA_EX_H
109#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U
110#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U
111#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U
112#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U
113#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U
114#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U
115#define HAL_DMAMUX1_SYNC_EXTI0 6U
116#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U
118#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U
119#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U
120#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U
121#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U
122#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U
123#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U
124#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U
125#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U
126#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U
127#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U
128#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U
129#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U
130#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U
131#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U
132#define HAL_DMAMUX2_SYNC_EXTI0 14U
133#define HAL_DMAMUX2_SYNC_EXTI2 15U
143#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U
144#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0
145#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1
146#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL
157#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U
158#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U
159#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U
160#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U
161#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U
162#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U
163#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U
164#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U
166#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U
167#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U
168#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U
169#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U
170#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U
171#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U
172#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U
173#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U
174#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U
175#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U
176#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U
177#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U
178#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U
180#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U
183#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U
185#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U
186#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U
187#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U
188#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U
189#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U
190#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U
191#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U
192#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U
193#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U
194#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U
195#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U
197#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U
198#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U
200#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U
201#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U
212#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
213#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0
214#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1
215#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL
259#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
260#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
262#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
264#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
265 ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
266 ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
267 ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
269#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
271#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
274#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
275#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
277#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
279#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
280 ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
281 ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
282 ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
HAL_DMA_MemoryTypeDef
HAL DMA Memory definition.
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
HAL DMAMUX request generator parameters structure definition.
uint32_t Polarity
Specifies the polarity of the signal on which the request is generated.
uint32_t RequestNumber
Specifies the number of DMA request that will be generated after a signal event.
uint32_t SignalID
Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of DMA...
HAL DMAMUX Synchronization configuration structure definition.
uint32_t RequestNumber
Specifies the number of DMA request that will be authorized after a sync event.
FunctionalState EventEnable
Specifies if an event shall be generated once the RequestNumber is reached.
FunctionalState SyncEnable
Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABL...
uint32_t SyncSignalID
Specifies the synchronization signal gating the DMA request in periodic mode.
uint32_t SyncPolarity
Specifies the polarity of the signal on which the DMA request is synchronized.