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stm32h7xx_ll_dma.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_DMA_H
21#define STM32H7xx_LL_DMA_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29#include "stm32h7xx_ll_dmamux.h"
30
31/** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35#if defined (DMA1) || defined (DMA2)
36
37/** @defgroup DMA_LL DMA
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
47static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
48{
49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
57};
58
59
60/**
61 * @}
62 */
63
64/* Private macros ------------------------------------------------------------*/
65/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros
66 * @{
67 */
68/**
69 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
70 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
71 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
72 * @param __DMA_INSTANCE__ DMAx
73 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
74 */
75#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
76(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
77/**
78 * @}
79 */
80
81/* Exported types ------------------------------------------------------------*/
82#if defined(USE_FULL_LL_DRIVER)
83/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
84 * @{
85 */
86typedef struct
87{
88 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
89 or as Source base address in case of memory to memory transfer direction.
90
91 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
92
93 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
94 or as Destination base address in case of memory to memory transfer direction.
95
96 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
97
98 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
99 from memory to memory or from peripheral to memory.
100 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
101
102 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
103
104 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
105 This parameter can be a value of @ref DMA_LL_EC_MODE
106 @note The circular buffer mode cannot be used if the memory to memory
107 data transfer direction is configured on the selected Stream
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
110
111 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
112 is incremented or not.
113 This parameter can be a value of @ref DMA_LL_EC_PERIPH
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
116
117 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
118 is incremented or not.
119 This parameter can be a value of @ref DMA_LL_EC_MEMORY
120
121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
122
123 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
124 in case of memory to memory transfer direction.
125 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
126
127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
128
129 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
130 in case of memory to memory transfer direction.
131 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
132
133 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
134
135 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
136 The data unit is equal to the source buffer configuration set in PeripheralSize
137 or MemorySize parameters depending in the transfer direction.
138 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
139
140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
141
142 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
143 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
144
145 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
146
147 uint32_t Priority; /*!< Specifies the channel priority level.
148 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
149
150 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
151
152 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
153 This parameter can be a value of @ref DMA_LL_FIFOMODE
154 @note The Direct mode (FIFO mode disabled) cannot be used if the
155 memory-to-memory data transfer is configured on the selected stream
156
157 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
158
159 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
160 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
161
162 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
163
164 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
165 It specifies the amount of data to be transferred in a single non interruptible
166 transaction.
167 This parameter can be a value of @ref DMA_LL_EC_MBURST
168 @note The burst mode is possible only if the address Increment mode is enabled.
169
170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
171
172 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
173 It specifies the amount of data to be transferred in a single non interruptible
174 transaction.
175 This parameter can be a value of @ref DMA_LL_EC_PBURST
176 @note The burst mode is possible only if the address Increment mode is enabled.
177
178 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
179
180 uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
181 This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE
182
183 This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */
184
185 uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
186 This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM
187
188 This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */
189} LL_DMA_InitTypeDef;
190/**
191 * @}
192 */
193#endif /*USE_FULL_LL_DRIVER*/
194/* Exported constants --------------------------------------------------------*/
195/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
196 * @{
197 */
198
199/** @defgroup DMA_LL_EC_STREAM STREAM
200 * @{
201 */
202#define LL_DMA_STREAM_0 0x00000000U
203#define LL_DMA_STREAM_1 0x00000001U
204#define LL_DMA_STREAM_2 0x00000002U
205#define LL_DMA_STREAM_3 0x00000003U
206#define LL_DMA_STREAM_4 0x00000004U
207#define LL_DMA_STREAM_5 0x00000005U
208#define LL_DMA_STREAM_6 0x00000006U
209#define LL_DMA_STREAM_7 0x00000007U
210#define LL_DMA_STREAM_ALL 0xFFFF0000U
211/**
212 * @}
213 */
214
215
216/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
217 * @{
218 */
219#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
220#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
221#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
222/**
223 * @}
224 */
225
226/** @defgroup DMA_LL_EC_MODE MODE
227 * @{
228 */
229#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
230#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
231#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
232/**
233 * @}
234 */
235
236/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
237 * @{
238 */
239#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
240#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
241/**
242 * @}
243 */
244
245/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
246 * @{
247 */
248#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
249#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
250/**
251 * @}
252 */
253
254/** @defgroup DMA_LL_EC_PERIPH PERIPH
255 * @{
256 */
257#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
258#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
259/**
260 * @}
261 */
262
263/** @defgroup DMA_LL_EC_MEMORY MEMORY
264 * @{
265 */
266#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
267#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
268/**
269 * @}
270 */
271
272/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
273 * @{
274 */
275#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
276#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
277#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
278/**
279 * @}
280 */
281
282/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
283 * @{
284 */
285#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
286#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
287#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
288/**
289 * @}
290 */
291
292/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
293 * @{
294 */
295#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
296#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
297/**
298 * @}
299 */
300
301/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
302 * @{
303 */
304#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
305#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
306#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
307#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
308/**
309 * @}
310 */
311
312
313/** @defgroup DMA_LL_EC_MBURST MBURST
314 * @{
315 */
316#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
317#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
318#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
319#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
320/**
321 * @}
322 */
323
324/** @defgroup DMA_LL_EC_PBURST PBURST
325 * @{
326 */
327#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
328#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
329#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
330#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
331/**
332 * @}
333 */
334
335/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
336 * @{
337 */
338#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
339#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
340/**
341 * @}
342 */
343
344/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
345 * @{
346 */
347#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
348#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
349#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
350#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
351#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
352#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
353/**
354 * @}
355 */
356
357/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
358 * @{
359 */
360#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
361#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
362#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
363#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
364/**
365 * @}
366 */
367
368/**
369 * @}
370 */
371
372/* Exported macro ------------------------------------------------------------*/
373/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
374 * @{
375 */
376
377/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
378 * @{
379 */
380/**
381 * @brief Write a value in DMA register
382 * @param __INSTANCE__ DMA Instance
383 * @param __REG__ Register to be written
384 * @param __VALUE__ Value to be written in the register
385 * @retval None
386 */
387#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
388
389/**
390 * @brief Read a value in DMA register
391 * @param __INSTANCE__ DMA Instance
392 * @param __REG__ Register to be read
393 * @retval Register value
394 */
395#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
396/**
397 * @}
398 */
399
400/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
401 * @{
402 */
403/**
404 * @brief Convert DMAx_Streamy into DMAx
405 * @param __STREAM_INSTANCE__ DMAx_Streamy
406 * @retval DMAx
407 */
408#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
409(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
410
411/**
412 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
413 * @param __STREAM_INSTANCE__ DMAx_Streamy
414 * @retval LL_DMA_STREAM_y
415 */
416#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
417(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
418 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
419 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
420 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
421 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
422 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
423 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
424 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
425 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
426 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
428 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
429 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
431 LL_DMA_STREAM_7)
432
433/**
434 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
435 * @param __DMA_INSTANCE__ DMAx
436 * @param __STREAM__ LL_DMA_STREAM_y
437 * @retval DMAx_Streamy
438 */
439#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
440((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
455 DMA2_Stream7)
456
457/**
458 * @}
459 */
460
461/**
462 * @}
463 */
464
465
466/* Exported functions --------------------------------------------------------*/
467/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
468 * @{
469 */
470
471/** @defgroup DMA_LL_EF_Configuration Configuration
472 * @{
473 */
474/**
475 * @brief Enable DMA stream.
476 * @rmtoll CR EN LL_DMA_EnableStream
477 * @param DMAx DMAx Instance
478 * @param Stream This parameter can be one of the following values:
479 * @arg @ref LL_DMA_STREAM_0
480 * @arg @ref LL_DMA_STREAM_1
481 * @arg @ref LL_DMA_STREAM_2
482 * @arg @ref LL_DMA_STREAM_3
483 * @arg @ref LL_DMA_STREAM_4
484 * @arg @ref LL_DMA_STREAM_5
485 * @arg @ref LL_DMA_STREAM_6
486 * @arg @ref LL_DMA_STREAM_7
487 * @retval None
488 */
489__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream)
490{
491 uint32_t dma_base_addr = (uint32_t)DMAx;
492
493 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
494}
495
496/**
497 * @brief Disable DMA stream.
498 * @rmtoll CR EN LL_DMA_DisableStream
499 * @param DMAx DMAx Instance
500 * @param Stream This parameter can be one of the following values:
501 * @arg @ref LL_DMA_STREAM_0
502 * @arg @ref LL_DMA_STREAM_1
503 * @arg @ref LL_DMA_STREAM_2
504 * @arg @ref LL_DMA_STREAM_3
505 * @arg @ref LL_DMA_STREAM_4
506 * @arg @ref LL_DMA_STREAM_5
507 * @arg @ref LL_DMA_STREAM_6
508 * @arg @ref LL_DMA_STREAM_7
509 * @retval None
510 */
511__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream)
512{
513 uint32_t dma_base_addr = (uint32_t)DMAx;
514
515 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
516}
517
518/**
519 * @brief Check if DMA stream is enabled or disabled.
520 * @rmtoll CR EN LL_DMA_IsEnabledStream
521 * @param DMAx DMAx Instance
522 * @param Stream This parameter can be one of the following values:
523 * @arg @ref LL_DMA_STREAM_0
524 * @arg @ref LL_DMA_STREAM_1
525 * @arg @ref LL_DMA_STREAM_2
526 * @arg @ref LL_DMA_STREAM_3
527 * @arg @ref LL_DMA_STREAM_4
528 * @arg @ref LL_DMA_STREAM_5
529 * @arg @ref LL_DMA_STREAM_6
530 * @arg @ref LL_DMA_STREAM_7
531 * @retval State of bit (1 or 0).
532 */
533__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream)
534{
535 uint32_t dma_base_addr = (uint32_t)DMAx;
536
537 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
538}
539
540/**
541 * @brief Configure all parameters linked to DMA transfer.
542 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
543 * CR CIRC LL_DMA_ConfigTransfer\n
544 * CR PINC LL_DMA_ConfigTransfer\n
545 * CR MINC LL_DMA_ConfigTransfer\n
546 * CR PSIZE LL_DMA_ConfigTransfer\n
547 * CR MSIZE LL_DMA_ConfigTransfer\n
548 * CR PL LL_DMA_ConfigTransfer\n
549 * CR PFCTRL LL_DMA_ConfigTransfer\n
550 * CR DBM LL_DMA_ConfigTransfer\n
551 * CR CT LL_DMA_ConfigTransfer
552 * @param DMAx DMAx Instance
553 * @param Stream This parameter can be one of the following values:
554 * @arg @ref LL_DMA_STREAM_0
555 * @arg @ref LL_DMA_STREAM_1
556 * @arg @ref LL_DMA_STREAM_2
557 * @arg @ref LL_DMA_STREAM_3
558 * @arg @ref LL_DMA_STREAM_4
559 * @arg @ref LL_DMA_STREAM_5
560 * @arg @ref LL_DMA_STREAM_6
561 * @arg @ref LL_DMA_STREAM_7
562 * @param Configuration This parameter must be a combination of all the following values:
563 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
564 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
565 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
566 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
567 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
568 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
569 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
570 * @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE
571 * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1
572 *@retval None
573 */
574__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
575{
576 uint32_t dma_base_addr = (uint32_t)DMAx;
577
578 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
579 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \
580 DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration);
581}
582
583/**
584 * @brief Set Data transfer direction (read from peripheral or from memory).
585 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
586 * @param DMAx DMAx Instance
587 * @param Stream This parameter can be one of the following values:
588 * @arg @ref LL_DMA_STREAM_0
589 * @arg @ref LL_DMA_STREAM_1
590 * @arg @ref LL_DMA_STREAM_2
591 * @arg @ref LL_DMA_STREAM_3
592 * @arg @ref LL_DMA_STREAM_4
593 * @arg @ref LL_DMA_STREAM_5
594 * @arg @ref LL_DMA_STREAM_6
595 * @arg @ref LL_DMA_STREAM_7
596 * @param Direction This parameter can be one of the following values:
597 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
598 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
599 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
600 * @retval None
601 */
602__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
603{
604 uint32_t dma_base_addr = (uint32_t)DMAx;
605
606 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
607}
608
609/**
610 * @brief Get Data transfer direction (read from peripheral or from memory).
611 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
612 * @param DMAx DMAx Instance
613 * @param Stream This parameter can be one of the following values:
614 * @arg @ref LL_DMA_STREAM_0
615 * @arg @ref LL_DMA_STREAM_1
616 * @arg @ref LL_DMA_STREAM_2
617 * @arg @ref LL_DMA_STREAM_3
618 * @arg @ref LL_DMA_STREAM_4
619 * @arg @ref LL_DMA_STREAM_5
620 * @arg @ref LL_DMA_STREAM_6
621 * @arg @ref LL_DMA_STREAM_7
622 * @retval Returned value can be one of the following values:
623 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
624 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
625 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
626 */
627__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream)
628{
629 uint32_t dma_base_addr = (uint32_t)DMAx;
630
631 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
632}
633
634/**
635 * @brief Set DMA mode normal, circular or peripheral flow control.
636 * @rmtoll CR CIRC LL_DMA_SetMode\n
637 * CR PFCTRL LL_DMA_SetMode
638 * @param DMAx DMAx Instance
639 * @param Stream This parameter can be one of the following values:
640 * @arg @ref LL_DMA_STREAM_0
641 * @arg @ref LL_DMA_STREAM_1
642 * @arg @ref LL_DMA_STREAM_2
643 * @arg @ref LL_DMA_STREAM_3
644 * @arg @ref LL_DMA_STREAM_4
645 * @arg @ref LL_DMA_STREAM_5
646 * @arg @ref LL_DMA_STREAM_6
647 * @arg @ref LL_DMA_STREAM_7
648 * @param Mode This parameter can be one of the following values:
649 * @arg @ref LL_DMA_MODE_NORMAL
650 * @arg @ref LL_DMA_MODE_CIRCULAR
651 * @arg @ref LL_DMA_MODE_PFCTRL
652 * @retval None
653 */
654__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
655{
656 uint32_t dma_base_addr = (uint32_t)DMAx;
657
658 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
659}
660
661/**
662 * @brief Get DMA mode normal, circular or peripheral flow control.
663 * @rmtoll CR CIRC LL_DMA_GetMode\n
664 * CR PFCTRL LL_DMA_GetMode
665 * @param DMAx DMAx Instance
666 * @param Stream This parameter can be one of the following values:
667 * @arg @ref LL_DMA_STREAM_0
668 * @arg @ref LL_DMA_STREAM_1
669 * @arg @ref LL_DMA_STREAM_2
670 * @arg @ref LL_DMA_STREAM_3
671 * @arg @ref LL_DMA_STREAM_4
672 * @arg @ref LL_DMA_STREAM_5
673 * @arg @ref LL_DMA_STREAM_6
674 * @arg @ref LL_DMA_STREAM_7
675 * @retval Returned value can be one of the following values:
676 * @arg @ref LL_DMA_MODE_NORMAL
677 * @arg @ref LL_DMA_MODE_CIRCULAR
678 * @arg @ref LL_DMA_MODE_PFCTRL
679 */
680__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream)
681{
682 uint32_t dma_base_addr = (uint32_t)DMAx;
683
684 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
685}
686
687/**
688 * @brief Set Peripheral increment mode.
689 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
690 * @param DMAx DMAx Instance
691 * @param Stream This parameter can be one of the following values:
692 * @arg @ref LL_DMA_STREAM_0
693 * @arg @ref LL_DMA_STREAM_1
694 * @arg @ref LL_DMA_STREAM_2
695 * @arg @ref LL_DMA_STREAM_3
696 * @arg @ref LL_DMA_STREAM_4
697 * @arg @ref LL_DMA_STREAM_5
698 * @arg @ref LL_DMA_STREAM_6
699 * @arg @ref LL_DMA_STREAM_7
700 * @param IncrementMode This parameter can be one of the following values:
701 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
702 * @arg @ref LL_DMA_PERIPH_INCREMENT
703 * @retval None
704 */
705__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
706{
707 uint32_t dma_base_addr = (uint32_t)DMAx;
708
709 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
710}
711
712/**
713 * @brief Get Peripheral increment mode.
714 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
715 * @param DMAx DMAx Instance
716 * @param Stream This parameter can be one of the following values:
717 * @arg @ref LL_DMA_STREAM_0
718 * @arg @ref LL_DMA_STREAM_1
719 * @arg @ref LL_DMA_STREAM_2
720 * @arg @ref LL_DMA_STREAM_3
721 * @arg @ref LL_DMA_STREAM_4
722 * @arg @ref LL_DMA_STREAM_5
723 * @arg @ref LL_DMA_STREAM_6
724 * @arg @ref LL_DMA_STREAM_7
725 * @retval Returned value can be one of the following values:
726 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
727 * @arg @ref LL_DMA_PERIPH_INCREMENT
728 */
729__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream)
730{
731 uint32_t dma_base_addr = (uint32_t)DMAx;
732
733 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
734}
735
736/**
737 * @brief Set Memory increment mode.
738 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
739 * @param DMAx DMAx Instance
740 * @param Stream This parameter can be one of the following values:
741 * @arg @ref LL_DMA_STREAM_0
742 * @arg @ref LL_DMA_STREAM_1
743 * @arg @ref LL_DMA_STREAM_2
744 * @arg @ref LL_DMA_STREAM_3
745 * @arg @ref LL_DMA_STREAM_4
746 * @arg @ref LL_DMA_STREAM_5
747 * @arg @ref LL_DMA_STREAM_6
748 * @arg @ref LL_DMA_STREAM_7
749 * @param IncrementMode This parameter can be one of the following values:
750 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
751 * @arg @ref LL_DMA_MEMORY_INCREMENT
752 * @retval None
753 */
754__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
755{
756 uint32_t dma_base_addr = (uint32_t)DMAx;
757
758 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
759}
760
761/**
762 * @brief Get Memory increment mode.
763 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
764 * @param DMAx DMAx Instance
765 * @param Stream This parameter can be one of the following values:
766 * @arg @ref LL_DMA_STREAM_0
767 * @arg @ref LL_DMA_STREAM_1
768 * @arg @ref LL_DMA_STREAM_2
769 * @arg @ref LL_DMA_STREAM_3
770 * @arg @ref LL_DMA_STREAM_4
771 * @arg @ref LL_DMA_STREAM_5
772 * @arg @ref LL_DMA_STREAM_6
773 * @arg @ref LL_DMA_STREAM_7
774 * @retval Returned value can be one of the following values:
775 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
776 * @arg @ref LL_DMA_MEMORY_INCREMENT
777 */
778__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream)
779{
780 uint32_t dma_base_addr = (uint32_t)DMAx;
781
782 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
783}
784
785/**
786 * @brief Set Peripheral size.
787 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
788 * @param DMAx DMAx Instance
789 * @param Stream This parameter can be one of the following values:
790 * @arg @ref LL_DMA_STREAM_0
791 * @arg @ref LL_DMA_STREAM_1
792 * @arg @ref LL_DMA_STREAM_2
793 * @arg @ref LL_DMA_STREAM_3
794 * @arg @ref LL_DMA_STREAM_4
795 * @arg @ref LL_DMA_STREAM_5
796 * @arg @ref LL_DMA_STREAM_6
797 * @arg @ref LL_DMA_STREAM_7
798 * @param Size This parameter can be one of the following values:
799 * @arg @ref LL_DMA_PDATAALIGN_BYTE
800 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
801 * @arg @ref LL_DMA_PDATAALIGN_WORD
802 * @retval None
803 */
804__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
805{
806 uint32_t dma_base_addr = (uint32_t)DMAx;
807
808 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
809}
810
811/**
812 * @brief Get Peripheral size.
813 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
814 * @param DMAx DMAx Instance
815 * @param Stream This parameter can be one of the following values:
816 * @arg @ref LL_DMA_STREAM_0
817 * @arg @ref LL_DMA_STREAM_1
818 * @arg @ref LL_DMA_STREAM_2
819 * @arg @ref LL_DMA_STREAM_3
820 * @arg @ref LL_DMA_STREAM_4
821 * @arg @ref LL_DMA_STREAM_5
822 * @arg @ref LL_DMA_STREAM_6
823 * @arg @ref LL_DMA_STREAM_7
824 * @retval Returned value can be one of the following values:
825 * @arg @ref LL_DMA_PDATAALIGN_BYTE
826 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
827 * @arg @ref LL_DMA_PDATAALIGN_WORD
828 */
829__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream)
830{
831 uint32_t dma_base_addr = (uint32_t)DMAx;
832
833 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
834}
835
836/**
837 * @brief Set Memory size.
838 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
839 * @param DMAx DMAx Instance
840 * @param Stream This parameter can be one of the following values:
841 * @arg @ref LL_DMA_STREAM_0
842 * @arg @ref LL_DMA_STREAM_1
843 * @arg @ref LL_DMA_STREAM_2
844 * @arg @ref LL_DMA_STREAM_3
845 * @arg @ref LL_DMA_STREAM_4
846 * @arg @ref LL_DMA_STREAM_5
847 * @arg @ref LL_DMA_STREAM_6
848 * @arg @ref LL_DMA_STREAM_7
849 * @param Size This parameter can be one of the following values:
850 * @arg @ref LL_DMA_MDATAALIGN_BYTE
851 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
852 * @arg @ref LL_DMA_MDATAALIGN_WORD
853 * @retval None
854 */
855__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
856{
857 uint32_t dma_base_addr = (uint32_t)DMAx;
858
859 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
860}
861
862/**
863 * @brief Get Memory size.
864 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
865 * @param DMAx DMAx Instance
866 * @param Stream This parameter can be one of the following values:
867 * @arg @ref LL_DMA_STREAM_0
868 * @arg @ref LL_DMA_STREAM_1
869 * @arg @ref LL_DMA_STREAM_2
870 * @arg @ref LL_DMA_STREAM_3
871 * @arg @ref LL_DMA_STREAM_4
872 * @arg @ref LL_DMA_STREAM_5
873 * @arg @ref LL_DMA_STREAM_6
874 * @arg @ref LL_DMA_STREAM_7
875 * @retval Returned value can be one of the following values:
876 * @arg @ref LL_DMA_MDATAALIGN_BYTE
877 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
878 * @arg @ref LL_DMA_MDATAALIGN_WORD
879 */
880__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream)
881{
882 uint32_t dma_base_addr = (uint32_t)DMAx;
883
884 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
885}
886
887/**
888 * @brief Set Peripheral increment offset size.
889 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
890 * @param DMAx DMAx Instance
891 * @param Stream This parameter can be one of the following values:
892 * @arg @ref LL_DMA_STREAM_0
893 * @arg @ref LL_DMA_STREAM_1
894 * @arg @ref LL_DMA_STREAM_2
895 * @arg @ref LL_DMA_STREAM_3
896 * @arg @ref LL_DMA_STREAM_4
897 * @arg @ref LL_DMA_STREAM_5
898 * @arg @ref LL_DMA_STREAM_6
899 * @arg @ref LL_DMA_STREAM_7
900 * @param OffsetSize This parameter can be one of the following values:
901 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
902 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
903 * @retval None
904 */
905__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
906{
907 uint32_t dma_base_addr = (uint32_t)DMAx;
908
909 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
910}
911
912/**
913 * @brief Get Peripheral increment offset size.
914 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
915 * @param DMAx DMAx Instance
916 * @param Stream This parameter can be one of the following values:
917 * @arg @ref LL_DMA_STREAM_0
918 * @arg @ref LL_DMA_STREAM_1
919 * @arg @ref LL_DMA_STREAM_2
920 * @arg @ref LL_DMA_STREAM_3
921 * @arg @ref LL_DMA_STREAM_4
922 * @arg @ref LL_DMA_STREAM_5
923 * @arg @ref LL_DMA_STREAM_6
924 * @arg @ref LL_DMA_STREAM_7
925 * @retval Returned value can be one of the following values:
926 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
927 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
928 */
929__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream)
930{
931 uint32_t dma_base_addr = (uint32_t)DMAx;
932
933 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
934}
935
936/**
937 * @brief Set Stream priority level.
938 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
939 * @param DMAx DMAx Instance
940 * @param Stream This parameter can be one of the following values:
941 * @arg @ref LL_DMA_STREAM_0
942 * @arg @ref LL_DMA_STREAM_1
943 * @arg @ref LL_DMA_STREAM_2
944 * @arg @ref LL_DMA_STREAM_3
945 * @arg @ref LL_DMA_STREAM_4
946 * @arg @ref LL_DMA_STREAM_5
947 * @arg @ref LL_DMA_STREAM_6
948 * @arg @ref LL_DMA_STREAM_7
949 * @param Priority This parameter can be one of the following values:
950 * @arg @ref LL_DMA_PRIORITY_LOW
951 * @arg @ref LL_DMA_PRIORITY_MEDIUM
952 * @arg @ref LL_DMA_PRIORITY_HIGH
953 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
954 * @retval None
955 */
956__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
957{
958 uint32_t dma_base_addr = (uint32_t)DMAx;
959
960 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
961}
962
963/**
964 * @brief Get Stream priority level.
965 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
966 * @param DMAx DMAx Instance
967 * @param Stream This parameter can be one of the following values:
968 * @arg @ref LL_DMA_STREAM_0
969 * @arg @ref LL_DMA_STREAM_1
970 * @arg @ref LL_DMA_STREAM_2
971 * @arg @ref LL_DMA_STREAM_3
972 * @arg @ref LL_DMA_STREAM_4
973 * @arg @ref LL_DMA_STREAM_5
974 * @arg @ref LL_DMA_STREAM_6
975 * @arg @ref LL_DMA_STREAM_7
976 * @retval Returned value can be one of the following values:
977 * @arg @ref LL_DMA_PRIORITY_LOW
978 * @arg @ref LL_DMA_PRIORITY_MEDIUM
979 * @arg @ref LL_DMA_PRIORITY_HIGH
980 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
981 */
982__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream)
983{
984 uint32_t dma_base_addr = (uint32_t)DMAx;
985
986 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
987}
988
989/**
990 * @brief Enable DMA stream bufferable transfer.
991 * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer
992 * @param DMAx DMAx Instance
993 * @param Stream This parameter can be one of the following values:
994 * @arg @ref LL_DMA_STREAM_0
995 * @arg @ref LL_DMA_STREAM_1
996 * @arg @ref LL_DMA_STREAM_2
997 * @arg @ref LL_DMA_STREAM_3
998 * @arg @ref LL_DMA_STREAM_4
999 * @arg @ref LL_DMA_STREAM_5
1000 * @arg @ref LL_DMA_STREAM_6
1001 * @arg @ref LL_DMA_STREAM_7
1002 * @retval None
1003 */
1004__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream)
1005{
1006 uint32_t dma_base_addr = (uint32_t)DMAx;
1007
1008 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
1009}
1010
1011/**
1012 * @brief Disable DMA stream bufferable transfer.
1013 * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer
1014 * @param DMAx DMAx Instance
1015 * @param Stream This parameter can be one of the following values:
1016 * @arg @ref LL_DMA_STREAM_0
1017 * @arg @ref LL_DMA_STREAM_1
1018 * @arg @ref LL_DMA_STREAM_2
1019 * @arg @ref LL_DMA_STREAM_3
1020 * @arg @ref LL_DMA_STREAM_4
1021 * @arg @ref LL_DMA_STREAM_5
1022 * @arg @ref LL_DMA_STREAM_6
1023 * @arg @ref LL_DMA_STREAM_7
1024 * @retval None
1025 */
1026__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream)
1027{
1028 uint32_t dma_base_addr = (uint32_t)DMAx;
1029
1030 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
1031}
1032
1033/**
1034 * @brief Set Number of data to transfer.
1035 * @rmtoll NDTR NDT LL_DMA_SetDataLength
1036 * @note This action has no effect if
1037 * stream is enabled.
1038 * @param DMAx DMAx Instance
1039 * @param Stream This parameter can be one of the following values:
1040 * @arg @ref LL_DMA_STREAM_0
1041 * @arg @ref LL_DMA_STREAM_1
1042 * @arg @ref LL_DMA_STREAM_2
1043 * @arg @ref LL_DMA_STREAM_3
1044 * @arg @ref LL_DMA_STREAM_4
1045 * @arg @ref LL_DMA_STREAM_5
1046 * @arg @ref LL_DMA_STREAM_6
1047 * @arg @ref LL_DMA_STREAM_7
1048 * @param NbData Between 0 to 0xFFFFFFFF
1049 * @retval None
1050 */
1051__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
1052{
1053 uint32_t dma_base_addr = (uint32_t)DMAx;
1054
1055 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
1056}
1057
1058/**
1059 * @brief Get Number of data to transfer.
1060 * @rmtoll NDTR NDT LL_DMA_GetDataLength
1061 * @note Once the stream is enabled, the return value indicate the
1062 * remaining bytes to be transmitted.
1063 * @param DMAx DMAx Instance
1064 * @param Stream This parameter can be one of the following values:
1065 * @arg @ref LL_DMA_STREAM_0
1066 * @arg @ref LL_DMA_STREAM_1
1067 * @arg @ref LL_DMA_STREAM_2
1068 * @arg @ref LL_DMA_STREAM_3
1069 * @arg @ref LL_DMA_STREAM_4
1070 * @arg @ref LL_DMA_STREAM_5
1071 * @arg @ref LL_DMA_STREAM_6
1072 * @arg @ref LL_DMA_STREAM_7
1073 * @retval Between 0 to 0xFFFFFFFF
1074 */
1075__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream)
1076{
1077 uint32_t dma_base_addr = (uint32_t)DMAx;
1078
1079 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
1080}
1081/**
1082 * @brief Set DMA request for DMA Streams on DMAMUX Channel x.
1083 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1084 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1085 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1086 * @param DMAx DMAx Instance
1087 * @param Stream This parameter can be one of the following values:
1088 * @arg @ref LL_DMA_STREAM_0
1089 * @arg @ref LL_DMA_STREAM_1
1090 * @arg @ref LL_DMA_STREAM_2
1091 * @arg @ref LL_DMA_STREAM_3
1092 * @arg @ref LL_DMA_STREAM_4
1093 * @arg @ref LL_DMA_STREAM_5
1094 * @arg @ref LL_DMA_STREAM_6
1095 * @arg @ref LL_DMA_STREAM_7
1096 * @param Request This parameter can be one of the following values:
1097 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1098 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1099 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1100 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1101 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1102 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1103 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1104 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1105 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1106 * @arg @ref LL_DMAMUX1_REQ_ADC1
1107 * @arg @ref LL_DMAMUX1_REQ_ADC2
1108 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1109 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1110 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1111 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1112 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1113 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1114 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1115 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1116 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1117 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1118 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1119 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1120 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1121 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1122 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1123 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1124 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1125 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1126 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1127 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1128 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1129 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1130 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1131 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1132 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1133 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1134 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1135 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1136 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1137 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1138 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1139 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1140 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1141 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1142 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1143 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1144 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1145 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1146 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1147 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1148 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1149 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1150 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1151 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1152 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1153 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1154 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1155 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1156 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1157 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1158 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1159 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1160 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1161 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1162 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1163 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1164 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1165 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1166 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1167 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1168 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1169 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1170 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1171 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
1172 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1173 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1174 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1175 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1176 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1177 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1178 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1179 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1180 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1181 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1182 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1183 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1184 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1185 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
1186 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
1187 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1188 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1189 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1190 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1191 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1192 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1193 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1194 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1195 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1196 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1197 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1198 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1199 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1200 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1201 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1202 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1203 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1204 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1205 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1206 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1207 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1208 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1209 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1210 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1211 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1212 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1213 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
1214 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1215 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
1216 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
1217 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
1218 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
1219 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
1220 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
1221 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
1222 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
1223 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
1224 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
1225 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
1226 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
1227 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
1228 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
1229 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
1230 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
1231 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
1232 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
1233 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
1234 *
1235 * @note (*) Availability depends on devices.
1236 * @retval None
1237 */
1238__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
1239{
1240 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1241}
1242
1243/**
1244 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1245 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1246 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1247 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1248 * @param DMAx DMAx Instance
1249 * @param Stream This parameter can be one of the following values:
1250 * @arg @ref LL_DMA_STREAM_0
1251 * @arg @ref LL_DMA_STREAM_1
1252 * @arg @ref LL_DMA_STREAM_2
1253 * @arg @ref LL_DMA_STREAM_3
1254 * @arg @ref LL_DMA_STREAM_4
1255 * @arg @ref LL_DMA_STREAM_5
1256 * @arg @ref LL_DMA_STREAM_6
1257 * @arg @ref LL_DMA_STREAM_7
1258 * @retval Returned value can be one of the following values:
1259 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1260 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1261 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1262 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1263 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1264 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1265 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1266 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1267 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1268 * @arg @ref LL_DMAMUX1_REQ_ADC1
1269 * @arg @ref LL_DMAMUX1_REQ_ADC2
1270 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1271 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1272 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1273 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1274 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1275 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1276 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1277 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1278 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1279 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1280 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1281 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1282 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1283 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1284 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1285 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1286 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1287 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1288 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1289 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1290 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1291 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1292 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1293 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1294 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1295 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1296 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1297 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1298 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1299 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1300 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1301 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1302 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1303 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1304 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1305 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1306 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1307 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1308 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1309 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1310 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1311 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1312 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1313 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1314 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1315 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1316 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1317 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1318 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1319 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1320 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1321 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1322 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1323 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1324 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1325 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1326 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1327 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1328 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1329 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1330 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1331 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1332 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1333 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
1334 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1335 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1336 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1337 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1338 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1339 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1340 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1341 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1342 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1343 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1344 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1345 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1346 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1347 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
1348 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
1349 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1350 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1351 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1352 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1353 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1354 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1355 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1356 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1357 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1358 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1359 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1360 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1361 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1362 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1363 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1364 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1365 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1366 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1367 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1368 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1369 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1370 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1371 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1372 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1373 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1374 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1375 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
1376 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1377 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
1378 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
1379 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
1380 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
1381 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
1382 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
1383 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
1384 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
1385 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
1386 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
1387 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
1388 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
1389 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
1390 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
1391 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
1392 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
1393 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
1394 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
1395 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
1396 *
1397 * @note (*) Availability depends on devices.
1398 */
1399__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream)
1400{
1401 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1402}
1403
1404/**
1405 * @brief Set Memory burst transfer configuration.
1406 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1407 * @param DMAx DMAx Instance
1408 * @param Stream This parameter can be one of the following values:
1409 * @arg @ref LL_DMA_STREAM_0
1410 * @arg @ref LL_DMA_STREAM_1
1411 * @arg @ref LL_DMA_STREAM_2
1412 * @arg @ref LL_DMA_STREAM_3
1413 * @arg @ref LL_DMA_STREAM_4
1414 * @arg @ref LL_DMA_STREAM_5
1415 * @arg @ref LL_DMA_STREAM_6
1416 * @arg @ref LL_DMA_STREAM_7
1417 * @param Mburst This parameter can be one of the following values:
1418 * @arg @ref LL_DMA_MBURST_SINGLE
1419 * @arg @ref LL_DMA_MBURST_INC4
1420 * @arg @ref LL_DMA_MBURST_INC8
1421 * @arg @ref LL_DMA_MBURST_INC16
1422 * @retval None
1423 */
1424__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1425{
1426 uint32_t dma_base_addr = (uint32_t)DMAx;
1427
1428 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
1429}
1430
1431/**
1432 * @brief Get Memory burst transfer configuration.
1433 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1434 * @param DMAx DMAx Instance
1435 * @param Stream This parameter can be one of the following values:
1436 * @arg @ref LL_DMA_STREAM_0
1437 * @arg @ref LL_DMA_STREAM_1
1438 * @arg @ref LL_DMA_STREAM_2
1439 * @arg @ref LL_DMA_STREAM_3
1440 * @arg @ref LL_DMA_STREAM_4
1441 * @arg @ref LL_DMA_STREAM_5
1442 * @arg @ref LL_DMA_STREAM_6
1443 * @arg @ref LL_DMA_STREAM_7
1444 * @retval Returned value can be one of the following values:
1445 * @arg @ref LL_DMA_MBURST_SINGLE
1446 * @arg @ref LL_DMA_MBURST_INC4
1447 * @arg @ref LL_DMA_MBURST_INC8
1448 * @arg @ref LL_DMA_MBURST_INC16
1449 */
1450__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream)
1451{
1452 uint32_t dma_base_addr = (uint32_t)DMAx;
1453
1454 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
1455}
1456
1457/**
1458 * @brief Set Peripheral burst transfer configuration.
1459 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1460 * @param DMAx DMAx Instance
1461 * @param Stream This parameter can be one of the following values:
1462 * @arg @ref LL_DMA_STREAM_0
1463 * @arg @ref LL_DMA_STREAM_1
1464 * @arg @ref LL_DMA_STREAM_2
1465 * @arg @ref LL_DMA_STREAM_3
1466 * @arg @ref LL_DMA_STREAM_4
1467 * @arg @ref LL_DMA_STREAM_5
1468 * @arg @ref LL_DMA_STREAM_6
1469 * @arg @ref LL_DMA_STREAM_7
1470 * @param Pburst This parameter can be one of the following values:
1471 * @arg @ref LL_DMA_PBURST_SINGLE
1472 * @arg @ref LL_DMA_PBURST_INC4
1473 * @arg @ref LL_DMA_PBURST_INC8
1474 * @arg @ref LL_DMA_PBURST_INC16
1475 * @retval None
1476 */
1477__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1478{
1479 uint32_t dma_base_addr = (uint32_t)DMAx;
1480
1481 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
1482}
1483
1484/**
1485 * @brief Get Peripheral burst transfer configuration.
1486 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1487 * @param DMAx DMAx Instance
1488 * @param Stream This parameter can be one of the following values:
1489 * @arg @ref LL_DMA_STREAM_0
1490 * @arg @ref LL_DMA_STREAM_1
1491 * @arg @ref LL_DMA_STREAM_2
1492 * @arg @ref LL_DMA_STREAM_3
1493 * @arg @ref LL_DMA_STREAM_4
1494 * @arg @ref LL_DMA_STREAM_5
1495 * @arg @ref LL_DMA_STREAM_6
1496 * @arg @ref LL_DMA_STREAM_7
1497 * @retval Returned value can be one of the following values:
1498 * @arg @ref LL_DMA_PBURST_SINGLE
1499 * @arg @ref LL_DMA_PBURST_INC4
1500 * @arg @ref LL_DMA_PBURST_INC8
1501 * @arg @ref LL_DMA_PBURST_INC16
1502 */
1503__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream)
1504{
1505 uint32_t dma_base_addr = (uint32_t)DMAx;
1506
1507 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
1508}
1509
1510/**
1511 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1512 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1513 * @param DMAx DMAx Instance
1514 * @param Stream This parameter can be one of the following values:
1515 * @arg @ref LL_DMA_STREAM_0
1516 * @arg @ref LL_DMA_STREAM_1
1517 * @arg @ref LL_DMA_STREAM_2
1518 * @arg @ref LL_DMA_STREAM_3
1519 * @arg @ref LL_DMA_STREAM_4
1520 * @arg @ref LL_DMA_STREAM_5
1521 * @arg @ref LL_DMA_STREAM_6
1522 * @arg @ref LL_DMA_STREAM_7
1523 * @param CurrentMemory This parameter can be one of the following values:
1524 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1525 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1526 * @retval None
1527 */
1528__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1529{
1530 uint32_t dma_base_addr = (uint32_t)DMAx;
1531
1532 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
1533}
1534
1535/**
1536 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1537 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1538 * @param DMAx DMAx Instance
1539 * @param Stream This parameter can be one of the following values:
1540 * @arg @ref LL_DMA_STREAM_0
1541 * @arg @ref LL_DMA_STREAM_1
1542 * @arg @ref LL_DMA_STREAM_2
1543 * @arg @ref LL_DMA_STREAM_3
1544 * @arg @ref LL_DMA_STREAM_4
1545 * @arg @ref LL_DMA_STREAM_5
1546 * @arg @ref LL_DMA_STREAM_6
1547 * @arg @ref LL_DMA_STREAM_7
1548 * @retval Returned value can be one of the following values:
1549 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1550 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1551 */
1552__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream)
1553{
1554 uint32_t dma_base_addr = (uint32_t)DMAx;
1555
1556 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
1557}
1558
1559/**
1560 * @brief Enable the double buffer mode.
1561 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1562 * @param DMAx DMAx Instance
1563 * @param Stream This parameter can be one of the following values:
1564 * @arg @ref LL_DMA_STREAM_0
1565 * @arg @ref LL_DMA_STREAM_1
1566 * @arg @ref LL_DMA_STREAM_2
1567 * @arg @ref LL_DMA_STREAM_3
1568 * @arg @ref LL_DMA_STREAM_4
1569 * @arg @ref LL_DMA_STREAM_5
1570 * @arg @ref LL_DMA_STREAM_6
1571 * @arg @ref LL_DMA_STREAM_7
1572 * @retval None
1573 */
1574__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream)
1575{
1576 uint32_t dma_base_addr = (uint32_t)DMAx;
1577
1578 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1579}
1580
1581/**
1582 * @brief Disable the double buffer mode.
1583 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1584 * @param DMAx DMAx Instance
1585 * @param Stream This parameter can be one of the following values:
1586 * @arg @ref LL_DMA_STREAM_0
1587 * @arg @ref LL_DMA_STREAM_1
1588 * @arg @ref LL_DMA_STREAM_2
1589 * @arg @ref LL_DMA_STREAM_3
1590 * @arg @ref LL_DMA_STREAM_4
1591 * @arg @ref LL_DMA_STREAM_5
1592 * @arg @ref LL_DMA_STREAM_6
1593 * @arg @ref LL_DMA_STREAM_7
1594 * @retval None
1595 */
1596__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream)
1597{
1598 uint32_t dma_base_addr = (uint32_t)DMAx;
1599
1600 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1601}
1602
1603/**
1604 * @brief Check if double buffer mode is enabled or not.
1605 * @rmtoll CR DBM LL_DMA_IsEnabledDoubleBufferMode
1606 * @param DMAx DMAx Instance
1607 * @param Stream This parameter can be one of the following values:
1608 * @arg @ref LL_DMA_STREAM_0
1609 * @arg @ref LL_DMA_STREAM_1
1610 * @arg @ref LL_DMA_STREAM_2
1611 * @arg @ref LL_DMA_STREAM_3
1612 * @arg @ref LL_DMA_STREAM_4
1613 * @arg @ref LL_DMA_STREAM_5
1614 * @arg @ref LL_DMA_STREAM_6
1615 * @arg @ref LL_DMA_STREAM_7
1616 * @retval State of bit (1 or 0).
1617 */
1618__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream)
1619{
1620 uint32_t dma_base_addr = (uint32_t)DMAx;
1621
1622 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL);
1623}
1624
1625/**
1626 * @brief Get FIFO status.
1627 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1628 * @param DMAx DMAx Instance
1629 * @param Stream This parameter can be one of the following values:
1630 * @arg @ref LL_DMA_STREAM_0
1631 * @arg @ref LL_DMA_STREAM_1
1632 * @arg @ref LL_DMA_STREAM_2
1633 * @arg @ref LL_DMA_STREAM_3
1634 * @arg @ref LL_DMA_STREAM_4
1635 * @arg @ref LL_DMA_STREAM_5
1636 * @arg @ref LL_DMA_STREAM_6
1637 * @arg @ref LL_DMA_STREAM_7
1638 * @retval Returned value can be one of the following values:
1639 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1640 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1641 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1642 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1643 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1644 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1645 */
1646__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream)
1647{
1648 uint32_t dma_base_addr = (uint32_t)DMAx;
1649
1650 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
1651}
1652
1653/**
1654 * @brief Disable Fifo mode.
1655 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1656 * @param DMAx DMAx Instance
1657 * @param Stream This parameter can be one of the following values:
1658 * @arg @ref LL_DMA_STREAM_0
1659 * @arg @ref LL_DMA_STREAM_1
1660 * @arg @ref LL_DMA_STREAM_2
1661 * @arg @ref LL_DMA_STREAM_3
1662 * @arg @ref LL_DMA_STREAM_4
1663 * @arg @ref LL_DMA_STREAM_5
1664 * @arg @ref LL_DMA_STREAM_6
1665 * @arg @ref LL_DMA_STREAM_7
1666 * @retval None
1667 */
1668__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream)
1669{
1670 uint32_t dma_base_addr = (uint32_t)DMAx;
1671
1672 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1673}
1674
1675/**
1676 * @brief Enable Fifo mode.
1677 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1678 * @param DMAx DMAx Instance
1679 * @param Stream This parameter can be one of the following values:
1680 * @arg @ref LL_DMA_STREAM_0
1681 * @arg @ref LL_DMA_STREAM_1
1682 * @arg @ref LL_DMA_STREAM_2
1683 * @arg @ref LL_DMA_STREAM_3
1684 * @arg @ref LL_DMA_STREAM_4
1685 * @arg @ref LL_DMA_STREAM_5
1686 * @arg @ref LL_DMA_STREAM_6
1687 * @arg @ref LL_DMA_STREAM_7
1688 * @retval None
1689 */
1690__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream)
1691{
1692 uint32_t dma_base_addr = (uint32_t)DMAx;
1693
1694 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1695}
1696
1697/**
1698 * @brief Select FIFO threshold.
1699 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1700 * @param DMAx DMAx Instance
1701 * @param Stream This parameter can be one of the following values:
1702 * @arg @ref LL_DMA_STREAM_0
1703 * @arg @ref LL_DMA_STREAM_1
1704 * @arg @ref LL_DMA_STREAM_2
1705 * @arg @ref LL_DMA_STREAM_3
1706 * @arg @ref LL_DMA_STREAM_4
1707 * @arg @ref LL_DMA_STREAM_5
1708 * @arg @ref LL_DMA_STREAM_6
1709 * @arg @ref LL_DMA_STREAM_7
1710 * @param Threshold This parameter can be one of the following values:
1711 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1712 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1713 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1714 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1715 * @retval None
1716 */
1717__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1718{
1719 uint32_t dma_base_addr = (uint32_t)DMAx;
1720
1721 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
1722}
1723
1724/**
1725 * @brief Get FIFO threshold.
1726 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1727 * @param DMAx DMAx Instance
1728 * @param Stream This parameter can be one of the following values:
1729 * @arg @ref LL_DMA_STREAM_0
1730 * @arg @ref LL_DMA_STREAM_1
1731 * @arg @ref LL_DMA_STREAM_2
1732 * @arg @ref LL_DMA_STREAM_3
1733 * @arg @ref LL_DMA_STREAM_4
1734 * @arg @ref LL_DMA_STREAM_5
1735 * @arg @ref LL_DMA_STREAM_6
1736 * @arg @ref LL_DMA_STREAM_7
1737 * @retval Returned value can be one of the following values:
1738 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1739 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1740 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1741 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1742 */
1743__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream)
1744{
1745 uint32_t dma_base_addr = (uint32_t)DMAx;
1746
1747 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
1748}
1749
1750/**
1751 * @brief Configure the FIFO .
1752 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1753 * FCR DMDIS LL_DMA_ConfigFifo
1754 * @param DMAx DMAx Instance
1755 * @param Stream This parameter can be one of the following values:
1756 * @arg @ref LL_DMA_STREAM_0
1757 * @arg @ref LL_DMA_STREAM_1
1758 * @arg @ref LL_DMA_STREAM_2
1759 * @arg @ref LL_DMA_STREAM_3
1760 * @arg @ref LL_DMA_STREAM_4
1761 * @arg @ref LL_DMA_STREAM_5
1762 * @arg @ref LL_DMA_STREAM_6
1763 * @arg @ref LL_DMA_STREAM_7
1764 * @param FifoMode This parameter can be one of the following values:
1765 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1766 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1767 * @param FifoThreshold This parameter can be one of the following values:
1768 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1769 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1770 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1771 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1772 * @retval None
1773 */
1774__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1775{
1776 uint32_t dma_base_addr = (uint32_t)DMAx;
1777
1778 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
1779}
1780
1781/**
1782 * @brief Configure the Source and Destination addresses.
1783 * @note This API must not be called when the DMA stream is enabled.
1784 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1785 * PAR PA LL_DMA_ConfigAddresses
1786 * @param DMAx DMAx Instance
1787 * @param Stream This parameter can be one of the following values:
1788 * @arg @ref LL_DMA_STREAM_0
1789 * @arg @ref LL_DMA_STREAM_1
1790 * @arg @ref LL_DMA_STREAM_2
1791 * @arg @ref LL_DMA_STREAM_3
1792 * @arg @ref LL_DMA_STREAM_4
1793 * @arg @ref LL_DMA_STREAM_5
1794 * @arg @ref LL_DMA_STREAM_6
1795 * @arg @ref LL_DMA_STREAM_7
1796 * @param SrcAddress Between 0 to 0xFFFFFFFF
1797 * @param DstAddress Between 0 to 0xFFFFFFFF
1798 * @param Direction This parameter can be one of the following values:
1799 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1800 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1801 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1802 * @retval None
1803 */
1804__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1805{
1806 uint32_t dma_base_addr = (uint32_t)DMAx;
1807
1808 /* Direction Memory to Periph */
1809 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1810 {
1811 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
1812 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
1813 }
1814 /* Direction Periph to Memory and Memory to Memory */
1815 else
1816 {
1817 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
1818 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
1819 }
1820}
1821
1822/**
1823 * @brief Set the Memory address.
1824 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1825 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1826 * @note This API must not be called when the DMA stream is enabled.
1827 * @param DMAx DMAx Instance
1828 * @param Stream This parameter can be one of the following values:
1829 * @arg @ref LL_DMA_STREAM_0
1830 * @arg @ref LL_DMA_STREAM_1
1831 * @arg @ref LL_DMA_STREAM_2
1832 * @arg @ref LL_DMA_STREAM_3
1833 * @arg @ref LL_DMA_STREAM_4
1834 * @arg @ref LL_DMA_STREAM_5
1835 * @arg @ref LL_DMA_STREAM_6
1836 * @arg @ref LL_DMA_STREAM_7
1837 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1838 * @retval None
1839 */
1840__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1841{
1842 uint32_t dma_base_addr = (uint32_t)DMAx;
1843
1844 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1845}
1846
1847/**
1848 * @brief Set the Peripheral address.
1849 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1850 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1851 * @note This API must not be called when the DMA stream is enabled.
1852 * @param DMAx DMAx Instance
1853 * @param Stream This parameter can be one of the following values:
1854 * @arg @ref LL_DMA_STREAM_0
1855 * @arg @ref LL_DMA_STREAM_1
1856 * @arg @ref LL_DMA_STREAM_2
1857 * @arg @ref LL_DMA_STREAM_3
1858 * @arg @ref LL_DMA_STREAM_4
1859 * @arg @ref LL_DMA_STREAM_5
1860 * @arg @ref LL_DMA_STREAM_6
1861 * @arg @ref LL_DMA_STREAM_7
1862 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1863 * @retval None
1864 */
1865__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
1866{
1867 uint32_t dma_base_addr = (uint32_t)DMAx;
1868
1869 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
1870}
1871
1872/**
1873 * @brief Get the Memory address.
1874 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1875 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1876 * @param DMAx DMAx Instance
1877 * @param Stream This parameter can be one of the following values:
1878 * @arg @ref LL_DMA_STREAM_0
1879 * @arg @ref LL_DMA_STREAM_1
1880 * @arg @ref LL_DMA_STREAM_2
1881 * @arg @ref LL_DMA_STREAM_3
1882 * @arg @ref LL_DMA_STREAM_4
1883 * @arg @ref LL_DMA_STREAM_5
1884 * @arg @ref LL_DMA_STREAM_6
1885 * @arg @ref LL_DMA_STREAM_7
1886 * @retval Between 0 to 0xFFFFFFFF
1887 */
1888__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream)
1889{
1890 uint32_t dma_base_addr = (uint32_t)DMAx;
1891
1892 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1893}
1894
1895/**
1896 * @brief Get the Peripheral address.
1897 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1898 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1899 * @param DMAx DMAx Instance
1900 * @param Stream This parameter can be one of the following values:
1901 * @arg @ref LL_DMA_STREAM_0
1902 * @arg @ref LL_DMA_STREAM_1
1903 * @arg @ref LL_DMA_STREAM_2
1904 * @arg @ref LL_DMA_STREAM_3
1905 * @arg @ref LL_DMA_STREAM_4
1906 * @arg @ref LL_DMA_STREAM_5
1907 * @arg @ref LL_DMA_STREAM_6
1908 * @arg @ref LL_DMA_STREAM_7
1909 * @retval Between 0 to 0xFFFFFFFF
1910 */
1911__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream)
1912{
1913 uint32_t dma_base_addr = (uint32_t)DMAx;
1914
1915 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1916}
1917
1918/**
1919 * @brief Set the Memory to Memory Source address.
1920 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1921 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1922 * @note This API must not be called when the DMA stream is enabled.
1923 * @param DMAx DMAx Instance
1924 * @param Stream This parameter can be one of the following values:
1925 * @arg @ref LL_DMA_STREAM_0
1926 * @arg @ref LL_DMA_STREAM_1
1927 * @arg @ref LL_DMA_STREAM_2
1928 * @arg @ref LL_DMA_STREAM_3
1929 * @arg @ref LL_DMA_STREAM_4
1930 * @arg @ref LL_DMA_STREAM_5
1931 * @arg @ref LL_DMA_STREAM_6
1932 * @arg @ref LL_DMA_STREAM_7
1933 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1934 * @retval None
1935 */
1936__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1937{
1938 uint32_t dma_base_addr = (uint32_t)DMAx;
1939
1940 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
1941}
1942
1943/**
1944 * @brief Set the Memory to Memory Destination address.
1945 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1946 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1947 * @note This API must not be called when the DMA stream is enabled.
1948 * @param DMAx DMAx Instance
1949 * @param Stream This parameter can be one of the following values:
1950 * @arg @ref LL_DMA_STREAM_0
1951 * @arg @ref LL_DMA_STREAM_1
1952 * @arg @ref LL_DMA_STREAM_2
1953 * @arg @ref LL_DMA_STREAM_3
1954 * @arg @ref LL_DMA_STREAM_4
1955 * @arg @ref LL_DMA_STREAM_5
1956 * @arg @ref LL_DMA_STREAM_6
1957 * @arg @ref LL_DMA_STREAM_7
1958 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1959 * @retval None
1960 */
1961__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1962{
1963 uint32_t dma_base_addr = (uint32_t)DMAx;
1964
1965 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1966}
1967
1968/**
1969 * @brief Get the Memory to Memory Source address.
1970 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1971 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1972 * @param DMAx DMAx Instance
1973 * @param Stream This parameter can be one of the following values:
1974 * @arg @ref LL_DMA_STREAM_0
1975 * @arg @ref LL_DMA_STREAM_1
1976 * @arg @ref LL_DMA_STREAM_2
1977 * @arg @ref LL_DMA_STREAM_3
1978 * @arg @ref LL_DMA_STREAM_4
1979 * @arg @ref LL_DMA_STREAM_5
1980 * @arg @ref LL_DMA_STREAM_6
1981 * @arg @ref LL_DMA_STREAM_7
1982 * @retval Between 0 to 0xFFFFFFFF
1983 */
1984__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream)
1985{
1986 uint32_t dma_base_addr = (uint32_t)DMAx;
1987
1988 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1989}
1990
1991/**
1992 * @brief Get the Memory to Memory Destination address.
1993 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1994 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1995 * @param DMAx DMAx Instance
1996 * @param Stream This parameter can be one of the following values:
1997 * @arg @ref LL_DMA_STREAM_0
1998 * @arg @ref LL_DMA_STREAM_1
1999 * @arg @ref LL_DMA_STREAM_2
2000 * @arg @ref LL_DMA_STREAM_3
2001 * @arg @ref LL_DMA_STREAM_4
2002 * @arg @ref LL_DMA_STREAM_5
2003 * @arg @ref LL_DMA_STREAM_6
2004 * @arg @ref LL_DMA_STREAM_7
2005 * @retval Between 0 to 0xFFFFFFFF
2006 */
2007__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream)
2008{
2009 uint32_t dma_base_addr = (uint32_t)DMAx;
2010
2011 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
2012}
2013
2014/**
2015 * @brief Set Memory 1 address (used in case of Double buffer mode).
2016 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
2017 * @param DMAx DMAx Instance
2018 * @param Stream This parameter can be one of the following values:
2019 * @arg @ref LL_DMA_STREAM_0
2020 * @arg @ref LL_DMA_STREAM_1
2021 * @arg @ref LL_DMA_STREAM_2
2022 * @arg @ref LL_DMA_STREAM_3
2023 * @arg @ref LL_DMA_STREAM_4
2024 * @arg @ref LL_DMA_STREAM_5
2025 * @arg @ref LL_DMA_STREAM_6
2026 * @arg @ref LL_DMA_STREAM_7
2027 * @param Address Between 0 to 0xFFFFFFFF
2028 * @retval None
2029 */
2030__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
2031{
2032 uint32_t dma_base_addr = (uint32_t)DMAx;
2033
2034 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
2035}
2036
2037/**
2038 * @brief Get Memory 1 address (used in case of Double buffer mode).
2039 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
2040 * @param DMAx DMAx Instance
2041 * @param Stream This parameter can be one of the following values:
2042 * @arg @ref LL_DMA_STREAM_0
2043 * @arg @ref LL_DMA_STREAM_1
2044 * @arg @ref LL_DMA_STREAM_2
2045 * @arg @ref LL_DMA_STREAM_3
2046 * @arg @ref LL_DMA_STREAM_4
2047 * @arg @ref LL_DMA_STREAM_5
2048 * @arg @ref LL_DMA_STREAM_6
2049 * @arg @ref LL_DMA_STREAM_7
2050 * @retval Between 0 to 0xFFFFFFFF
2051 */
2052__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream)
2053{
2054 uint32_t dma_base_addr = (uint32_t)DMAx;
2055
2056 return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
2057}
2058
2059/**
2060 * @}
2061 */
2062
2063/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
2064 * @{
2065 */
2066
2067/**
2068 * @brief Get Stream 0 half transfer flag.
2069 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
2070 * @param DMAx DMAx Instance
2071 * @retval State of bit (1 or 0).
2072 */
2073__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx)
2074{
2075 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
2076}
2077
2078/**
2079 * @brief Get Stream 1 half transfer flag.
2080 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
2081 * @param DMAx DMAx Instance
2082 * @retval State of bit (1 or 0).
2083 */
2084__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx)
2085{
2086 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
2087}
2088
2089/**
2090 * @brief Get Stream 2 half transfer flag.
2091 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
2092 * @param DMAx DMAx Instance
2093 * @retval State of bit (1 or 0).
2094 */
2095__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx)
2096{
2097 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
2098}
2099
2100/**
2101 * @brief Get Stream 3 half transfer flag.
2102 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
2103 * @param DMAx DMAx Instance
2104 * @retval State of bit (1 or 0).
2105 */
2106__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx)
2107{
2108 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
2109}
2110
2111/**
2112 * @brief Get Stream 4 half transfer flag.
2113 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
2114 * @param DMAx DMAx Instance
2115 * @retval State of bit (1 or 0).
2116 */
2117__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx)
2118{
2119 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
2120}
2121
2122/**
2123 * @brief Get Stream 5 half transfer flag.
2124 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
2125 * @param DMAx DMAx Instance
2126 * @retval State of bit (1 or 0).
2127 */
2128__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx)
2129{
2130 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
2131}
2132
2133/**
2134 * @brief Get Stream 6 half transfer flag.
2135 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
2136 * @param DMAx DMAx Instance
2137 * @retval State of bit (1 or 0).
2138 */
2139__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx)
2140{
2141 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
2142}
2143
2144/**
2145 * @brief Get Stream 7 half transfer flag.
2146 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
2147 * @param DMAx DMAx Instance
2148 * @retval State of bit (1 or 0).
2149 */
2150__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx)
2151{
2152 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
2153}
2154
2155/**
2156 * @brief Get Stream 0 transfer complete flag.
2157 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
2158 * @param DMAx DMAx Instance
2159 * @retval State of bit (1 or 0).
2160 */
2161__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx)
2162{
2163 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
2164}
2165
2166/**
2167 * @brief Get Stream 1 transfer complete flag.
2168 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
2169 * @param DMAx DMAx Instance
2170 * @retval State of bit (1 or 0).
2171 */
2172__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx)
2173{
2174 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
2175}
2176
2177/**
2178 * @brief Get Stream 2 transfer complete flag.
2179 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
2180 * @param DMAx DMAx Instance
2181 * @retval State of bit (1 or 0).
2182 */
2183__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx)
2184{
2185 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
2186}
2187
2188/**
2189 * @brief Get Stream 3 transfer complete flag.
2190 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
2191 * @param DMAx DMAx Instance
2192 * @retval State of bit (1 or 0).
2193 */
2194__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx)
2195{
2196 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
2197}
2198
2199/**
2200 * @brief Get Stream 4 transfer complete flag.
2201 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
2202 * @param DMAx DMAx Instance
2203 * @retval State of bit (1 or 0).
2204 */
2205__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx)
2206{
2207 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
2208}
2209
2210/**
2211 * @brief Get Stream 5 transfer complete flag.
2212 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
2213 * @param DMAx DMAx Instance
2214 * @retval State of bit (1 or 0).
2215 */
2216__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx)
2217{
2218 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
2219}
2220
2221/**
2222 * @brief Get Stream 6 transfer complete flag.
2223 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
2224 * @param DMAx DMAx Instance
2225 * @retval State of bit (1 or 0).
2226 */
2227__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx)
2228{
2229 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
2230}
2231
2232/**
2233 * @brief Get Stream 7 transfer complete flag.
2234 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
2235 * @param DMAx DMAx Instance
2236 * @retval State of bit (1 or 0).
2237 */
2238__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx)
2239{
2240 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
2241}
2242
2243/**
2244 * @brief Get Stream 0 transfer error flag.
2245 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
2246 * @param DMAx DMAx Instance
2247 * @retval State of bit (1 or 0).
2248 */
2249__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx)
2250{
2251 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
2252}
2253
2254/**
2255 * @brief Get Stream 1 transfer error flag.
2256 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
2257 * @param DMAx DMAx Instance
2258 * @retval State of bit (1 or 0).
2259 */
2260__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx)
2261{
2262 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
2263}
2264
2265/**
2266 * @brief Get Stream 2 transfer error flag.
2267 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
2268 * @param DMAx DMAx Instance
2269 * @retval State of bit (1 or 0).
2270 */
2271__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx)
2272{
2273 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
2274}
2275
2276/**
2277 * @brief Get Stream 3 transfer error flag.
2278 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
2279 * @param DMAx DMAx Instance
2280 * @retval State of bit (1 or 0).
2281 */
2282__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx)
2283{
2284 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
2285}
2286
2287/**
2288 * @brief Get Stream 4 transfer error flag.
2289 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
2290 * @param DMAx DMAx Instance
2291 * @retval State of bit (1 or 0).
2292 */
2293__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx)
2294{
2295 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
2296}
2297
2298/**
2299 * @brief Get Stream 5 transfer error flag.
2300 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
2301 * @param DMAx DMAx Instance
2302 * @retval State of bit (1 or 0).
2303 */
2304__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx)
2305{
2306 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
2307}
2308
2309/**
2310 * @brief Get Stream 6 transfer error flag.
2311 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
2312 * @param DMAx DMAx Instance
2313 * @retval State of bit (1 or 0).
2314 */
2315__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx)
2316{
2317 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
2318}
2319
2320/**
2321 * @brief Get Stream 7 transfer error flag.
2322 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
2323 * @param DMAx DMAx Instance
2324 * @retval State of bit (1 or 0).
2325 */
2326__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx)
2327{
2328 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
2329}
2330
2331/**
2332 * @brief Get Stream 0 direct mode error flag.
2333 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
2334 * @param DMAx DMAx Instance
2335 * @retval State of bit (1 or 0).
2336 */
2337__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx)
2338{
2339 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
2340}
2341
2342/**
2343 * @brief Get Stream 1 direct mode error flag.
2344 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
2345 * @param DMAx DMAx Instance
2346 * @retval State of bit (1 or 0).
2347 */
2348__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx)
2349{
2350 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
2351}
2352
2353/**
2354 * @brief Get Stream 2 direct mode error flag.
2355 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
2356 * @param DMAx DMAx Instance
2357 * @retval State of bit (1 or 0).
2358 */
2359__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx)
2360{
2361 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
2362}
2363
2364/**
2365 * @brief Get Stream 3 direct mode error flag.
2366 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
2367 * @param DMAx DMAx Instance
2368 * @retval State of bit (1 or 0).
2369 */
2370__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx)
2371{
2372 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
2373}
2374
2375/**
2376 * @brief Get Stream 4 direct mode error flag.
2377 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
2378 * @param DMAx DMAx Instance
2379 * @retval State of bit (1 or 0).
2380 */
2381__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx)
2382{
2383 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
2384}
2385
2386/**
2387 * @brief Get Stream 5 direct mode error flag.
2388 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
2389 * @param DMAx DMAx Instance
2390 * @retval State of bit (1 or 0).
2391 */
2392__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx)
2393{
2394 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
2395}
2396
2397/**
2398 * @brief Get Stream 6 direct mode error flag.
2399 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2400 * @param DMAx DMAx Instance
2401 * @retval State of bit (1 or 0).
2402 */
2403__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx)
2404{
2405 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
2406}
2407
2408/**
2409 * @brief Get Stream 7 direct mode error flag.
2410 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2411 * @param DMAx DMAx Instance
2412 * @retval State of bit (1 or 0).
2413 */
2414__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx)
2415{
2416 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
2417}
2418
2419/**
2420 * @brief Get Stream 0 FIFO error flag.
2421 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2422 * @param DMAx DMAx Instance
2423 * @retval State of bit (1 or 0).
2424 */
2425__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx)
2426{
2427 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
2428}
2429
2430/**
2431 * @brief Get Stream 1 FIFO error flag.
2432 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2433 * @param DMAx DMAx Instance
2434 * @retval State of bit (1 or 0).
2435 */
2436__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx)
2437{
2438 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
2439}
2440
2441/**
2442 * @brief Get Stream 2 FIFO error flag.
2443 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2444 * @param DMAx DMAx Instance
2445 * @retval State of bit (1 or 0).
2446 */
2447__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx)
2448{
2449 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
2450}
2451
2452/**
2453 * @brief Get Stream 3 FIFO error flag.
2454 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2455 * @param DMAx DMAx Instance
2456 * @retval State of bit (1 or 0).
2457 */
2458__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx)
2459{
2460 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
2461}
2462
2463/**
2464 * @brief Get Stream 4 FIFO error flag.
2465 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2466 * @param DMAx DMAx Instance
2467 * @retval State of bit (1 or 0).
2468 */
2469__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx)
2470{
2471 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
2472}
2473
2474/**
2475 * @brief Get Stream 5 FIFO error flag.
2476 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2477 * @param DMAx DMAx Instance
2478 * @retval State of bit (1 or 0).
2479 */
2480__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx)
2481{
2482 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
2483}
2484
2485/**
2486 * @brief Get Stream 6 FIFO error flag.
2487 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2488 * @param DMAx DMAx Instance
2489 * @retval State of bit (1 or 0).
2490 */
2491__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx)
2492{
2493 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
2494}
2495
2496/**
2497 * @brief Get Stream 7 FIFO error flag.
2498 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2499 * @param DMAx DMAx Instance
2500 * @retval State of bit (1 or 0).
2501 */
2502__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx)
2503{
2504 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
2505}
2506
2507/**
2508 * @brief Clear Stream 0 half transfer flag.
2509 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2510 * @param DMAx DMAx Instance
2511 * @retval None
2512 */
2513__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2514{
2515 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
2516}
2517
2518/**
2519 * @brief Clear Stream 1 half transfer flag.
2520 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2521 * @param DMAx DMAx Instance
2522 * @retval None
2523 */
2524__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2525{
2526 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
2527}
2528
2529/**
2530 * @brief Clear Stream 2 half transfer flag.
2531 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2532 * @param DMAx DMAx Instance
2533 * @retval None
2534 */
2535__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2536{
2537 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
2538}
2539
2540/**
2541 * @brief Clear Stream 3 half transfer flag.
2542 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2543 * @param DMAx DMAx Instance
2544 * @retval None
2545 */
2546__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2547{
2548 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
2549}
2550
2551/**
2552 * @brief Clear Stream 4 half transfer flag.
2553 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2554 * @param DMAx DMAx Instance
2555 * @retval None
2556 */
2557__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2558{
2559 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
2560}
2561
2562/**
2563 * @brief Clear Stream 5 half transfer flag.
2564 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2565 * @param DMAx DMAx Instance
2566 * @retval None
2567 */
2568__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2569{
2570 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
2571}
2572
2573/**
2574 * @brief Clear Stream 6 half transfer flag.
2575 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2576 * @param DMAx DMAx Instance
2577 * @retval None
2578 */
2579__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2580{
2581 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
2582}
2583
2584/**
2585 * @brief Clear Stream 7 half transfer flag.
2586 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2587 * @param DMAx DMAx Instance
2588 * @retval None
2589 */
2590__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2591{
2592 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
2593}
2594
2595/**
2596 * @brief Clear Stream 0 transfer complete flag.
2597 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2598 * @param DMAx DMAx Instance
2599 * @retval None
2600 */
2601__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2602{
2603 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
2604}
2605
2606/**
2607 * @brief Clear Stream 1 transfer complete flag.
2608 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2609 * @param DMAx DMAx Instance
2610 * @retval None
2611 */
2612__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2613{
2614 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
2615}
2616
2617/**
2618 * @brief Clear Stream 2 transfer complete flag.
2619 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2620 * @param DMAx DMAx Instance
2621 * @retval None
2622 */
2623__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2624{
2625 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
2626}
2627
2628/**
2629 * @brief Clear Stream 3 transfer complete flag.
2630 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2631 * @param DMAx DMAx Instance
2632 * @retval None
2633 */
2634__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2635{
2636 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
2637}
2638
2639/**
2640 * @brief Clear Stream 4 transfer complete flag.
2641 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2642 * @param DMAx DMAx Instance
2643 * @retval None
2644 */
2645__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2646{
2647 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
2648}
2649
2650/**
2651 * @brief Clear Stream 5 transfer complete flag.
2652 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2653 * @param DMAx DMAx Instance
2654 * @retval None
2655 */
2656__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2657{
2658 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
2659}
2660
2661/**
2662 * @brief Clear Stream 6 transfer complete flag.
2663 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2664 * @param DMAx DMAx Instance
2665 * @retval None
2666 */
2667__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2668{
2669 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
2670}
2671
2672/**
2673 * @brief Clear Stream 7 transfer complete flag.
2674 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2675 * @param DMAx DMAx Instance
2676 * @retval None
2677 */
2678__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2679{
2680 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
2681}
2682
2683/**
2684 * @brief Clear Stream 0 transfer error flag.
2685 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2686 * @param DMAx DMAx Instance
2687 * @retval None
2688 */
2689__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2690{
2691 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
2692}
2693
2694/**
2695 * @brief Clear Stream 1 transfer error flag.
2696 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2697 * @param DMAx DMAx Instance
2698 * @retval None
2699 */
2700__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2701{
2702 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
2703}
2704
2705/**
2706 * @brief Clear Stream 2 transfer error flag.
2707 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2708 * @param DMAx DMAx Instance
2709 * @retval None
2710 */
2711__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2712{
2713 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
2714}
2715
2716/**
2717 * @brief Clear Stream 3 transfer error flag.
2718 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2719 * @param DMAx DMAx Instance
2720 * @retval None
2721 */
2722__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2723{
2724 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
2725}
2726
2727/**
2728 * @brief Clear Stream 4 transfer error flag.
2729 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2730 * @param DMAx DMAx Instance
2731 * @retval None
2732 */
2733__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2734{
2735 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
2736}
2737
2738/**
2739 * @brief Clear Stream 5 transfer error flag.
2740 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2741 * @param DMAx DMAx Instance
2742 * @retval None
2743 */
2744__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2745{
2746 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
2747}
2748
2749/**
2750 * @brief Clear Stream 6 transfer error flag.
2751 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2752 * @param DMAx DMAx Instance
2753 * @retval None
2754 */
2755__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2756{
2757 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
2758}
2759
2760/**
2761 * @brief Clear Stream 7 transfer error flag.
2762 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2763 * @param DMAx DMAx Instance
2764 * @retval None
2765 */
2766__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2767{
2768 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
2769}
2770
2771/**
2772 * @brief Clear Stream 0 direct mode error flag.
2773 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2774 * @param DMAx DMAx Instance
2775 * @retval None
2776 */
2777__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2778{
2779 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
2780}
2781
2782/**
2783 * @brief Clear Stream 1 direct mode error flag.
2784 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2785 * @param DMAx DMAx Instance
2786 * @retval None
2787 */
2788__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2789{
2790 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
2791}
2792
2793/**
2794 * @brief Clear Stream 2 direct mode error flag.
2795 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2796 * @param DMAx DMAx Instance
2797 * @retval None
2798 */
2799__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2800{
2801 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
2802}
2803
2804/**
2805 * @brief Clear Stream 3 direct mode error flag.
2806 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2807 * @param DMAx DMAx Instance
2808 * @retval None
2809 */
2810__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2811{
2812 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
2813}
2814
2815/**
2816 * @brief Clear Stream 4 direct mode error flag.
2817 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2818 * @param DMAx DMAx Instance
2819 * @retval None
2820 */
2821__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2822{
2823 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
2824}
2825
2826/**
2827 * @brief Clear Stream 5 direct mode error flag.
2828 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2829 * @param DMAx DMAx Instance
2830 * @retval None
2831 */
2832__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2833{
2834 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
2835}
2836
2837/**
2838 * @brief Clear Stream 6 direct mode error flag.
2839 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2840 * @param DMAx DMAx Instance
2841 * @retval None
2842 */
2843__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2844{
2845 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
2846}
2847
2848/**
2849 * @brief Clear Stream 7 direct mode error flag.
2850 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2851 * @param DMAx DMAx Instance
2852 * @retval None
2853 */
2854__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2855{
2856 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
2857}
2858
2859/**
2860 * @brief Clear Stream 0 FIFO error flag.
2861 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2862 * @param DMAx DMAx Instance
2863 * @retval None
2864 */
2865__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2866{
2867 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
2868}
2869
2870/**
2871 * @brief Clear Stream 1 FIFO error flag.
2872 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2873 * @param DMAx DMAx Instance
2874 * @retval None
2875 */
2876__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2877{
2878 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
2879}
2880
2881/**
2882 * @brief Clear Stream 2 FIFO error flag.
2883 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2884 * @param DMAx DMAx Instance
2885 * @retval None
2886 */
2887__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2888{
2889 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
2890}
2891
2892/**
2893 * @brief Clear Stream 3 FIFO error flag.
2894 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2895 * @param DMAx DMAx Instance
2896 * @retval None
2897 */
2898__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2899{
2900 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
2901}
2902
2903/**
2904 * @brief Clear Stream 4 FIFO error flag.
2905 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2906 * @param DMAx DMAx Instance
2907 * @retval None
2908 */
2909__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2910{
2911 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
2912}
2913
2914/**
2915 * @brief Clear Stream 5 FIFO error flag.
2916 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2917 * @param DMAx DMAx Instance
2918 * @retval None
2919 */
2920__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2921{
2922 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
2923}
2924
2925/**
2926 * @brief Clear Stream 6 FIFO error flag.
2927 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2928 * @param DMAx DMAx Instance
2929 * @retval None
2930 */
2931__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2932{
2933 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
2934}
2935
2936/**
2937 * @brief Clear Stream 7 FIFO error flag.
2938 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2939 * @param DMAx DMAx Instance
2940 * @retval None
2941 */
2942__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2943{
2944 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
2945}
2946
2947/**
2948 * @}
2949 */
2950
2951/** @defgroup DMA_LL_EF_IT_Management IT_Management
2952 * @{
2953 */
2954
2955/**
2956 * @brief Enable Half transfer interrupt.
2957 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2958 * @param DMAx DMAx Instance
2959 * @param Stream This parameter can be one of the following values:
2960 * @arg @ref LL_DMA_STREAM_0
2961 * @arg @ref LL_DMA_STREAM_1
2962 * @arg @ref LL_DMA_STREAM_2
2963 * @arg @ref LL_DMA_STREAM_3
2964 * @arg @ref LL_DMA_STREAM_4
2965 * @arg @ref LL_DMA_STREAM_5
2966 * @arg @ref LL_DMA_STREAM_6
2967 * @arg @ref LL_DMA_STREAM_7
2968 * @retval None
2969 */
2970__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream)
2971{
2972 uint32_t dma_base_addr = (uint32_t)DMAx;
2973
2974 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2975}
2976
2977/**
2978 * @brief Enable Transfer error interrupt.
2979 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2980 * @param DMAx DMAx Instance
2981 * @param Stream This parameter can be one of the following values:
2982 * @arg @ref LL_DMA_STREAM_0
2983 * @arg @ref LL_DMA_STREAM_1
2984 * @arg @ref LL_DMA_STREAM_2
2985 * @arg @ref LL_DMA_STREAM_3
2986 * @arg @ref LL_DMA_STREAM_4
2987 * @arg @ref LL_DMA_STREAM_5
2988 * @arg @ref LL_DMA_STREAM_6
2989 * @arg @ref LL_DMA_STREAM_7
2990 * @retval None
2991 */
2992__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream)
2993{
2994 uint32_t dma_base_addr = (uint32_t)DMAx;
2995
2996 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2997}
2998
2999/**
3000 * @brief Enable Transfer complete interrupt.
3001 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
3002 * @param DMAx DMAx Instance
3003 * @param Stream This parameter can be one of the following values:
3004 * @arg @ref LL_DMA_STREAM_0
3005 * @arg @ref LL_DMA_STREAM_1
3006 * @arg @ref LL_DMA_STREAM_2
3007 * @arg @ref LL_DMA_STREAM_3
3008 * @arg @ref LL_DMA_STREAM_4
3009 * @arg @ref LL_DMA_STREAM_5
3010 * @arg @ref LL_DMA_STREAM_6
3011 * @arg @ref LL_DMA_STREAM_7
3012 * @retval None
3013 */
3014__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream)
3015{
3016 uint32_t dma_base_addr = (uint32_t)DMAx;
3017
3018 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
3019}
3020
3021/**
3022 * @brief Enable Direct mode error interrupt.
3023 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
3024 * @param DMAx DMAx Instance
3025 * @param Stream This parameter can be one of the following values:
3026 * @arg @ref LL_DMA_STREAM_0
3027 * @arg @ref LL_DMA_STREAM_1
3028 * @arg @ref LL_DMA_STREAM_2
3029 * @arg @ref LL_DMA_STREAM_3
3030 * @arg @ref LL_DMA_STREAM_4
3031 * @arg @ref LL_DMA_STREAM_5
3032 * @arg @ref LL_DMA_STREAM_6
3033 * @arg @ref LL_DMA_STREAM_7
3034 * @retval None
3035 */
3036__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream)
3037{
3038 uint32_t dma_base_addr = (uint32_t)DMAx;
3039
3040 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3041}
3042
3043/**
3044 * @brief Enable FIFO error interrupt.
3045 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
3046 * @param DMAx DMAx Instance
3047 * @param Stream This parameter can be one of the following values:
3048 * @arg @ref LL_DMA_STREAM_0
3049 * @arg @ref LL_DMA_STREAM_1
3050 * @arg @ref LL_DMA_STREAM_2
3051 * @arg @ref LL_DMA_STREAM_3
3052 * @arg @ref LL_DMA_STREAM_4
3053 * @arg @ref LL_DMA_STREAM_5
3054 * @arg @ref LL_DMA_STREAM_6
3055 * @arg @ref LL_DMA_STREAM_7
3056 * @retval None
3057 */
3058__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream)
3059{
3060 uint32_t dma_base_addr = (uint32_t)DMAx;
3061
3062 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3063}
3064
3065/**
3066 * @brief Disable Half transfer interrupt.
3067 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
3068 * @param DMAx DMAx Instance
3069 * @param Stream This parameter can be one of the following values:
3070 * @arg @ref LL_DMA_STREAM_0
3071 * @arg @ref LL_DMA_STREAM_1
3072 * @arg @ref LL_DMA_STREAM_2
3073 * @arg @ref LL_DMA_STREAM_3
3074 * @arg @ref LL_DMA_STREAM_4
3075 * @arg @ref LL_DMA_STREAM_5
3076 * @arg @ref LL_DMA_STREAM_6
3077 * @arg @ref LL_DMA_STREAM_7
3078 * @retval None
3079 */
3080__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream)
3081{
3082 uint32_t dma_base_addr = (uint32_t)DMAx;
3083
3084 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
3085}
3086
3087/**
3088 * @brief Disable Transfer error interrupt.
3089 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
3090 * @param DMAx DMAx Instance
3091 * @param Stream This parameter can be one of the following values:
3092 * @arg @ref LL_DMA_STREAM_0
3093 * @arg @ref LL_DMA_STREAM_1
3094 * @arg @ref LL_DMA_STREAM_2
3095 * @arg @ref LL_DMA_STREAM_3
3096 * @arg @ref LL_DMA_STREAM_4
3097 * @arg @ref LL_DMA_STREAM_5
3098 * @arg @ref LL_DMA_STREAM_6
3099 * @arg @ref LL_DMA_STREAM_7
3100 * @retval None
3101 */
3102__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream)
3103{
3104 uint32_t dma_base_addr = (uint32_t)DMAx;
3105
3106 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
3107}
3108
3109/**
3110 * @brief Disable Transfer complete interrupt.
3111 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
3112 * @param DMAx DMAx Instance
3113 * @param Stream This parameter can be one of the following values:
3114 * @arg @ref LL_DMA_STREAM_0
3115 * @arg @ref LL_DMA_STREAM_1
3116 * @arg @ref LL_DMA_STREAM_2
3117 * @arg @ref LL_DMA_STREAM_3
3118 * @arg @ref LL_DMA_STREAM_4
3119 * @arg @ref LL_DMA_STREAM_5
3120 * @arg @ref LL_DMA_STREAM_6
3121 * @arg @ref LL_DMA_STREAM_7
3122 * @retval None
3123 */
3124__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream)
3125{
3126 uint32_t dma_base_addr = (uint32_t)DMAx;
3127
3128 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
3129}
3130
3131/**
3132 * @brief Disable Direct mode error interrupt.
3133 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
3134 * @param DMAx DMAx Instance
3135 * @param Stream This parameter can be one of the following values:
3136 * @arg @ref LL_DMA_STREAM_0
3137 * @arg @ref LL_DMA_STREAM_1
3138 * @arg @ref LL_DMA_STREAM_2
3139 * @arg @ref LL_DMA_STREAM_3
3140 * @arg @ref LL_DMA_STREAM_4
3141 * @arg @ref LL_DMA_STREAM_5
3142 * @arg @ref LL_DMA_STREAM_6
3143 * @arg @ref LL_DMA_STREAM_7
3144 * @retval None
3145 */
3146__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream)
3147{
3148 uint32_t dma_base_addr = (uint32_t)DMAx;
3149
3150 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3151}
3152
3153/**
3154 * @brief Disable FIFO error interrupt.
3155 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
3156 * @param DMAx DMAx Instance
3157 * @param Stream This parameter can be one of the following values:
3158 * @arg @ref LL_DMA_STREAM_0
3159 * @arg @ref LL_DMA_STREAM_1
3160 * @arg @ref LL_DMA_STREAM_2
3161 * @arg @ref LL_DMA_STREAM_3
3162 * @arg @ref LL_DMA_STREAM_4
3163 * @arg @ref LL_DMA_STREAM_5
3164 * @arg @ref LL_DMA_STREAM_6
3165 * @arg @ref LL_DMA_STREAM_7
3166 * @retval None
3167 */
3168__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream)
3169{
3170 uint32_t dma_base_addr = (uint32_t)DMAx;
3171
3172 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3173}
3174
3175/**
3176 * @brief Check if Half transfer interrupt is enabled.
3177 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
3178 * @param DMAx DMAx Instance
3179 * @param Stream This parameter can be one of the following values:
3180 * @arg @ref LL_DMA_STREAM_0
3181 * @arg @ref LL_DMA_STREAM_1
3182 * @arg @ref LL_DMA_STREAM_2
3183 * @arg @ref LL_DMA_STREAM_3
3184 * @arg @ref LL_DMA_STREAM_4
3185 * @arg @ref LL_DMA_STREAM_5
3186 * @arg @ref LL_DMA_STREAM_6
3187 * @arg @ref LL_DMA_STREAM_7
3188 * @retval State of bit (1 or 0).
3189 */
3190__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream)
3191{
3192 uint32_t dma_base_addr = (uint32_t)DMAx;
3193
3194 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
3195}
3196
3197/**
3198 * @brief Check if Transfer error nterrup is enabled.
3199 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
3200 * @param DMAx DMAx Instance
3201 * @param Stream This parameter can be one of the following values:
3202 * @arg @ref LL_DMA_STREAM_0
3203 * @arg @ref LL_DMA_STREAM_1
3204 * @arg @ref LL_DMA_STREAM_2
3205 * @arg @ref LL_DMA_STREAM_3
3206 * @arg @ref LL_DMA_STREAM_4
3207 * @arg @ref LL_DMA_STREAM_5
3208 * @arg @ref LL_DMA_STREAM_6
3209 * @arg @ref LL_DMA_STREAM_7
3210 * @retval State of bit (1 or 0).
3211 */
3212__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream)
3213{
3214 uint32_t dma_base_addr = (uint32_t)DMAx;
3215
3216 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
3217}
3218
3219/**
3220 * @brief Check if Transfer complete interrupt is enabled.
3221 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
3222 * @param DMAx DMAx Instance
3223 * @param Stream This parameter can be one of the following values:
3224 * @arg @ref LL_DMA_STREAM_0
3225 * @arg @ref LL_DMA_STREAM_1
3226 * @arg @ref LL_DMA_STREAM_2
3227 * @arg @ref LL_DMA_STREAM_3
3228 * @arg @ref LL_DMA_STREAM_4
3229 * @arg @ref LL_DMA_STREAM_5
3230 * @arg @ref LL_DMA_STREAM_6
3231 * @arg @ref LL_DMA_STREAM_7
3232 * @retval State of bit (1 or 0).
3233 */
3234__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream)
3235{
3236 uint32_t dma_base_addr = (uint32_t)DMAx;
3237
3238 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
3239}
3240
3241/**
3242 * @brief Check if Direct mode error interrupt is enabled.
3243 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
3244 * @param DMAx DMAx Instance
3245 * @param Stream This parameter can be one of the following values:
3246 * @arg @ref LL_DMA_STREAM_0
3247 * @arg @ref LL_DMA_STREAM_1
3248 * @arg @ref LL_DMA_STREAM_2
3249 * @arg @ref LL_DMA_STREAM_3
3250 * @arg @ref LL_DMA_STREAM_4
3251 * @arg @ref LL_DMA_STREAM_5
3252 * @arg @ref LL_DMA_STREAM_6
3253 * @arg @ref LL_DMA_STREAM_7
3254 * @retval State of bit (1 or 0).
3255 */
3256__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream)
3257{
3258 uint32_t dma_base_addr = (uint32_t)DMAx;
3259
3260 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
3261}
3262
3263/**
3264 * @brief Check if FIFO error interrupt is enabled.
3265 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
3266 * @param DMAx DMAx Instance
3267 * @param Stream This parameter can be one of the following values:
3268 * @arg @ref LL_DMA_STREAM_0
3269 * @arg @ref LL_DMA_STREAM_1
3270 * @arg @ref LL_DMA_STREAM_2
3271 * @arg @ref LL_DMA_STREAM_3
3272 * @arg @ref LL_DMA_STREAM_4
3273 * @arg @ref LL_DMA_STREAM_5
3274 * @arg @ref LL_DMA_STREAM_6
3275 * @arg @ref LL_DMA_STREAM_7
3276 * @retval State of bit (1 or 0).
3277 */
3278__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream)
3279{
3280 uint32_t dma_base_addr = (uint32_t)DMAx;
3281
3282 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
3283}
3284
3285/**
3286 * @}
3287 */
3288
3289#if defined(USE_FULL_LL_DRIVER)
3290/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3291 * @{
3292 */
3293
3294uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
3295uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
3296void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
3297
3298/**
3299 * @}
3300 */
3301#endif /* USE_FULL_LL_DRIVER */
3302
3303/**
3304 * @}
3305 */
3306
3307/**
3308 * @}
3309 */
3310
3311#endif /* DMA1 || DMA2 */
3312
3313/**
3314 * @}
3315 */
3316
3317#ifdef __cplusplus
3318}
3319#endif
3320
3321#endif /* __STM32H7xx_LL_DMA_H */
3322
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
READ_REG
#define READ_REG(REG)
Definition stm32h7xx.h:217
DMA_LISR_DMEIF3
#define DMA_LISR_DMEIF3
Stream 3 direct mode error interrupt flag.
Definition stm32h723xx.h:8899
DMA_LISR_HTIF1
#define DMA_LISR_HTIF1
Stream 1 half transfer interrupt flag.
Definition stm32h723xx.h:8923
DMA_LIFCR_CTEIF3
#define DMA_LIFCR_CTEIF3
Stream 3 clear transfer error interrupt flag.
Definition stm32h723xx.h:9020
DMA_LISR_TEIF1
#define DMA_LISR_TEIF1
Stream 1 transfer error interrupt flag.
Definition stm32h723xx.h:8926
DMA_HISR_HTIF6
#define DMA_HISR_HTIF6
Stream 6 half transfer interrupt flag.
Definition stm32h723xx.h:8970
DMA_HISR_FEIF5
#define DMA_HISR_FEIF5
Stream 5 FIFO error interrupt flag.
Definition stm32h723xx.h:8994
DMA_HIFCR_CDMEIF4
#define DMA_HIFCR_CDMEIF4
Stream 4 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9130
DMA_LIFCR_CHTIF3
#define DMA_LIFCR_CHTIF3
Stream 3 clear half transfer interrupt flag.
Definition stm32h723xx.h:9017
DMA_SxCR_PFCTRL
#define DMA_SxCR_PFCTRL
Peripheral flow controller.
Definition stm32h723xx.h:8830
DMA_SxCR_HTIE
#define DMA_SxCR_HTIE
Half transfer interrupt enable.
Definition stm32h723xx.h:8836
DMA_SxCR_PL
#define DMA_SxCR_PL
Priority level.
Definition stm32h723xx.h:8798
DMA_HIFCR_CDMEIF5
#define DMA_HIFCR_CDMEIF5
Stream 5 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9115
DMA_SxCR_DIR
#define DMA_SxCR_DIR
Data transfer direction.
Definition stm32h723xx.h:8825
DMA_HISR_TEIF6
#define DMA_HISR_TEIF6
Stream 6 transfer error interrupt flag.
Definition stm32h723xx.h:8973
DMA_HIFCR_CFEIF4
#define DMA_HIFCR_CFEIF4
Stream 4 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9133
DMA_SxCR_PINC
#define DMA_SxCR_PINC
Peripheral increment mode.
Definition stm32h723xx.h:8819
DMA_HIFCR_CHTIF5
#define DMA_HIFCR_CHTIF5
Stream 5 clear half transfer interrupt flag.
Definition stm32h723xx.h:9109
DMA_HIFCR_CTEIF5
#define DMA_HIFCR_CTEIF5
Stream 5 clear transfer error interrupt flag.
Definition stm32h723xx.h:9112
DMA_HIFCR_CFEIF6
#define DMA_HIFCR_CFEIF6
Stream 6 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9103
DMA_HISR_DMEIF7
#define DMA_HISR_DMEIF7
Stream 7 direct mode error interrupt flag.
Definition stm32h723xx.h:8961
DMA_SxCR_TRBUFF
#define DMA_SxCR_TRBUFF
bufferable transfers enabled/disable
Definition stm32h723xx.h:8789
DMAMUX_CxCR_DMAREQ_ID
#define DMAMUX_CxCR_DMAREQ_ID
DMA request identification.
Definition stm32h723xx.h:9158
DMA_HIFCR_CTCIF4
#define DMA_HIFCR_CTCIF4
Stream 4 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9121
DMA_SxFCR_FTH
#define DMA_SxFCR_FTH
FIFO threshold selection.
Definition stm32h723xx.h:8883
DMA_LISR_TCIF3
#define DMA_LISR_TCIF3
Stream 3 transfer complete interrupt flag.
Definition stm32h723xx.h:8890
DMA_LIFCR_CHTIF0
#define DMA_LIFCR_CHTIF0
Stream 0 clear half transfer interrupt flag.
Definition stm32h723xx.h:9062
DMA_SxCR_PBURST
#define DMA_SxCR_PBURST
Peripheral burst transfer configuration.
Definition stm32h723xx.h:8784
DMA_HIFCR_CFEIF7
#define DMA_HIFCR_CFEIF7
Stream 7 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9088
DMA_LIFCR_CTCIF3
#define DMA_LIFCR_CTCIF3
Stream 3 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9014
DMA_LIFCR_CTCIF2
#define DMA_LIFCR_CTCIF2
Stream 2 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9029
DMA_LISR_FEIF3
#define DMA_LISR_FEIF3
Stream 3 FIFO error interrupt flag.
Definition stm32h723xx.h:8902
DMA_SxCR_DBM
#define DMA_SxCR_DBM
Double buffer mode.
Definition stm32h723xx.h:8795
DMA_SxFCR_FS
#define DMA_SxFCR_FS
FIFO status.
Definition stm32h723xx.h:8874
DMA_LIFCR_CTEIF0
#define DMA_LIFCR_CTEIF0
Stream 0 clear transfer error interrupt flag.
Definition stm32h723xx.h:9065
DMA_SxCR_MBURST
#define DMA_SxCR_MBURST
Memory burst transfer configuration.
Definition stm32h723xx.h:8779
DMA_LISR_TEIF3
#define DMA_LISR_TEIF3
Stream 3 transfer error interrupt flag.
Definition stm32h723xx.h:8896
DMA_LISR_HTIF0
#define DMA_LISR_HTIF0
Stream 0 half transfer interrupt flag.
Definition stm32h723xx.h:8938
DMA_SxNDT
#define DMA_SxNDT
Number of data items to transfer.
Definition stm32h723xx.h:8850
DMA_HISR_TCIF5
#define DMA_HISR_TCIF5
Stream 5 transfer complete interrupt flag.
Definition stm32h723xx.h:8982
DMA_HIFCR_CTEIF6
#define DMA_HIFCR_CTEIF6
Stream 6 clear transfer error interrupt flag.
Definition stm32h723xx.h:9097
DMA_SxCR_TCIE
#define DMA_SxCR_TCIE
Transfer complete interrupt enable.
Definition stm32h723xx.h:8833
DMA_LISR_HTIF2
#define DMA_LISR_HTIF2
Stream 2 half transfer interrupt flag.
Definition stm32h723xx.h:8908
DMA_LISR_DMEIF0
#define DMA_LISR_DMEIF0
Stream 0 direct mode error interrupt flag.
Definition stm32h723xx.h:8944
DMA_LIFCR_CTCIF1
#define DMA_LIFCR_CTCIF1
Stream 1 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9044
DMA_LISR_TEIF2
#define DMA_LISR_TEIF2
Stream 2 transfer error interrupt flag.
Definition stm32h723xx.h:8911
DMA_LIFCR_CDMEIF2
#define DMA_LIFCR_CDMEIF2
Stream 2 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9038
DMA_SxCR_MINC
#define DMA_SxCR_MINC
Memory increment mode.
Definition stm32h723xx.h:8816
DMA_LISR_FEIF0
#define DMA_LISR_FEIF0
Stream 0 FIFO error interrupt flag.
Definition stm32h723xx.h:8947
DMA_HIFCR_CDMEIF6
#define DMA_HIFCR_CDMEIF6
Stream 6 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9100
DMA_HIFCR_CTEIF7
#define DMA_HIFCR_CTEIF7
Stream 7 clear transfer error interrupt flag.
Definition stm32h723xx.h:9082
DMA_HISR_HTIF5
#define DMA_HISR_HTIF5
Stream 5 half transfer interrupt flag.
Definition stm32h723xx.h:8985
DMA_SxFCR_DMDIS
#define DMA_SxFCR_DMDIS
Direct mode disable.
Definition stm32h723xx.h:8880
DMA_HISR_TEIF4
#define DMA_HISR_TEIF4
Stream 4 transfer error interrupt flag.
Definition stm32h723xx.h:9003
DMA_HIFCR_CHTIF7
#define DMA_HIFCR_CHTIF7
Stream 7 clear half transfer interrupt flag.
Definition stm32h723xx.h:9079
DMA_HISR_TEIF7
#define DMA_HISR_TEIF7
Stream 7 transfer error interrupt flag.
Definition stm32h723xx.h:8958
DMA_LIFCR_CFEIF1
#define DMA_LIFCR_CFEIF1
Stream 1 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9056
DMA_LISR_FEIF2
#define DMA_LISR_FEIF2
Stream 2 FIFO error interrupt flag.
Definition stm32h723xx.h:8917
DMA_HIFCR_CFEIF5
#define DMA_HIFCR_CFEIF5
Stream 5 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9118
DMA_LIFCR_CDMEIF1
#define DMA_LIFCR_CDMEIF1
Stream 1 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9053
DMA_HIFCR_CTEIF4
#define DMA_HIFCR_CTEIF4
Stream 4 clear transfer error interrupt flag.
Definition stm32h723xx.h:9127
DMA_LISR_HTIF3
#define DMA_LISR_HTIF3
Stream 3 half transfer interrupt flag.
Definition stm32h723xx.h:8893
DMA_LISR_DMEIF1
#define DMA_LISR_DMEIF1
Stream 1 direct mode error interrupt flag.
Definition stm32h723xx.h:8929
DMA_HIFCR_CTCIF5
#define DMA_HIFCR_CTCIF5
Stream 5 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9106
DMA_LIFCR_CTEIF2
#define DMA_LIFCR_CTEIF2
Stream 2 clear transfer error interrupt flag.
Definition stm32h723xx.h:9035
DMA_SxCR_EN
#define DMA_SxCR_EN
Stream enable / flag stream ready when read low.
Definition stm32h723xx.h:8845
DMA_LIFCR_CTCIF0
#define DMA_LIFCR_CTCIF0
Stream 0 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9059
DMA_HISR_DMEIF6
#define DMA_HISR_DMEIF6
Stream 6 direct mode error interrupt flag.
Definition stm32h723xx.h:8976
DMA_SxFCR_FEIE
#define DMA_SxFCR_FEIE
FIFO error interrupt enable.
Definition stm32h723xx.h:8871
DMA_LISR_DMEIF2
#define DMA_LISR_DMEIF2
Stream 2 direct mode error interrupt flag.
Definition stm32h723xx.h:8914
DMA_LIFCR_CDMEIF3
#define DMA_LIFCR_CDMEIF3
Stream 3 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9023
DMA_HISR_DMEIF5
#define DMA_HISR_DMEIF5
Stream 5 direct mode error interrupt flag.
Definition stm32h723xx.h:8991
DMA_HISR_FEIF4
#define DMA_HISR_FEIF4
Stream 4 FIFO error interrupt flag.
Definition stm32h723xx.h:9009
DMA_SxCR_DMEIE
#define DMA_SxCR_DMEIE
Direct mode error interrupt enable.
Definition stm32h723xx.h:8842
DMA_HIFCR_CTCIF6
#define DMA_HIFCR_CTCIF6
Stream 6 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9091
DMA_HISR_TCIF7
#define DMA_HISR_TCIF7
Stream 7 transfer complete interrupt flag.
Definition stm32h723xx.h:8952
DMA_HISR_TCIF6
#define DMA_HISR_TCIF6
Stream 6 transfer complete interrupt flag.
Definition stm32h723xx.h:8967
DMA_LIFCR_CHTIF1
#define DMA_LIFCR_CHTIF1
Stream 1 clear half transfer interrupt flag.
Definition stm32h723xx.h:9047
DMA_LISR_TEIF0
#define DMA_LISR_TEIF0
Stream 0 transfer error interrupt flag.
Definition stm32h723xx.h:8941
DMA_HIFCR_CDMEIF7
#define DMA_HIFCR_CDMEIF7
Stream 7 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9085
DMA_LIFCR_CFEIF3
#define DMA_LIFCR_CFEIF3
Stream 3 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9026
DMA_HISR_HTIF4
#define DMA_HISR_HTIF4
Stream 4 half transfer interrupt flag.
Definition stm32h723xx.h:9000
DMA_LISR_TCIF0
#define DMA_LISR_TCIF0
Stream 0 transfer complete interrupt flag.
Definition stm32h723xx.h:8935
DMA_SxCR_CIRC
#define DMA_SxCR_CIRC
Circular mode.
Definition stm32h723xx.h:8822
DMA_SxCR_CT
#define DMA_SxCR_CT
Current target (only in double buffer mode).
Definition stm32h723xx.h:8792
DMA_HISR_FEIF7
#define DMA_HISR_FEIF7
Stream 7 FIFO error interrupt flag.
Definition stm32h723xx.h:8964
DMA_LIFCR_CFEIF0
#define DMA_LIFCR_CFEIF0
Stream 0 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9071
DMA_HIFCR_CTCIF7
#define DMA_HIFCR_CTCIF7
Stream 7 clear transfer complete interrupt flag.
Definition stm32h723xx.h:9076
DMA_LISR_TCIF1
#define DMA_LISR_TCIF1
Stream 1 transfer complete interrupt flag.
Definition stm32h723xx.h:8920
DMA_SxM1AR_M1A
#define DMA_SxM1AR_M1A
Memory 1 Address.
Definition stm32h723xx.h:9148
DMA_LIFCR_CFEIF2
#define DMA_LIFCR_CFEIF2
Stream 2 clear FIFO error interrupt flag.
Definition stm32h723xx.h:9041
DMA_LIFCR_CHTIF2
#define DMA_LIFCR_CHTIF2
Stream 2 clear half transfer interrupt flag.
Definition stm32h723xx.h:9032
DMA_SxCR_MSIZE
#define DMA_SxCR_MSIZE
Memory data size.
Definition stm32h723xx.h:8806
DMA_SxCR_PSIZE
#define DMA_SxCR_PSIZE
Definition stm32h723xx.h:8811
DMA_SxCR_PINCOS
#define DMA_SxCR_PINCOS
Peripheral increment offset size.
Definition stm32h723xx.h:8803
DMA_HIFCR_CHTIF6
#define DMA_HIFCR_CHTIF6
Stream 6 clear half transfer interrupt flag.
Definition stm32h723xx.h:9094
DMA_SxCR_TEIE
#define DMA_SxCR_TEIE
Transfer error interrupt enable.
Definition stm32h723xx.h:8839
DMA_HISR_TEIF5
#define DMA_HISR_TEIF5
Stream 5 transfer error interrupt flag.
Definition stm32h723xx.h:8988
DMA_LISR_TCIF2
#define DMA_LISR_TCIF2
Stream 2 transfer complete interrupt flag.
Definition stm32h723xx.h:8905
DMA_HISR_HTIF7
#define DMA_HISR_HTIF7
Stream 7 half transfer interrupt flag.
Definition stm32h723xx.h:8955
DMA_LIFCR_CTEIF1
#define DMA_LIFCR_CTEIF1
Stream 1 clear transfer error interrupt flag.
Definition stm32h723xx.h:9050
DMA_HISR_DMEIF4
#define DMA_HISR_DMEIF4
Stream 4 direct mode error interrupt flag.
Definition stm32h723xx.h:9006
DMA_HIFCR_CHTIF4
#define DMA_HIFCR_CHTIF4
Stream 4 clear half transfer interrupt flag.
Definition stm32h723xx.h:9124
DMA_HISR_FEIF6
#define DMA_HISR_FEIF6
Stream 6 FIFO error interrupt flag.
Definition stm32h723xx.h:8979
DMA_LISR_FEIF1
#define DMA_LISR_FEIF1
Stream 1 FIFO error interrupt flag.
Definition stm32h723xx.h:8932
DMA_HISR_TCIF4
#define DMA_HISR_TCIF4
Stream 4 transfer complete interrupt flag.
Definition stm32h723xx.h:8997
DMA_LIFCR_CDMEIF0
#define DMA_LIFCR_CDMEIF0
Stream 0 clear direct mode error interrupt flag.
Definition stm32h723xx.h:9068
DMAMUX1_Channel0
#define DMAMUX1_Channel0
Definition stm32h723xx.h:2610
DMA1_Stream0_BASE
#define DMA1_Stream0_BASE
Definition stm32h723xx.h:2316
DMA1_Stream5_BASE
#define DMA1_Stream5_BASE
Definition stm32h723xx.h:2321
DMA1_Stream2_BASE
#define DMA1_Stream2_BASE
Definition stm32h723xx.h:2318
DMA1_Stream6_BASE
#define DMA1_Stream6_BASE
Definition stm32h723xx.h:2322
DMA1_Stream1_BASE
#define DMA1_Stream1_BASE
Definition stm32h723xx.h:2317
DMA1_Stream4_BASE
#define DMA1_Stream4_BASE
Definition stm32h723xx.h:2320
DMA1_Stream7_BASE
#define DMA1_Stream7_BASE
Definition stm32h723xx.h:2323
DMA1_BASE
#define DMA1_BASE
Definition stm32h723xx.h:2122
DMA1_Stream3_BASE
#define DMA1_Stream3_BASE
Definition stm32h723xx.h:2319
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
stm32h7xx_ll_dmamux.h
Header file of DMAMUX LL module.
DMAMUX_Channel_TypeDef
Definition stm32h723xx.h:634
DMA_Stream_TypeDef
DMA Controller.
Definition stm32h723xx.h:601
DMA_TypeDef
Definition stm32h723xx.h:611
DMA_TypeDef::HISR
__IO uint32_t HISR
DMA high interrupt status register, Address offset: 0x04.
Definition stm32h723xx.h:613
DMA_TypeDef::LIFCR
__IO uint32_t LIFCR
DMA low interrupt flag clear register, Address offset: 0x08.
Definition stm32h723xx.h:614
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
DMA high interrupt flag clear register, Address offset: 0x0C.
Definition stm32h723xx.h:615
DMA_TypeDef::LISR
__IO uint32_t LISR
DMA low interrupt status register, Address offset: 0x00.
Definition stm32h723xx.h:612