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stm32h7xx_ll_lpuart.h
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_LPUART_H
21#define STM32H7xx_LL_LPUART_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined (LPUART1)
35
36/** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
43 * @{
44 */
45/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
46static const uint16_t LPUART_PRESCALER_TAB[] =
47{
48 (uint16_t)1,
49 (uint16_t)2,
50 (uint16_t)4,
51 (uint16_t)6,
52 (uint16_t)8,
53 (uint16_t)10,
54 (uint16_t)12,
55 (uint16_t)16,
56 (uint16_t)32,
57 (uint16_t)64,
58 (uint16_t)128,
59 (uint16_t)256,
60 (uint16_t)256,
61 (uint16_t)256,
62 (uint16_t)256,
63 (uint16_t)256
64};
65/**
66 * @}
67 */
68
69/* Private constants ---------------------------------------------------------*/
70/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
71 * @{
72 */
73/* Defines used in Baud Rate related macros and corresponding register setting computation */
74#define LPUART_LPUARTDIV_FREQ_MUL 256U
75#define LPUART_BRR_MASK 0x000FFFFFU
76#define LPUART_BRR_MIN_VALUE 0x00000300U
77/**
78 * @}
79 */
80
81
82/* Private macros ------------------------------------------------------------*/
83#if defined(USE_FULL_LL_DRIVER)
84/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
85 * @{
86 */
87/**
88 * @}
89 */
90#endif /*USE_FULL_LL_DRIVER*/
91
92/* Exported types ------------------------------------------------------------*/
93#if defined(USE_FULL_LL_DRIVER)
94/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
95 * @{
96 */
97
98/**
99 * @brief LL LPUART Init Structure definition
100 */
101typedef struct
102{
103 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
104 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
105
106 This feature can be modified afterwards using unitary
107 function @ref LL_LPUART_SetPrescaler().*/
108
109 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
110
111 This feature can be modified afterwards using unitary
112 function @ref LL_LPUART_SetBaudRate().*/
113
114 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
115 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
116
117 This feature can be modified afterwards using unitary
118 function @ref LL_LPUART_SetDataWidth().*/
119
120 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
121 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
122
123 This feature can be modified afterwards using unitary
124 function @ref LL_LPUART_SetStopBitsLength().*/
125
126 uint32_t Parity; /*!< Specifies the parity mode.
127 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
128
129 This feature can be modified afterwards using unitary
130 function @ref LL_LPUART_SetParity().*/
131
132 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
133 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
134
135 This feature can be modified afterwards using unitary
136 function @ref LL_LPUART_SetTransferDirection().*/
137
138 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
139 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
140
141 This feature can be modified afterwards using unitary
142 function @ref LL_LPUART_SetHWFlowCtrl().*/
143
144} LL_LPUART_InitTypeDef;
145
146/**
147 * @}
148 */
149#endif /* USE_FULL_LL_DRIVER */
150
151/* Exported constants --------------------------------------------------------*/
152/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
153 * @{
154 */
155
156/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
157 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
158 * @{
159 */
160#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
161#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
162#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
163#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
164#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
165#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
166#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
167#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
168#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
169/**
170 * @}
171 */
172
173/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
174 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
175 * @{
176 */
177#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
178#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
179#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
180#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
181#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
182#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
183#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
184#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
185#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
186#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
187#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
188#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
189#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
190#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
191#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
192#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
193#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
194#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
195#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
196#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
197#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
198/**
199 * @}
200 */
201
202/** @defgroup LPUART_LL_EC_IT IT Defines
203 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
204 * @{
205 */
206#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
207#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
208 interrupt enable */
209#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
210#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
211 not full interrupt enable */
212#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
213#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
214#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
215#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
216#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
217#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
218#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
219#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
220#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
221/**
222 * @}
223 */
224
225/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
226 * @{
227 */
228#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
229#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
230#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
231#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
232#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
233#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
234/**
235 * @}
236 */
237
238/** @defgroup LPUART_LL_EC_DIRECTION Direction
239 * @{
240 */
241#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
242#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
243#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
244#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
245/**
246 * @}
247 */
248
249/** @defgroup LPUART_LL_EC_PARITY Parity Control
250 * @{
251 */
252#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
253#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
254#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
255/**
256 * @}
257 */
258
259/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
260 * @{
261 */
262#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
263#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
264/**
265 * @}
266 */
267
268/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
269 * @{
270 */
271#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
272#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
273#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
274/**
275 * @}
276 */
277
278/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
279 * @{
280 */
281#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
282#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
283#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
284#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
285 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
286#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
287#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
288 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
289#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
290 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
291#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
292 USART_PRESC_PRESCALER_1 |\
293 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
294#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
295#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
296 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
297#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
298 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
299#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
300 USART_PRESC_PRESCALER_1 |\
301 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
302/**
303 * @}
304 */
305
306/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
307 * @{
308 */
309#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
310#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
311/**
312 * @}
313 */
314
315/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
316 * @{
317 */
318#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
319#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
320/**
321 * @}
322 */
323
324/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
325 * @{
326 */
327#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
328#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
329/**
330 * @}
331 */
332
333/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
334 * @{
335 */
336#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
337#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
338/**
339 * @}
340 */
341
342/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
343 * @{
344 */
345#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
346 in positive/direct logic. (1=H, 0=L) */
347#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
348 in negative/inverse logic. (1=L, 0=H).
349 The parity bit is also inverted. */
350/**
351 * @}
352 */
353
354/** @defgroup LPUART_LL_EC_BITORDER Bit Order
355 * @{
356 */
357#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
358 following the start bit */
359#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
360 following the start bit */
361/**
362 * @}
363 */
364
365/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
366 * @{
367 */
368#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
369#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
370/**
371 * @}
372 */
373
374/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
375 * @{
376 */
377#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
378#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
379 when there is space in the receive buffer */
380#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
381 when the nCTS input is asserted (tied to 0)*/
382#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
383/**
384 * @}
385 */
386
387/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
388 * @{
389 */
390#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
391#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
392#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
393/**
394 * @}
395 */
396
397/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
398 * @{
399 */
400#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
401#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
402/**
403 * @}
404 */
405
406/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
407 * @{
408 */
409#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
410#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
411/**
412 * @}
413 */
414
415/**
416 * @}
417 */
418
419/* Exported macro ------------------------------------------------------------*/
420/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
421 * @{
422 */
423
424/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
425 * @{
426 */
427
428/**
429 * @brief Write a value in LPUART register
430 * @param __INSTANCE__ LPUART Instance
431 * @param __REG__ Register to be written
432 * @param __VALUE__ Value to be written in the register
433 * @retval None
434 */
435#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
436
437/**
438 * @brief Read a value in LPUART register
439 * @param __INSTANCE__ LPUART Instance
440 * @param __REG__ Register to be read
441 * @retval Register value
442 */
443#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
444/**
445 * @}
446 */
447
448/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
449 * @{
450 */
451
452/**
453 * @brief Compute LPUARTDIV value according to Peripheral Clock and
454 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
455 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
456 * @param __PRESCALER__ This parameter can be one of the following values:
457 * @arg @ref LL_LPUART_PRESCALER_DIV1
458 * @arg @ref LL_LPUART_PRESCALER_DIV2
459 * @arg @ref LL_LPUART_PRESCALER_DIV4
460 * @arg @ref LL_LPUART_PRESCALER_DIV6
461 * @arg @ref LL_LPUART_PRESCALER_DIV8
462 * @arg @ref LL_LPUART_PRESCALER_DIV10
463 * @arg @ref LL_LPUART_PRESCALER_DIV12
464 * @arg @ref LL_LPUART_PRESCALER_DIV16
465 * @arg @ref LL_LPUART_PRESCALER_DIV32
466 * @arg @ref LL_LPUART_PRESCALER_DIV64
467 * @arg @ref LL_LPUART_PRESCALER_DIV128
468 * @arg @ref LL_LPUART_PRESCALER_DIV256
469 * @param __BAUDRATE__ Baud Rate value to achieve
470 * @retval LPUARTDIV value to be used for BRR register filling
471 */
472#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
473 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
474 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
475
476/**
477 * @}
478 */
479
480/**
481 * @}
482 */
483
484/* Exported functions --------------------------------------------------------*/
485/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
486 * @{
487 */
488
489/** @defgroup LPUART_LL_EF_Configuration Configuration functions
490 * @{
491 */
492
493/**
494 * @brief LPUART Enable
495 * @rmtoll CR1 UE LL_LPUART_Enable
496 * @param LPUARTx LPUART Instance
497 * @retval None
498 */
499__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
500{
501 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
502}
503
504/**
505 * @brief LPUART Disable
506 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
507 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
508 * flags, in the LPUARTx_ISR are set to their default values.
509 * @note In order to go into low-power mode without generating errors on the line,
510 * the TE bit must be reset before and the software must wait
511 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
512 * The DMA requests are also reset when UE = 0 so the DMA channel must
513 * be disabled before resetting the UE bit.
514 * @rmtoll CR1 UE LL_LPUART_Disable
515 * @param LPUARTx LPUART Instance
516 * @retval None
517 */
518__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
519{
520 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
521}
522
523/**
524 * @brief Indicate if LPUART is enabled
525 * @rmtoll CR1 UE LL_LPUART_IsEnabled
526 * @param LPUARTx LPUART Instance
527 * @retval State of bit (1 or 0).
528 */
529__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
530{
531 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
532}
533
534/**
535 * @brief FIFO Mode Enable
536 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
537 * @param LPUARTx LPUART Instance
538 * @retval None
539 */
540__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
541{
542 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
543}
544
545/**
546 * @brief FIFO Mode Disable
547 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
548 * @param LPUARTx LPUART Instance
549 * @retval None
550 */
551__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
552{
553 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
554}
555
556/**
557 * @brief Indicate if FIFO Mode is enabled
558 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
559 * @param LPUARTx LPUART Instance
560 * @retval State of bit (1 or 0).
561 */
562__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
563{
564 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
565}
566
567/**
568 * @brief Configure TX FIFO Threshold
569 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
570 * @param LPUARTx LPUART Instance
571 * @param Threshold This parameter can be one of the following values:
572 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
573 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
574 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
575 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
576 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
577 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
578 * @retval None
579 */
580__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
581{
582 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
583}
584
585/**
586 * @brief Return TX FIFO Threshold Configuration
587 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
588 * @param LPUARTx LPUART Instance
589 * @retval Returned value can be one of the following values:
590 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
591 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
592 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
593 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
594 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
595 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
596 */
597__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
598{
599 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
600}
601
602/**
603 * @brief Configure RX FIFO Threshold
604 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
605 * @param LPUARTx LPUART Instance
606 * @param Threshold This parameter can be one of the following values:
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
608 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
609 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
610 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
611 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
612 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
613 * @retval None
614 */
615__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
616{
617 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
618}
619
620/**
621 * @brief Return RX FIFO Threshold Configuration
622 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
623 * @param LPUARTx LPUART Instance
624 * @retval Returned value can be one of the following values:
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
626 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
627 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
628 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
629 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
630 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
631 */
632__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
633{
634 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
635}
636
637/**
638 * @brief Configure TX and RX FIFOs Threshold
639 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
640 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
641 * @param LPUARTx LPUART Instance
642 * @param TXThreshold This parameter can be one of the following values:
643 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
644 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
645 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
646 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
647 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
648 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
649 * @param RXThreshold This parameter can be one of the following values:
650 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
651 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
652 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
653 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
654 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
655 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
656 * @retval None
657 */
658__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
659{
660 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
661 (RXThreshold << USART_CR3_RXFTCFG_Pos));
662}
663
664/**
665 * @brief LPUART enabled in STOP Mode
666 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
667 * LPUART clock selection is HSI or LSE in RCC.
668 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
669 * @param LPUARTx LPUART Instance
670 * @retval None
671 */
672__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
673{
674 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
675}
676
677/**
678 * @brief LPUART disabled in STOP Mode
679 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
680 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
681 * @param LPUARTx LPUART Instance
682 * @retval None
683 */
684__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
685{
686 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
687}
688
689/**
690 * @brief Indicate if LPUART is enabled in STOP Mode
691 * (able to wake up MCU from Stop mode or not)
692 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
693 * @param LPUARTx LPUART Instance
694 * @retval State of bit (1 or 0).
695 */
696__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
697{
698 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
699}
700
701/**
702 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
703 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
704 * @param LPUARTx LPUART Instance
705 * @retval None
706 */
707__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
708{
709 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
710}
711
712/**
713 * @brief Receiver Disable
714 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
715 * @param LPUARTx LPUART Instance
716 * @retval None
717 */
718__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
719{
720 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
721}
722
723/**
724 * @brief Transmitter Enable
725 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
726 * @param LPUARTx LPUART Instance
727 * @retval None
728 */
729__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
730{
731 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
732}
733
734/**
735 * @brief Transmitter Disable
736 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
737 * @param LPUARTx LPUART Instance
738 * @retval None
739 */
740__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
741{
742 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
743}
744
745/**
746 * @brief Configure simultaneously enabled/disabled states
747 * of Transmitter and Receiver
748 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
749 * CR1 TE LL_LPUART_SetTransferDirection
750 * @param LPUARTx LPUART Instance
751 * @param TransferDirection This parameter can be one of the following values:
752 * @arg @ref LL_LPUART_DIRECTION_NONE
753 * @arg @ref LL_LPUART_DIRECTION_RX
754 * @arg @ref LL_LPUART_DIRECTION_TX
755 * @arg @ref LL_LPUART_DIRECTION_TX_RX
756 * @retval None
757 */
758__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
759{
760 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
761}
762
763/**
764 * @brief Return enabled/disabled states of Transmitter and Receiver
765 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
766 * CR1 TE LL_LPUART_GetTransferDirection
767 * @param LPUARTx LPUART Instance
768 * @retval Returned value can be one of the following values:
769 * @arg @ref LL_LPUART_DIRECTION_NONE
770 * @arg @ref LL_LPUART_DIRECTION_RX
771 * @arg @ref LL_LPUART_DIRECTION_TX
772 * @arg @ref LL_LPUART_DIRECTION_TX_RX
773 */
774__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
775{
776 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
777}
778
779/**
780 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
781 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
782 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
783 * (depending on data width) and parity is checked on the received data.
784 * @rmtoll CR1 PS LL_LPUART_SetParity\n
785 * CR1 PCE LL_LPUART_SetParity
786 * @param LPUARTx LPUART Instance
787 * @param Parity This parameter can be one of the following values:
788 * @arg @ref LL_LPUART_PARITY_NONE
789 * @arg @ref LL_LPUART_PARITY_EVEN
790 * @arg @ref LL_LPUART_PARITY_ODD
791 * @retval None
792 */
793__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
794{
795 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
796}
797
798/**
799 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
800 * @rmtoll CR1 PS LL_LPUART_GetParity\n
801 * CR1 PCE LL_LPUART_GetParity
802 * @param LPUARTx LPUART Instance
803 * @retval Returned value can be one of the following values:
804 * @arg @ref LL_LPUART_PARITY_NONE
805 * @arg @ref LL_LPUART_PARITY_EVEN
806 * @arg @ref LL_LPUART_PARITY_ODD
807 */
808__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
809{
810 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
811}
812
813/**
814 * @brief Set Receiver Wake Up method from Mute mode.
815 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
816 * @param LPUARTx LPUART Instance
817 * @param Method This parameter can be one of the following values:
818 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
819 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
820 * @retval None
821 */
822__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
823{
824 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
825}
826
827/**
828 * @brief Return Receiver Wake Up method from Mute mode
829 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
830 * @param LPUARTx LPUART Instance
831 * @retval Returned value can be one of the following values:
832 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
833 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
834 */
835__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
836{
837 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
838}
839
840/**
841 * @brief Set Word length (nb of data bits, excluding start and stop bits)
842 * @rmtoll CR1 M LL_LPUART_SetDataWidth
843 * @param LPUARTx LPUART Instance
844 * @param DataWidth This parameter can be one of the following values:
845 * @arg @ref LL_LPUART_DATAWIDTH_7B
846 * @arg @ref LL_LPUART_DATAWIDTH_8B
847 * @arg @ref LL_LPUART_DATAWIDTH_9B
848 * @retval None
849 */
850__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
851{
852 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
853}
854
855/**
856 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
857 * @rmtoll CR1 M LL_LPUART_GetDataWidth
858 * @param LPUARTx LPUART Instance
859 * @retval Returned value can be one of the following values:
860 * @arg @ref LL_LPUART_DATAWIDTH_7B
861 * @arg @ref LL_LPUART_DATAWIDTH_8B
862 * @arg @ref LL_LPUART_DATAWIDTH_9B
863 */
864__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
865{
866 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
867}
868
869/**
870 * @brief Allow switch between Mute Mode and Active mode
871 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
872 * @param LPUARTx LPUART Instance
873 * @retval None
874 */
875__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
876{
877 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
878}
879
880/**
881 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
882 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
883 * @param LPUARTx LPUART Instance
884 * @retval None
885 */
886__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
887{
888 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
889}
890
891/**
892 * @brief Indicate if switch between Mute Mode and Active mode is allowed
893 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
894 * @param LPUARTx LPUART Instance
895 * @retval State of bit (1 or 0).
896 */
897__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
898{
899 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
900}
901
902/**
903 * @brief Configure Clock source prescaler for baudrate generator and oversampling
904 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
905 * @param LPUARTx LPUART Instance
906 * @param PrescalerValue This parameter can be one of the following values:
907 * @arg @ref LL_LPUART_PRESCALER_DIV1
908 * @arg @ref LL_LPUART_PRESCALER_DIV2
909 * @arg @ref LL_LPUART_PRESCALER_DIV4
910 * @arg @ref LL_LPUART_PRESCALER_DIV6
911 * @arg @ref LL_LPUART_PRESCALER_DIV8
912 * @arg @ref LL_LPUART_PRESCALER_DIV10
913 * @arg @ref LL_LPUART_PRESCALER_DIV12
914 * @arg @ref LL_LPUART_PRESCALER_DIV16
915 * @arg @ref LL_LPUART_PRESCALER_DIV32
916 * @arg @ref LL_LPUART_PRESCALER_DIV64
917 * @arg @ref LL_LPUART_PRESCALER_DIV128
918 * @arg @ref LL_LPUART_PRESCALER_DIV256
919 * @retval None
920 */
921__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
922{
923 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
924}
925
926/**
927 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
928 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
929 * @param LPUARTx LPUART Instance
930 * @retval Returned value can be one of the following values:
931 * @arg @ref LL_LPUART_PRESCALER_DIV1
932 * @arg @ref LL_LPUART_PRESCALER_DIV2
933 * @arg @ref LL_LPUART_PRESCALER_DIV4
934 * @arg @ref LL_LPUART_PRESCALER_DIV6
935 * @arg @ref LL_LPUART_PRESCALER_DIV8
936 * @arg @ref LL_LPUART_PRESCALER_DIV10
937 * @arg @ref LL_LPUART_PRESCALER_DIV12
938 * @arg @ref LL_LPUART_PRESCALER_DIV16
939 * @arg @ref LL_LPUART_PRESCALER_DIV32
940 * @arg @ref LL_LPUART_PRESCALER_DIV64
941 * @arg @ref LL_LPUART_PRESCALER_DIV128
942 * @arg @ref LL_LPUART_PRESCALER_DIV256
943 */
944__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
945{
946 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
947}
948
949/**
950 * @brief Set the length of the stop bits
951 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
952 * @param LPUARTx LPUART Instance
953 * @param StopBits This parameter can be one of the following values:
954 * @arg @ref LL_LPUART_STOPBITS_1
955 * @arg @ref LL_LPUART_STOPBITS_2
956 * @retval None
957 */
958__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
959{
960 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
961}
962
963/**
964 * @brief Retrieve the length of the stop bits
965 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
966 * @param LPUARTx LPUART Instance
967 * @retval Returned value can be one of the following values:
968 * @arg @ref LL_LPUART_STOPBITS_1
969 * @arg @ref LL_LPUART_STOPBITS_2
970 */
971__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
972{
973 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
974}
975
976/**
977 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
978 * @note Call of this function is equivalent to following function call sequence :
979 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
980 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
981 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
982 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
983 * CR1 PCE LL_LPUART_ConfigCharacter\n
984 * CR1 M LL_LPUART_ConfigCharacter\n
985 * CR2 STOP LL_LPUART_ConfigCharacter
986 * @param LPUARTx LPUART Instance
987 * @param DataWidth This parameter can be one of the following values:
988 * @arg @ref LL_LPUART_DATAWIDTH_7B
989 * @arg @ref LL_LPUART_DATAWIDTH_8B
990 * @arg @ref LL_LPUART_DATAWIDTH_9B
991 * @param Parity This parameter can be one of the following values:
992 * @arg @ref LL_LPUART_PARITY_NONE
993 * @arg @ref LL_LPUART_PARITY_EVEN
994 * @arg @ref LL_LPUART_PARITY_ODD
995 * @param StopBits This parameter can be one of the following values:
996 * @arg @ref LL_LPUART_STOPBITS_1
997 * @arg @ref LL_LPUART_STOPBITS_2
998 * @retval None
999 */
1000__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1001 uint32_t StopBits)
1002{
1003 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1004 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1005}
1006
1007/**
1008 * @brief Configure TX/RX pins swapping setting.
1009 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1010 * @param LPUARTx LPUART Instance
1011 * @param SwapConfig This parameter can be one of the following values:
1012 * @arg @ref LL_LPUART_TXRX_STANDARD
1013 * @arg @ref LL_LPUART_TXRX_SWAPPED
1014 * @retval None
1015 */
1016__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1017{
1018 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1019}
1020
1021/**
1022 * @brief Retrieve TX/RX pins swapping configuration.
1023 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1024 * @param LPUARTx LPUART Instance
1025 * @retval Returned value can be one of the following values:
1026 * @arg @ref LL_LPUART_TXRX_STANDARD
1027 * @arg @ref LL_LPUART_TXRX_SWAPPED
1028 */
1029__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1030{
1031 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1032}
1033
1034/**
1035 * @brief Configure RX pin active level logic
1036 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1037 * @param LPUARTx LPUART Instance
1038 * @param PinInvMethod This parameter can be one of the following values:
1039 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1040 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1041 * @retval None
1042 */
1043__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1044{
1045 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1046}
1047
1048/**
1049 * @brief Retrieve RX pin active level logic configuration
1050 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1051 * @param LPUARTx LPUART Instance
1052 * @retval Returned value can be one of the following values:
1053 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1054 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1055 */
1056__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1057{
1058 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1059}
1060
1061/**
1062 * @brief Configure TX pin active level logic
1063 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1064 * @param LPUARTx LPUART Instance
1065 * @param PinInvMethod This parameter can be one of the following values:
1066 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1067 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1068 * @retval None
1069 */
1070__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1071{
1072 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1073}
1074
1075/**
1076 * @brief Retrieve TX pin active level logic configuration
1077 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1078 * @param LPUARTx LPUART Instance
1079 * @retval Returned value can be one of the following values:
1080 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1081 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1082 */
1083__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1084{
1085 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1086}
1087
1088/**
1089 * @brief Configure Binary data logic.
1090 *
1091 * @note Allow to define how Logical data from the data register are send/received :
1092 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1093 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1094 * @param LPUARTx LPUART Instance
1095 * @param DataLogic This parameter can be one of the following values:
1096 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1097 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1098 * @retval None
1099 */
1100__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1101{
1102 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1103}
1104
1105/**
1106 * @brief Retrieve Binary data configuration
1107 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1108 * @param LPUARTx LPUART Instance
1109 * @retval Returned value can be one of the following values:
1110 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1111 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1112 */
1113__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1114{
1115 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1116}
1117
1118/**
1119 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1120 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1121 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1122 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1123 * @param LPUARTx LPUART Instance
1124 * @param BitOrder This parameter can be one of the following values:
1125 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1126 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1127 * @retval None
1128 */
1129__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1130{
1131 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1132}
1133
1134/**
1135 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1136 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1137 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1138 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1139 * @param LPUARTx LPUART Instance
1140 * @retval Returned value can be one of the following values:
1141 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1142 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1143 */
1144__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1145{
1146 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1147}
1148
1149/**
1150 * @brief Set Address of the LPUART node.
1151 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1152 * for wake up with address mark detection.
1153 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1154 * (b7-b4 should be set to 0)
1155 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1156 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1157 * for wake up with 7-bit address mark detection.
1158 * The MSB of the character sent by the transmitter should be equal to 1.
1159 * It may also be used for character detection during normal reception,
1160 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1161 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1162 * value and CMF flag is set on match)
1163 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1164 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1165 * @param LPUARTx LPUART Instance
1166 * @param AddressLen This parameter can be one of the following values:
1167 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1168 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1169 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1170 * @retval None
1171 */
1172__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1173{
1174 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1175 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1176}
1177
1178/**
1179 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1180 * @note If 4-bit Address Detection is selected in ADDM7,
1181 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1182 * If 7-bit Address Detection is selected in ADDM7,
1183 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1184 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1185 * @param LPUARTx LPUART Instance
1186 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1187 */
1188__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1189{
1190 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1191}
1192
1193/**
1194 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1195 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1196 * @param LPUARTx LPUART Instance
1197 * @retval Returned value can be one of the following values:
1198 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1199 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1200 */
1201__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1202{
1203 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1204}
1205
1206/**
1207 * @brief Enable RTS HW Flow Control
1208 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1209 * @param LPUARTx LPUART Instance
1210 * @retval None
1211 */
1212__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1213{
1214 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1215}
1216
1217/**
1218 * @brief Disable RTS HW Flow Control
1219 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1220 * @param LPUARTx LPUART Instance
1221 * @retval None
1222 */
1223__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1224{
1225 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1226}
1227
1228/**
1229 * @brief Enable CTS HW Flow Control
1230 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1231 * @param LPUARTx LPUART Instance
1232 * @retval None
1233 */
1234__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1235{
1236 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1237}
1238
1239/**
1240 * @brief Disable CTS HW Flow Control
1241 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1242 * @param LPUARTx LPUART Instance
1243 * @retval None
1244 */
1245__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1246{
1247 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1248}
1249
1250/**
1251 * @brief Configure HW Flow Control mode (both CTS and RTS)
1252 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1253 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1254 * @param LPUARTx LPUART Instance
1255 * @param HardwareFlowControl This parameter can be one of the following values:
1256 * @arg @ref LL_LPUART_HWCONTROL_NONE
1257 * @arg @ref LL_LPUART_HWCONTROL_RTS
1258 * @arg @ref LL_LPUART_HWCONTROL_CTS
1259 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1260 * @retval None
1261 */
1262__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1263{
1264 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1265}
1266
1267/**
1268 * @brief Return HW Flow Control configuration (both CTS and RTS)
1269 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1270 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1271 * @param LPUARTx LPUART Instance
1272 * @retval Returned value can be one of the following values:
1273 * @arg @ref LL_LPUART_HWCONTROL_NONE
1274 * @arg @ref LL_LPUART_HWCONTROL_RTS
1275 * @arg @ref LL_LPUART_HWCONTROL_CTS
1276 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1277 */
1278__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1279{
1280 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1281}
1282
1283/**
1284 * @brief Enable Overrun detection
1285 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1286 * @param LPUARTx LPUART Instance
1287 * @retval None
1288 */
1289__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1290{
1291 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1292}
1293
1294/**
1295 * @brief Disable Overrun detection
1296 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1297 * @param LPUARTx LPUART Instance
1298 * @retval None
1299 */
1300__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1301{
1302 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1303}
1304
1305/**
1306 * @brief Indicate if Overrun detection is enabled
1307 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1308 * @param LPUARTx LPUART Instance
1309 * @retval State of bit (1 or 0).
1310 */
1311__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1312{
1313 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1314}
1315
1316/**
1317 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1318 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1319 * @param LPUARTx LPUART Instance
1320 * @param Type This parameter can be one of the following values:
1321 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1322 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1323 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1324 * @retval None
1325 */
1326__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1327{
1328 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1329}
1330
1331/**
1332 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1333 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1334 * @param LPUARTx LPUART Instance
1335 * @retval Returned value can be one of the following values:
1336 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1337 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1338 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1339 */
1340__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
1341{
1342 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1343}
1344
1345/**
1346 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1347 *
1348 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1349 * according to used Peripheral Clock and expected Baud Rate values
1350 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1351 * (Baud rate value != 0).
1352 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1353 * a care should be taken when generating high baud rates using high PeriphClk
1354 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1355 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1356 * @param LPUARTx LPUART Instance
1357 * @param PeriphClk Peripheral Clock
1358 * @param PrescalerValue This parameter can be one of the following values:
1359 * @arg @ref LL_LPUART_PRESCALER_DIV1
1360 * @arg @ref LL_LPUART_PRESCALER_DIV2
1361 * @arg @ref LL_LPUART_PRESCALER_DIV4
1362 * @arg @ref LL_LPUART_PRESCALER_DIV6
1363 * @arg @ref LL_LPUART_PRESCALER_DIV8
1364 * @arg @ref LL_LPUART_PRESCALER_DIV10
1365 * @arg @ref LL_LPUART_PRESCALER_DIV12
1366 * @arg @ref LL_LPUART_PRESCALER_DIV16
1367 * @arg @ref LL_LPUART_PRESCALER_DIV32
1368 * @arg @ref LL_LPUART_PRESCALER_DIV64
1369 * @arg @ref LL_LPUART_PRESCALER_DIV128
1370 * @arg @ref LL_LPUART_PRESCALER_DIV256
1371 * @param BaudRate Baud Rate
1372 * @retval None
1373 */
1374__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1375 uint32_t BaudRate)
1376{
1377 if (BaudRate != 0U)
1378 {
1379 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1380 }
1381}
1382
1383/**
1384 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1385 * (full BRR content), and to used Peripheral Clock values
1386 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1387 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1388 * @param LPUARTx LPUART Instance
1389 * @param PeriphClk Peripheral Clock
1390 * @param PrescalerValue This parameter can be one of the following values:
1391 * @arg @ref LL_LPUART_PRESCALER_DIV1
1392 * @arg @ref LL_LPUART_PRESCALER_DIV2
1393 * @arg @ref LL_LPUART_PRESCALER_DIV4
1394 * @arg @ref LL_LPUART_PRESCALER_DIV6
1395 * @arg @ref LL_LPUART_PRESCALER_DIV8
1396 * @arg @ref LL_LPUART_PRESCALER_DIV10
1397 * @arg @ref LL_LPUART_PRESCALER_DIV12
1398 * @arg @ref LL_LPUART_PRESCALER_DIV16
1399 * @arg @ref LL_LPUART_PRESCALER_DIV32
1400 * @arg @ref LL_LPUART_PRESCALER_DIV64
1401 * @arg @ref LL_LPUART_PRESCALER_DIV128
1402 * @arg @ref LL_LPUART_PRESCALER_DIV256
1403 * @retval Baud Rate
1404 */
1405__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1406 uint32_t PrescalerValue)
1407{
1408 uint32_t lpuartdiv;
1409 uint32_t brrresult;
1410 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1411
1412 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1413
1414 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1415 {
1416 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1417 }
1418 else
1419 {
1420 brrresult = 0x0UL;
1421 }
1422
1423 return (brrresult);
1424}
1425
1426/**
1427 * @}
1428 */
1429
1430/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1431 * @{
1432 */
1433
1434/**
1435 * @brief Enable Single Wire Half-Duplex mode
1436 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1437 * @param LPUARTx LPUART Instance
1438 * @retval None
1439 */
1440__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1441{
1442 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1443}
1444
1445/**
1446 * @brief Disable Single Wire Half-Duplex mode
1447 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1448 * @param LPUARTx LPUART Instance
1449 * @retval None
1450 */
1451__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1452{
1453 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1454}
1455
1456/**
1457 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1458 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1459 * @param LPUARTx LPUART Instance
1460 * @retval State of bit (1 or 0).
1461 */
1462__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1463{
1464 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1465}
1466
1467/**
1468 * @}
1469 */
1470
1471/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1472 * @{
1473 */
1474
1475/**
1476 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1477 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1478 * @param LPUARTx LPUART Instance
1479 * @param Time Value between Min_Data=0 and Max_Data=31
1480 * @retval None
1481 */
1482__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1483{
1484 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1485}
1486
1487/**
1488 * @brief Return DEDT (Driver Enable De-Assertion Time)
1489 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1490 * @param LPUARTx LPUART Instance
1491 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1492 */
1493__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1494{
1495 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1496}
1497
1498/**
1499 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1500 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1501 * @param LPUARTx LPUART Instance
1502 * @param Time Value between Min_Data=0 and Max_Data=31
1503 * @retval None
1504 */
1505__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1506{
1507 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1508}
1509
1510/**
1511 * @brief Return DEAT (Driver Enable Assertion Time)
1512 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1513 * @param LPUARTx LPUART Instance
1514 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1515 */
1516__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1517{
1518 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1519}
1520
1521/**
1522 * @brief Enable Driver Enable (DE) Mode
1523 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1524 * @param LPUARTx LPUART Instance
1525 * @retval None
1526 */
1527__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1528{
1529 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1530}
1531
1532/**
1533 * @brief Disable Driver Enable (DE) Mode
1534 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1535 * @param LPUARTx LPUART Instance
1536 * @retval None
1537 */
1538__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1539{
1540 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1541}
1542
1543/**
1544 * @brief Indicate if Driver Enable (DE) Mode is enabled
1545 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1546 * @param LPUARTx LPUART Instance
1547 * @retval State of bit (1 or 0).
1548 */
1549__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1550{
1551 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1552}
1553
1554/**
1555 * @brief Select Driver Enable Polarity
1556 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1557 * @param LPUARTx LPUART Instance
1558 * @param Polarity This parameter can be one of the following values:
1559 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1560 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1561 * @retval None
1562 */
1563__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1564{
1565 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1566}
1567
1568/**
1569 * @brief Return Driver Enable Polarity
1570 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1571 * @param LPUARTx LPUART Instance
1572 * @retval Returned value can be one of the following values:
1573 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1574 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1575 */
1576__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1577{
1578 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1579}
1580
1581/**
1582 * @}
1583 */
1584
1585/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1586 * @{
1587 */
1588
1589/**
1590 * @brief Check if the LPUART Parity Error Flag is set or not
1591 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1592 * @param LPUARTx LPUART Instance
1593 * @retval State of bit (1 or 0).
1594 */
1595__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1596{
1597 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1598}
1599
1600/**
1601 * @brief Check if the LPUART Framing Error Flag is set or not
1602 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1603 * @param LPUARTx LPUART Instance
1604 * @retval State of bit (1 or 0).
1605 */
1606__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1607{
1608 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1609}
1610
1611/**
1612 * @brief Check if the LPUART Noise error detected Flag is set or not
1613 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1614 * @param LPUARTx LPUART Instance
1615 * @retval State of bit (1 or 0).
1616 */
1617__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1618{
1619 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1620}
1621
1622/**
1623 * @brief Check if the LPUART OverRun Error Flag is set or not
1624 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1625 * @param LPUARTx LPUART Instance
1626 * @retval State of bit (1 or 0).
1627 */
1628__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1629{
1630 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1631}
1632
1633/**
1634 * @brief Check if the LPUART IDLE line detected Flag is set or not
1635 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1636 * @param LPUARTx LPUART Instance
1637 * @retval State of bit (1 or 0).
1638 */
1639__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1640{
1641 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1642}
1643
1644#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
1645
1646/**
1647 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1648 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1649 * @param LPUARTx LPUART Instance
1650 * @retval State of bit (1 or 0).
1651 */
1652__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1653{
1654 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1655}
1656
1657/**
1658 * @brief Check if the LPUART Transmission Complete Flag is set or not
1659 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1660 * @param LPUARTx LPUART Instance
1661 * @retval State of bit (1 or 0).
1662 */
1663__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1664{
1665 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1666}
1667
1668#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
1669
1670/**
1671 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1672 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1673 * @param LPUARTx LPUART Instance
1674 * @retval State of bit (1 or 0).
1675 */
1676__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1677{
1678 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1679}
1680
1681/**
1682 * @brief Check if the LPUART CTS interrupt Flag is set or not
1683 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1684 * @param LPUARTx LPUART Instance
1685 * @retval State of bit (1 or 0).
1686 */
1687__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1688{
1689 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1690}
1691
1692/**
1693 * @brief Check if the LPUART CTS Flag is set or not
1694 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1695 * @param LPUARTx LPUART Instance
1696 * @retval State of bit (1 or 0).
1697 */
1698__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1699{
1700 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1701}
1702
1703/**
1704 * @brief Check if the LPUART Busy Flag is set or not
1705 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1706 * @param LPUARTx LPUART Instance
1707 * @retval State of bit (1 or 0).
1708 */
1709__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1710{
1711 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1712}
1713
1714/**
1715 * @brief Check if the LPUART Character Match Flag is set or not
1716 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1717 * @param LPUARTx LPUART Instance
1718 * @retval State of bit (1 or 0).
1719 */
1720__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1721{
1722 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1723}
1724
1725/**
1726 * @brief Check if the LPUART Send Break Flag is set or not
1727 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1728 * @param LPUARTx LPUART Instance
1729 * @retval State of bit (1 or 0).
1730 */
1731__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1732{
1733 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1734}
1735
1736/**
1737 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1738 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1739 * @param LPUARTx LPUART Instance
1740 * @retval State of bit (1 or 0).
1741 */
1742__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1743{
1744 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1745}
1746
1747/**
1748 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1749 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1750 * @param LPUARTx LPUART Instance
1751 * @retval State of bit (1 or 0).
1752 */
1753__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
1754{
1755 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1756}
1757
1758/**
1759 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1760 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1761 * @param LPUARTx LPUART Instance
1762 * @retval State of bit (1 or 0).
1763 */
1764__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1765{
1766 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1767}
1768
1769/**
1770 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1771 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1772 * @param LPUARTx LPUART Instance
1773 * @retval State of bit (1 or 0).
1774 */
1775__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1776{
1777 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1778}
1779
1780/**
1781 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1782 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1783 * @param LPUARTx LPUART Instance
1784 * @retval State of bit (1 or 0).
1785 */
1786__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1787{
1788 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1789}
1790
1791/**
1792 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1793 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1794 * @param LPUARTx LPUART Instance
1795 * @retval State of bit (1 or 0).
1796 */
1797__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1798{
1799 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1800}
1801
1802/**
1803 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1804 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1805 * @param LPUARTx LPUART Instance
1806 * @retval State of bit (1 or 0).
1807 */
1808__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1809{
1810 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1811}
1812
1813/**
1814 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1815 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1816 * @param LPUARTx LPUART Instance
1817 * @retval State of bit (1 or 0).
1818 */
1819__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1820{
1821 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1822}
1823
1824/**
1825 * @brief Clear Parity Error Flag
1826 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1827 * @param LPUARTx LPUART Instance
1828 * @retval None
1829 */
1830__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1831{
1832 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1833}
1834
1835/**
1836 * @brief Clear Framing Error Flag
1837 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1838 * @param LPUARTx LPUART Instance
1839 * @retval None
1840 */
1841__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1842{
1843 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1844}
1845
1846/**
1847 * @brief Clear Noise detected Flag
1848 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1849 * @param LPUARTx LPUART Instance
1850 * @retval None
1851 */
1852__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1853{
1854 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1855}
1856
1857/**
1858 * @brief Clear OverRun Error Flag
1859 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1860 * @param LPUARTx LPUART Instance
1861 * @retval None
1862 */
1863__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1864{
1865 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1866}
1867
1868/**
1869 * @brief Clear IDLE line detected Flag
1870 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1871 * @param LPUARTx LPUART Instance
1872 * @retval None
1873 */
1874__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1875{
1876 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1877}
1878
1879/**
1880 * @brief Clear Transmission Complete Flag
1881 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1882 * @param LPUARTx LPUART Instance
1883 * @retval None
1884 */
1885__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1886{
1887 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1888}
1889
1890/**
1891 * @brief Clear CTS Interrupt Flag
1892 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1893 * @param LPUARTx LPUART Instance
1894 * @retval None
1895 */
1896__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1897{
1898 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1899}
1900
1901/**
1902 * @brief Clear Character Match Flag
1903 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1904 * @param LPUARTx LPUART Instance
1905 * @retval None
1906 */
1907__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1908{
1909 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1910}
1911
1912/**
1913 * @brief Clear Wake Up from stop mode Flag
1914 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1915 * @param LPUARTx LPUART Instance
1916 * @retval None
1917 */
1918__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1919{
1920 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1921}
1922
1923/**
1924 * @}
1925 */
1926
1927/** @defgroup LPUART_LL_EF_IT_Management IT_Management
1928 * @{
1929 */
1930
1931/**
1932 * @brief Enable IDLE Interrupt
1933 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1934 * @param LPUARTx LPUART Instance
1935 * @retval None
1936 */
1937__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1938{
1939 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1940}
1941
1942#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
1943
1944/**
1945 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1946 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1947 * @param LPUARTx LPUART Instance
1948 * @retval None
1949 */
1950__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1951{
1952 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1953}
1954
1955/**
1956 * @brief Enable Transmission Complete Interrupt
1957 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1958 * @param LPUARTx LPUART Instance
1959 * @retval None
1960 */
1961__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1962{
1963 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1964}
1965
1966#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
1967
1968/**
1969 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1970 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1971 * @param LPUARTx LPUART Instance
1972 * @retval None
1973 */
1974__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1975{
1976 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1977}
1978
1979/**
1980 * @brief Enable Parity Error Interrupt
1981 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1982 * @param LPUARTx LPUART Instance
1983 * @retval None
1984 */
1985__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1986{
1987 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1988}
1989
1990/**
1991 * @brief Enable Character Match Interrupt
1992 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1993 * @param LPUARTx LPUART Instance
1994 * @retval None
1995 */
1996__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1997{
1998 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1999}
2000
2001/**
2002 * @brief Enable TX FIFO Empty Interrupt
2003 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
2004 * @param LPUARTx LPUART Instance
2005 * @retval None
2006 */
2007__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2008{
2009 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2010}
2011
2012/**
2013 * @brief Enable RX FIFO Full Interrupt
2014 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
2015 * @param LPUARTx LPUART Instance
2016 * @retval None
2017 */
2018__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2019{
2020 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2021}
2022
2023/**
2024 * @brief Enable Error Interrupt
2025 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2026 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2027 * - 0: Interrupt is inhibited
2028 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2029 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2030 * @param LPUARTx LPUART Instance
2031 * @retval None
2032 */
2033__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2034{
2035 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2036}
2037
2038/**
2039 * @brief Enable CTS Interrupt
2040 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2041 * @param LPUARTx LPUART Instance
2042 * @retval None
2043 */
2044__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2045{
2046 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2047}
2048
2049/**
2050 * @brief Enable Wake Up from Stop Mode Interrupt
2051 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2052 * @param LPUARTx LPUART Instance
2053 * @retval None
2054 */
2055__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2056{
2057 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2058}
2059
2060/**
2061 * @brief Enable TX FIFO Threshold Interrupt
2062 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2063 * @param LPUARTx LPUART Instance
2064 * @retval None
2065 */
2066__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2067{
2068 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2069}
2070
2071/**
2072 * @brief Enable RX FIFO Threshold Interrupt
2073 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2074 * @param LPUARTx LPUART Instance
2075 * @retval None
2076 */
2077__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2078{
2079 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2080}
2081
2082/**
2083 * @brief Disable IDLE Interrupt
2084 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2085 * @param LPUARTx LPUART Instance
2086 * @retval None
2087 */
2088__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2089{
2090 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2091}
2092
2093#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2094
2095/**
2096 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2097 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2098 * @param LPUARTx LPUART Instance
2099 * @retval None
2100 */
2101__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2102{
2103 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2104}
2105
2106/**
2107 * @brief Disable Transmission Complete Interrupt
2108 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2109 * @param LPUARTx LPUART Instance
2110 * @retval None
2111 */
2112__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2113{
2114 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2115}
2116
2117#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
2118
2119/**
2120 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2121 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2122 * @param LPUARTx LPUART Instance
2123 * @retval None
2124 */
2125__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2126{
2127 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2128}
2129
2130/**
2131 * @brief Disable Parity Error Interrupt
2132 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2133 * @param LPUARTx LPUART Instance
2134 * @retval None
2135 */
2136__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2137{
2138 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2139}
2140
2141/**
2142 * @brief Disable Character Match Interrupt
2143 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2144 * @param LPUARTx LPUART Instance
2145 * @retval None
2146 */
2147__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2148{
2149 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2150}
2151
2152/**
2153 * @brief Disable TX FIFO Empty Interrupt
2154 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2155 * @param LPUARTx LPUART Instance
2156 * @retval None
2157 */
2158__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2159{
2160 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2161}
2162
2163/**
2164 * @brief Disable RX FIFO Full Interrupt
2165 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2166 * @param LPUARTx LPUART Instance
2167 * @retval None
2168 */
2169__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2170{
2171 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2172}
2173
2174/**
2175 * @brief Disable Error Interrupt
2176 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2177 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2178 * - 0: Interrupt is inhibited
2179 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2180 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2181 * @param LPUARTx LPUART Instance
2182 * @retval None
2183 */
2184__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2185{
2186 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2187}
2188
2189/**
2190 * @brief Disable CTS Interrupt
2191 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2192 * @param LPUARTx LPUART Instance
2193 * @retval None
2194 */
2195__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2196{
2197 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2198}
2199
2200/**
2201 * @brief Disable Wake Up from Stop Mode Interrupt
2202 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2203 * @param LPUARTx LPUART Instance
2204 * @retval None
2205 */
2206__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2207{
2208 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2209}
2210
2211/**
2212 * @brief Disable TX FIFO Threshold Interrupt
2213 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2214 * @param LPUARTx LPUART Instance
2215 * @retval None
2216 */
2217__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2218{
2219 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2220}
2221
2222/**
2223 * @brief Disable RX FIFO Threshold Interrupt
2224 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2225 * @param LPUARTx LPUART Instance
2226 * @retval None
2227 */
2228__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2229{
2230 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2231}
2232
2233/**
2234 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2235 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2236 * @param LPUARTx LPUART Instance
2237 * @retval State of bit (1 or 0).
2238 */
2239__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2240{
2241 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2242}
2243
2244#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2245
2246/**
2247 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2248 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2249 * @param LPUARTx LPUART Instance
2250 * @retval State of bit (1 or 0).
2251 */
2252__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2253{
2254 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2255}
2256
2257/**
2258 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2259 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2260 * @param LPUARTx LPUART Instance
2261 * @retval State of bit (1 or 0).
2262 */
2263__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2264{
2265 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2266}
2267
2268#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
2269
2270/**
2271 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2272 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2273 * @param LPUARTx LPUART Instance
2274 * @retval State of bit (1 or 0).
2275 */
2276__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2277{
2278 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2279}
2280
2281/**
2282 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2283 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2284 * @param LPUARTx LPUART Instance
2285 * @retval State of bit (1 or 0).
2286 */
2287__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2288{
2289 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2290}
2291
2292/**
2293 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2294 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2295 * @param LPUARTx LPUART Instance
2296 * @retval State of bit (1 or 0).
2297 */
2298__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2299{
2300 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2301}
2302
2303/**
2304 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2305 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2306 * @param LPUARTx LPUART Instance
2307 * @retval State of bit (1 or 0).
2308 */
2309__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2310{
2311 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2312}
2313
2314/**
2315 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2316 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2317 * @param LPUARTx LPUART Instance
2318 * @retval State of bit (1 or 0).
2319 */
2320__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2321{
2322 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2323}
2324
2325/**
2326 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2327 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2328 * @param LPUARTx LPUART Instance
2329 * @retval State of bit (1 or 0).
2330 */
2331__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2332{
2333 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2334}
2335
2336/**
2337 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2338 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2339 * @param LPUARTx LPUART Instance
2340 * @retval State of bit (1 or 0).
2341 */
2342__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2343{
2344 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2345}
2346
2347/**
2348 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2349 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2350 * @param LPUARTx LPUART Instance
2351 * @retval State of bit (1 or 0).
2352 */
2353__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
2354{
2355 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2356}
2357
2358/**
2359 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2360 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2361 * @param LPUARTx LPUART Instance
2362 * @retval State of bit (1 or 0).
2363 */
2364__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2365{
2366 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2367}
2368
2369/**
2370 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2371 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2372 * @param LPUARTx LPUART Instance
2373 * @retval State of bit (1 or 0).
2374 */
2375__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2376{
2377 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2378}
2379
2380/**
2381 * @}
2382 */
2383
2384/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2385 * @{
2386 */
2387
2388/**
2389 * @brief Enable DMA Mode for reception
2390 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2391 * @param LPUARTx LPUART Instance
2392 * @retval None
2393 */
2394__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2395{
2396 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2397}
2398
2399/**
2400 * @brief Disable DMA Mode for reception
2401 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2402 * @param LPUARTx LPUART Instance
2403 * @retval None
2404 */
2405__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2406{
2407 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2408}
2409
2410/**
2411 * @brief Check if DMA Mode is enabled for reception
2412 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2413 * @param LPUARTx LPUART Instance
2414 * @retval State of bit (1 or 0).
2415 */
2416__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2417{
2418 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2419}
2420
2421/**
2422 * @brief Enable DMA Mode for transmission
2423 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2424 * @param LPUARTx LPUART Instance
2425 * @retval None
2426 */
2427__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2428{
2429 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2430}
2431
2432/**
2433 * @brief Disable DMA Mode for transmission
2434 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2435 * @param LPUARTx LPUART Instance
2436 * @retval None
2437 */
2438__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2439{
2440 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2441}
2442
2443/**
2444 * @brief Check if DMA Mode is enabled for transmission
2445 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2446 * @param LPUARTx LPUART Instance
2447 * @retval State of bit (1 or 0).
2448 */
2449__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2450{
2451 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2452}
2453
2454/**
2455 * @brief Enable DMA Disabling on Reception Error
2456 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2457 * @param LPUARTx LPUART Instance
2458 * @retval None
2459 */
2460__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2461{
2462 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2463}
2464
2465/**
2466 * @brief Disable DMA Disabling on Reception Error
2467 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2468 * @param LPUARTx LPUART Instance
2469 * @retval None
2470 */
2471__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2472{
2473 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2474}
2475
2476/**
2477 * @brief Indicate if DMA Disabling on Reception Error is disabled
2478 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2479 * @param LPUARTx LPUART Instance
2480 * @retval State of bit (1 or 0).
2481 */
2482__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2483{
2484 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2485}
2486
2487/**
2488 * @brief Get the LPUART data register address used for DMA transfer
2489 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2490 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2491 * @param LPUARTx LPUART Instance
2492 * @param Direction This parameter can be one of the following values:
2493 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2494 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2495 * @retval Address of data register
2496 */
2497__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2498{
2499 uint32_t data_reg_addr;
2500
2501 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2502 {
2503 /* return address of TDR register */
2504 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2505 }
2506 else
2507 {
2508 /* return address of RDR register */
2509 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2510 }
2511
2512 return data_reg_addr;
2513}
2514
2515/**
2516 * @}
2517 */
2518
2519/** @defgroup LPUART_LL_EF_Data_Management Data_Management
2520 * @{
2521 */
2522
2523/**
2524 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2525 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2526 * @param LPUARTx LPUART Instance
2527 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2528 */
2529__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2530{
2531 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2532}
2533
2534/**
2535 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2536 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2537 * @param LPUARTx LPUART Instance
2538 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2539 */
2540__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2541{
2542 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2543}
2544
2545/**
2546 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2547 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2548 * @param LPUARTx LPUART Instance
2549 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2550 * @retval None
2551 */
2552__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2553{
2554 LPUARTx->TDR = Value;
2555}
2556
2557/**
2558 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2559 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2560 * @param LPUARTx LPUART Instance
2561 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2562 * @retval None
2563 */
2564__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2565{
2566 LPUARTx->TDR = Value & 0x1FFUL;
2567}
2568
2569/**
2570 * @}
2571 */
2572
2573/** @defgroup LPUART_LL_EF_Execution Execution
2574 * @{
2575 */
2576
2577/**
2578 * @brief Request Break sending
2579 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2580 * @param LPUARTx LPUART Instance
2581 * @retval None
2582 */
2583__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2584{
2585 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2586}
2587
2588/**
2589 * @brief Put LPUART in mute mode and set the RWU flag
2590 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2591 * @param LPUARTx LPUART Instance
2592 * @retval None
2593 */
2594__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2595{
2596 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2597}
2598
2599/**
2600 * @brief Request a Receive Data and FIFO flush
2601 * @note Allows to discard the received data without reading them, and avoid an overrun
2602 * condition.
2603 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2604 * @param LPUARTx LPUART Instance
2605 * @retval None
2606 */
2607__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2608{
2609 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2610}
2611
2612/**
2613 * @brief Request a Transmit data FIFO flush
2614 * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
2615 * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
2616 * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
2617 * FIFO mode feature is supported by the USARTx instance.
2618 * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
2619 * @param LPUARTx LPUART Instance
2620 * @retval None
2621 */
2622__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
2623{
2624 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
2625}
2626
2627/**
2628 * @}
2629 */
2630
2631#if defined(USE_FULL_LL_DRIVER)
2632/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2633 * @{
2634 */
2635ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2636ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2637void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2638/**
2639 * @}
2640 */
2641#endif /* USE_FULL_LL_DRIVER */
2642
2643/**
2644 * @}
2645 */
2646
2647/**
2648 * @}
2649 */
2650
2651#endif /* LPUART1 */
2652
2653/**
2654 * @}
2655 */
2656
2657#ifdef __cplusplus
2658}
2659#endif
2660
2661#endif /* STM32H7xx_LL_LPUART_H */
2662
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
ATOMIC_CLEAR_BIT
#define ATOMIC_CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:234
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
ATOMIC_SET_BIT
#define ATOMIC_SET_BIT(REG, BIT)
Definition stm32h7xx.h:225
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
ATOMIC_MODIFY_REG
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
Definition stm32h7xx.h:243
ErrorStatus
ErrorStatus
Definition stm32h7xx.h:194
USART_ICR_WUCF
#define USART_ICR_WUCF
Wake Up from stop mode Clear Flag.
Definition stm32h723xx.h:21475
USART_ISR_NE
#define USART_ISR_NE
Noise detected Flag.
Definition stm32h723xx.h:21353
USART_ISR_RWU
#define USART_ISR_RWU
Receive Wake Up from mute mode Flag.
Definition stm32h723xx.h:21404
USART_ISR_TXE_TXFNF
#define USART_ISR_TXE_TXFNF
Transmit Data Register Empty or TX FIFO Not Full Flag.
Definition stm32h723xx.h:21368
USART_ISR_TXFT
#define USART_ISR_TXFT
TXFIFO threshold Flag.
Definition stm32h723xx.h:21428
USART_CR1_UESM
#define USART_CR1_UESM
USART Enable in STOP Mode.
Definition stm32h723xx.h:21067
USART_CR3_DEP
#define USART_CR3_DEP
Driver Enable Polarity Selection.
Definition stm32h723xx.h:21266
USART_PRESC_PRESCALER
#define USART_PRESC_PRESCALER
PRESCALER[3:0] bits (Clock prescaler).
Definition stm32h723xx.h:21490
USART_CR1_PEIE
#define USART_CR1_PEIE
PE Interrupt Enable.
Definition stm32h723xx.h:21088
USART_ISR_FE
#define USART_ISR_FE
Framing Error.
Definition stm32h723xx.h:21350
USART_RQR_MMRQ
#define USART_RQR_MMRQ
Mute Mode Request.
Definition stm32h723xx.h:21336
USART_CR1_UE
#define USART_CR1_UE
USART Enable.
Definition stm32h723xx.h:21064
USART_CR2_ADD_Pos
#define USART_CR2_ADD_Pos
Definition stm32h723xx.h:21214
USART_RQR_SBKRQ
#define USART_RQR_SBKRQ
Send Break Request.
Definition stm32h723xx.h:21333
USART_CR2_ADDM7
#define USART_CR2_ADDM7
7-bit or 4-bit Address Detection
Definition stm32h723xx.h:21161
USART_CR1_PS
#define USART_CR1_PS
Parity Selection.
Definition stm32h723xx.h:21091
USART_CR3_OVRDIS
#define USART_CR3_OVRDIS
Overrun Disable.
Definition stm32h723xx.h:21257
USART_ICR_ORECF
#define USART_ICR_ORECF
OverRun Error Clear Flag.
Definition stm32h723xx.h:21442
USART_CR2_ADD
#define USART_CR2_ADD
Address of the USART node.
Definition stm32h723xx.h:21216
USART_CR3_TXFTCFG
#define USART_CR3_TXFTCFG
TXFIFO [2:0] threshold configuration.
Definition stm32h723xx.h:21298
USART_ICR_PECF
#define USART_ICR_PECF
Parity Error Clear Flag.
Definition stm32h723xx.h:21433
USART_CR3_RXFTIE
#define USART_CR3_RXFTIE
RXFIFO threshold interrupt enable.
Definition stm32h723xx.h:21295
USART_CR1_MME
#define USART_CR1_MME
Mute Mode Enable.
Definition stm32h723xx.h:21106
USART_CR2_SWAP
#define USART_CR2_SWAP
SWAP TX/RX pins.
Definition stm32h723xx.h:21190
USART_CR1_IDLEIE
#define USART_CR1_IDLEIE
IDLE Interrupt Enable.
Definition stm32h723xx.h:21076
USART_ICR_CMCF
#define USART_ICR_CMCF
Character Match Clear Flag.
Definition stm32h723xx.h:21472
USART_CR3_TXFTIE
#define USART_CR3_TXFTIE
TXFIFO threshold interrupt enable.
Definition stm32h723xx.h:21283
USART_CR3_DMAT
#define USART_CR3_DMAT
DMA Enable Transmitter.
Definition stm32h723xx.h:21242
USART_CR1_PCE
#define USART_CR1_PCE
Parity Control Enable.
Definition stm32h723xx.h:21094
USART_CR3_CTSIE
#define USART_CR3_CTSIE
CTS Interrupt Enable.
Definition stm32h723xx.h:21251
USART_CR3_RXFTCFG_Pos
#define USART_CR3_RXFTCFG_Pos
Definition stm32h723xx.h:21287
USART_CR1_DEAT
#define USART_CR1_DEAT
DEAT[4:0] bits (Driver Enable Assertion Time).
Definition stm32h723xx.h:21123
USART_CR1_RXFFIE
#define USART_CR1_RXFFIE
RXFIFO Full interrupt enable.
Definition stm32h723xx.h:21146
USART_CR2_MSBFIRST
#define USART_CR2_MSBFIRST
Most Significant Bit First.
Definition stm32h723xx.h:21202
USART_ISR_SBKF
#define USART_ISR_SBKF
Send Break Flag.
Definition stm32h723xx.h:21401
USART_CR1_DEAT_Pos
#define USART_CR1_DEAT_Pos
Definition stm32h723xx.h:21121
USART_CR3_WUS
#define USART_CR3_WUS
WUS[1:0] bits (Wake UP Interrupt Flag Selection).
Definition stm32h723xx.h:21275
USART_RQR_RXFRQ
#define USART_RQR_RXFRQ
Receive Data flush Request.
Definition stm32h723xx.h:21339
USART_CR3_RTSE
#define USART_CR3_RTSE
RTS Enable.
Definition stm32h723xx.h:21245
USART_CR3_WUFIE
#define USART_CR3_WUFIE
Wake Up Interrupt Enable.
Definition stm32h723xx.h:21280
USART_ISR_CMF
#define USART_ISR_CMF
Character Match Flag.
Definition stm32h723xx.h:21398
USART_CR1_RXNEIE_RXFNEIE
#define USART_CR1_RXNEIE_RXFNEIE
RXNE and RX FIFO Not Empty Interrupt Enable.
Definition stm32h723xx.h:21079
USART_ICR_FECF
#define USART_ICR_FECF
Framing Error Clear Flag.
Definition stm32h723xx.h:21436
USART_ISR_CTS
#define USART_ISR_CTS
CTS flag.
Definition stm32h723xx.h:21377
USART_ICR_CTSCF
#define USART_ICR_CTSCF
CTS Interrupt Clear Flag.
Definition stm32h723xx.h:21460
USART_CR2_DATAINV
#define USART_CR2_DATAINV
Binary data inversion.
Definition stm32h723xx.h:21199
USART_CR1_TXEIE_TXFNFIE
#define USART_CR1_TXEIE_TXFNFIE
TXE and TX FIFO Not Full Interrupt Enable.
Definition stm32h723xx.h:21085
USART_CR1_M
#define USART_CR1_M
Word length.
Definition stm32h723xx.h:21100
USART_ICR_IDLECF
#define USART_ICR_IDLECF
IDLE line detected Clear Flag.
Definition stm32h723xx.h:21445
USART_ISR_ORE
#define USART_ISR_ORE
OverRun Error.
Definition stm32h723xx.h:21356
USART_ISR_CTSIF
#define USART_ISR_CTSIF
CTS interrupt flag.
Definition stm32h723xx.h:21374
USART_ISR_PE
#define USART_ISR_PE
Parity Error.
Definition stm32h723xx.h:21347
USART_CR3_CTSE
#define USART_CR3_CTSE
CTS Enable.
Definition stm32h723xx.h:21248
USART_CR1_TCIE
#define USART_CR1_TCIE
Transmission Complete Interrupt Enable.
Definition stm32h723xx.h:21082
USART_RQR_TXFRQ
#define USART_RQR_TXFRQ
Transmit data flush Request.
Definition stm32h723xx.h:21342
USART_ISR_TC
#define USART_ISR_TC
Transmission Complete.
Definition stm32h723xx.h:21365
USART_ISR_REACK
#define USART_ISR_REACK
Receive Enable Acknowledge Flag.
Definition stm32h723xx.h:21413
USART_ISR_RXFF
#define USART_ISR_RXFF
RXFIFO Full Flag.
Definition stm32h723xx.h:21419
USART_CR1_CMIE
#define USART_CR1_CMIE
Character match interrupt enable.
Definition stm32h723xx.h:21109
USART_CR3_EIE
#define USART_CR3_EIE
Error Interrupt Enable.
Definition stm32h723xx.h:21221
USART_CR3_TXFTCFG_Pos
#define USART_CR3_TXFTCFG_Pos
Definition stm32h723xx.h:21296
USART_CR1_DEDT
#define USART_CR1_DEDT
DEDT[4:0] bits (Driver Enable Deassertion Time).
Definition stm32h723xx.h:21115
USART_CR1_TXFEIE
#define USART_CR1_TXFEIE
TXFIFO empty interrupt enable.
Definition stm32h723xx.h:21143
USART_CR3_RXFTCFG
#define USART_CR3_RXFTCFG
RXFTCFG [2:0]Receive FIFO threshold configuration.
Definition stm32h723xx.h:21289
USART_ISR_RXNE_RXFNE
#define USART_ISR_RXNE_RXFNE
Read Data Register or RX FIFO Not Empty.
Definition stm32h723xx.h:21362
USART_CR3_HDSEL
#define USART_CR3_HDSEL
Half-Duplex Selection.
Definition stm32h723xx.h:21230
USART_ICR_NECF
#define USART_ICR_NECF
Noise detected Clear Flag.
Definition stm32h723xx.h:21439
USART_CR3_DEM
#define USART_CR3_DEM
Driver Enable Mode.
Definition stm32h723xx.h:21263
USART_ISR_IDLE
#define USART_ISR_IDLE
IDLE line detected.
Definition stm32h723xx.h:21359
USART_ICR_TCCF
#define USART_ICR_TCCF
Transmission Complete Clear Flag.
Definition stm32h723xx.h:21451
USART_CR1_WAKE
#define USART_CR1_WAKE
Receiver Wakeup method.
Definition stm32h723xx.h:21097
USART_ISR_WUF
#define USART_ISR_WUF
Wake Up from stop mode Flag.
Definition stm32h723xx.h:21407
USART_CR1_RE
#define USART_CR1_RE
Receiver Enable.
Definition stm32h723xx.h:21070
USART_CR2_TXINV
#define USART_CR2_TXINV
TX pin active level inversion.
Definition stm32h723xx.h:21196
USART_CR1_TE
#define USART_CR1_TE
Transmitter Enable.
Definition stm32h723xx.h:21073
USART_CR1_DEDT_Pos
#define USART_CR1_DEDT_Pos
Definition stm32h723xx.h:21113
USART_CR3_DDRE
#define USART_CR3_DDRE
DMA Disable on Reception Error.
Definition stm32h723xx.h:21260
USART_ISR_RXFT
#define USART_ISR_RXFT
RXFIFO threshold Flag.
Definition stm32h723xx.h:21425
USART_RDR_RDR
#define USART_RDR_RDR
RDR[8:0] bits (Receive Data value).
Definition stm32h723xx.h:21480
USART_ISR_TEACK
#define USART_ISR_TEACK
Transmit Enable Acknowledge Flag.
Definition stm32h723xx.h:21410
USART_ISR_TXFE
#define USART_ISR_TXFE
TXFIFO Empty.
Definition stm32h723xx.h:21416
USART_CR2_STOP
#define USART_CR2_STOP
STOP[1:0] bits (STOP bits).
Definition stm32h723xx.h:21182
USART_CR1_FIFOEN
#define USART_CR1_FIFOEN
FIFO mode enable.
Definition stm32h723xx.h:21140
USART_ISR_BUSY
#define USART_ISR_BUSY
Busy Flag.
Definition stm32h723xx.h:21395
USART_CR3_DMAR
#define USART_CR3_DMAR
DMA Enable Receiver.
Definition stm32h723xx.h:21239
USART_CR2_RXINV
#define USART_CR2_RXINV
RX pin active level inversion.
Definition stm32h723xx.h:21193
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32h723xx.h:1596
USART_TypeDef::TDR
__IO uint32_t TDR
USART Transmit Data register, Address offset: 0x28.
Definition stm32h723xx.h:1607
USART_TypeDef::CR1
__IO uint32_t CR1
USART Control register 1, Address offset: 0x00.
Definition stm32h723xx.h:1597
USART_TypeDef::BRR
__IO uint32_t BRR
USART Baud rate register, Address offset: 0x0C.
Definition stm32h723xx.h:1600
USART_TypeDef::ISR
__IO uint32_t ISR
USART Interrupt and status register, Address offset: 0x1C.
Definition stm32h723xx.h:1604
USART_TypeDef::RDR
__IO uint32_t RDR
USART Receive Data register, Address offset: 0x24.
Definition stm32h723xx.h:1606
USART_TypeDef::CR2
__IO uint32_t CR2
USART Control register 2, Address offset: 0x04.
Definition stm32h723xx.h:1598
USART_TypeDef::ICR
__IO uint32_t ICR
USART Interrupt flag Clear register, Address offset: 0x20.
Definition stm32h723xx.h:1605
USART_TypeDef::PRESC
__IO uint32_t PRESC
USART clock Prescaler register, Address offset: 0x2C.
Definition stm32h723xx.h:1608
USART_TypeDef::RQR
__IO uint32_t RQR
USART Request register, Address offset: 0x18.
Definition stm32h723xx.h:1603
USART_TypeDef::CR3
__IO uint32_t CR3
USART Control register 3, Address offset: 0x08.
Definition stm32h723xx.h:1599