20#ifndef STM32H7xx_LL_RTC_H
21#define STM32H7xx_LL_RTC_H
47#define RTC_LL_INIT_MASK 0xFFFFFFFFU
48#define RTC_LL_RSF_MASK 0xFFFFFF5FU
51#define RTC_WRITE_PROTECTION_DISABLE 0xFFU
52#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU
53#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U
56#define RTC_OFFSET_WEEKDAY 24U
57#define RTC_OFFSET_DAY 16U
58#define RTC_OFFSET_MONTH 8U
59#define RTC_OFFSET_HOUR 16U
60#define RTC_OFFSET_MINUTE 8U
67#if defined(USE_FULL_LL_DRIVER)
77#if defined(USE_FULL_LL_DRIVER)
93 uint32_t AsynchPrescaler;
99 uint32_t SynchPrescaler;
164 LL_RTC_TimeTypeDef AlarmTime;
173 uint32_t AlarmDateWeekDaySel;
180 uint8_t AlarmDateWeekDay;
191} LL_RTC_AlarmTypeDef;
203#if defined(USE_FULL_LL_DRIVER)
207#define LL_RTC_FORMAT_BIN 0x00000000U
208#define LL_RTC_FORMAT_BCD 0x00000001U
216#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
217#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
225#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
226#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
238#define LL_RTC_SCR_ITSF RTC_SCR_CITSF
239#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
240#define LL_RTC_SCR_TSF RTC_SCR_CTSF
241#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
242#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
243#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
245#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
246#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
247#define LL_RTC_ICSR_RSF RTC_ICSR_RSF
248#define LL_RTC_ICSR_INITS RTC_ICSR_INITS
249#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
250#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
252#define LL_RTC_ISR_ITSF RTC_ISR_ITSF
253#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
254#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
255#if defined(RTC_TAMPER2_SUPPORT)
256#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
258#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
259#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
260#define LL_RTC_ISR_TSF RTC_ISR_TSF
261#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
262#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
263#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
264#define LL_RTC_ISR_INITF RTC_ISR_INITF
265#define LL_RTC_ISR_RSF RTC_ISR_RSF
266#define LL_RTC_ISR_INITS RTC_ISR_INITS
267#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
268#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
269#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
270#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
280#define LL_RTC_CR_TSIE RTC_CR_TSIE
281#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
282#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
283#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
285#if defined(RTC_TAMPxIE_SUPPORT)
286#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
287#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
288#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
290#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE
299#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
300#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
301#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
302#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
303#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
304#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
305#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07
313#define LL_RTC_MONTH_JANUARY (uint8_t)0x01
314#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
315#define LL_RTC_MONTH_MARCH (uint8_t)0x03
316#define LL_RTC_MONTH_APRIL (uint8_t)0x04
317#define LL_RTC_MONTH_MAY (uint8_t)0x05
318#define LL_RTC_MONTH_JUNE (uint8_t)0x06
319#define LL_RTC_MONTH_JULY (uint8_t)0x07
320#define LL_RTC_MONTH_AUGUST (uint8_t)0x08
321#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
322#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10
323#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
324#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12
332#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U
333#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
341#define LL_RTC_ALARMOUT_DISABLE 0x00000000U
342#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
343#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
344#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
353#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
354#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U
356#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
357#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
366#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
367#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
375#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
376#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM
384#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U
385#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S
393#define LL_RTC_ALMA_MASK_NONE 0x00000000U
394#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
395#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
396#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
397#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
398#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
406#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
407#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
415#define LL_RTC_ALMB_MASK_NONE 0x00000000U
416#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
417#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
418#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
419#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
420#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
428#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
429#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
437#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
438#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
446#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
447#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
456#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
457#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
458#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E
466#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
467#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
468#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK
476#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
477#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
478#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE
486#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
487#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
488#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
489#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
497#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
498#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
499#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
500#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
508#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
509#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
510#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
511#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
512#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
513#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
514#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
515#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ
523#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
524#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
525#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG
533#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
534#if defined(RTC_TAMPER2_SUPPORT)
535#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
537#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
547#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
548#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
549#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF
559#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
560#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
561#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE
569#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
570#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
571#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
572#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH
580#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
581#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
582#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
583#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
591#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
592#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
593#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
594#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
595#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
596#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
597#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
598#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ
606#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
607#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
608#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG
618#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM
619#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM
620#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM
628#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U
629#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
630#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
631#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
632#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
633#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
634#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
635#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
643#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)
644#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)
645#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)
647#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos)
648#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos)
649#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos)
651#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos)
652#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos)
653#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos)
662#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
663#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
664#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
665#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
666#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
667#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
675#define LL_RTC_BKP_DR0 0x00000000U
676#define LL_RTC_BKP_DR1 0x00000001U
677#define LL_RTC_BKP_DR2 0x00000002U
678#define LL_RTC_BKP_DR3 0x00000003U
679#define LL_RTC_BKP_DR4 0x00000004U
680#define LL_RTC_BKP_DR5 0x00000005U
681#define LL_RTC_BKP_DR6 0x00000006U
682#define LL_RTC_BKP_DR7 0x00000007U
683#define LL_RTC_BKP_DR8 0x00000008U
684#define LL_RTC_BKP_DR9 0x00000009U
685#define LL_RTC_BKP_DR10 0x0000000AU
686#define LL_RTC_BKP_DR11 0x0000000BU
687#define LL_RTC_BKP_DR12 0x0000000CU
688#define LL_RTC_BKP_DR13 0x0000000DU
689#define LL_RTC_BKP_DR14 0x0000000EU
690#define LL_RTC_BKP_DR15 0x0000000FU
691#define LL_RTC_BKP_DR16 0x00000010U
692#define LL_RTC_BKP_DR17 0x00000011U
693#define LL_RTC_BKP_DR18 0x00000012U
694#define LL_RTC_BKP_DR19 0x00000013U
695#define LL_RTC_BKP_DR20 0x00000014U
696#define LL_RTC_BKP_DR21 0x00000015U
697#define LL_RTC_BKP_DR22 0x00000016U
698#define LL_RTC_BKP_DR23 0x00000017U
699#define LL_RTC_BKP_DR24 0x00000018U
700#define LL_RTC_BKP_DR25 0x00000019U
701#define LL_RTC_BKP_DR26 0x0000001AU
702#define LL_RTC_BKP_DR27 0x0000001BU
703#define LL_RTC_BKP_DR28 0x0000001CU
704#define LL_RTC_BKP_DR29 0x0000001DU
705#define LL_RTC_BKP_DR30 0x0000001EU
706#define LL_RTC_BKP_DR31 0x0000001FU
714#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
715#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
716#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE
724#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
725#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
733#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
734#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
735#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
760#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
768#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
782#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
789#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))
811#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
818#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
837#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
844#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
859#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
866#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
873#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
978 return (uint32_t)(
READ_BIT(RTCx->
CR, RTC_CR_TAMPALRM_TYPE));
1024 WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
1036 WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
1258 return ((
READ_BIT(RTCx->
CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL);
1291 return ((
READ_BIT(RTCx->
CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL);
1327 return ((
READ_BIT(RTCx->
CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL);
1520__STATIC_INLINE void LL_RTC_TIME_Config(
RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
1524 temp = Format12_24 | \
2178__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(
RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
2204 return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
2544__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(
RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
2570 return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
2942 SET_BIT(RTCx->TAMPCR, Tamper);
3042 SET_BIT(RTCx->TAMPCR, Tamper);
3184 SET_BIT(RTCx->TAMPCR, Tamper);
3221__STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3239__STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3258__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
3276__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
3294__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3312__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3330__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3348__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3361 SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
3372 CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
3386__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration)
3388 MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
3401__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx)
3403 return (uint32_t)(
READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH));
3417__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount)
3419 MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
3432__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx)
3434 return (uint32_t)(
READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT));
3452__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
3454 MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
3471__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx)
3473 return (uint32_t)(
READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ));
3635 tmp = (uint32_t)(&(RTCx->
BKP0R));
3636 tmp += (BackupRegister * 4U);
3639 *(
__IO uint32_t *)tmp = (uint32_t)Data;
3685 tmp = (uint32_t)(&(RTCx->
BKP0R));
3686 tmp += (BackupRegister * 4U);
3689 return (*(
__IO uint32_t *)tmp);
3732__STATIC_INLINE void LL_RTC_BKP_SetRegister(
const TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
3736 tmp = (uint32_t)(&(TAMPx->BKP0R));
3737 tmp += (BackupRegister * 4U);
3740 *(
__IO uint32_t *)tmp = (uint32_t)Data;
3782__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
3786 tmp = (uint32_t)(&(TAMPx->BKP0R));
3787 tmp += (BackupRegister * 4U);
3790 return (*(
__IO uint32_t *)tmp);
3963#if defined(RTC_TAMPER2_SUPPORT)
4064#if defined(RTC_TAMPER2_SUPPORT)
4241 return ((
READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL);
4252 return ((
READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL);
4263 return ((
READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL);
4274 return ((
READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL);
4285 return ((
READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL);
4296 return ((
READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);
4307 SET_BIT(RTCx->SCR, RTC_SCR_CITSF);
4318 SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
4329 SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
4340 SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
4351 SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
4362 SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
4373 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL);
4384 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL);
4395 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL);
4406 WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
4417 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL);
4428 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL);
4439 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL);
4450 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL);
4461 return ((
READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);
4472 return ((
READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL);
4483 return ((
READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL);
4494 return ((
READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL);
4505 return ((
READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL);
4516 return ((
READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL);
4527 return ((
READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);
4536__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx)
4538 return ((
READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);
4547__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx)
4549 return ((
READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);
4558__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx)
4560 return ((
READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);
4569__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx)
4571 return ((
READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);
4580__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx)
4582 return ((
READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);
4591__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx)
4593 return ((
READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);
4604 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F);
4615 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F);
4626 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F);
4735#if defined(RTC_TAMPxIE_SUPPORT)
4758#if defined(RTC_TAMPER2_SUPPORT)
4873#if defined(RTC_TAMPxIE_SUPPORT)
4930 SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
4941 CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
4952 SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
4963 CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
4974 SET_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
4985 CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
4996 return ((
READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);
5007 return ((
READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);
5018 return ((
READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);
5038__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
5053__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
5065 SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
5075 CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
5084__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
5086 MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
5094__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(
void)
5096 return (
READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
5107__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
5109 MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
5119 return (
READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
5129 SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
5139 CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
5150__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
5152 MODIFY_REG(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3), \
5161__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(
void)
5163 return (
READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3)));
5184 return ((
READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
5194 return ((
READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
5203#if defined(USE_FULL_LL_DRIVER)
5210void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
5212void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
5214void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
5215ErrorStatus LL_RTC_ALMA_Init(
RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5216ErrorStatus LL_RTC_ALMB_Init(
RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5217void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5218void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
#define __IO
Defines 'read / write' permissions.
#define CLEAR_BIT(REG, BIT)
#define SET_BIT(REG, BIT)
#define WRITE_REG(REG, VAL)
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
#define READ_BIT(REG, BIT)
#define RTC_ALRMBSSR_MASKSS_Pos
#define RTC_PRER_PREDIV_S
#define RTC_TAMPCR_TAMP2IE
#define RTC_TAMPCR_TAMPPRCH
#define RTC_ALRMAR_SU_Pos
#define RTC_TAMPCR_TAMPPUDIS
#define RTC_TAMPCR_TAMPFLT
#define RTC_TAMPCR_TAMPTS
#define RTC_ALRMBR_DU_Pos
#define RTC_ALRMBR_ST_Pos
#define RTC_TAMPCR_TAMP3IE
#define RTC_ALRMASSR_MASKSS
#define RTC_ALRMAR_ST_Pos
#define RTC_ALRMAR_HU_Pos
#define RTC_ALRMASSR_MASKSS_Pos
#define RTC_ALRMBR_MNT_Pos
#define RTC_ALRMAR_DU_Pos
#define RTC_ALRMAR_DT_Pos
#define RTC_OR_ALARMOUTTYPE
#define RTC_ALRMBR_MNU_Pos
#define RTC_TAMPCR_TAMPFREQ
#define RTC_ALRMAR_MNU_Pos
#define RTC_TAMPCR_TAMPIE
#define RTC_PRER_PREDIV_A
#define RTC_ALRMBR_HT_Pos
#define RTC_ALRMBR_DT_Pos
#define RTC_ALRMAR_HT_Pos
#define RTC_PRER_PREDIV_A_Pos
#define RTC_TAMPCR_TAMP1IE
#define RTC_ALRMAR_MNT_Pos
#define RTC_ALRMBR_SU_Pos
#define RTC_ALRMBSSR_MASKSS
#define RTC_ALRMBR_HU_Pos
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
__IO uint32_t TSTR
RTC time stamp time register, Address offset: 0x30.
__IO uint32_t TSSSR
RTC time-stamp sub second register, Address offset: 0x38.
__IO uint32_t ALRMBSSR
RTC alarm B sub second register, Address offset: 0x48.
__IO uint32_t TR
RTC time register, Address offset: 0x00.
__IO uint32_t ISR
RTC initialization and status register, Address offset: 0x0C.
__IO uint32_t PRER
RTC prescaler register, Address offset: 0x10.
__IO uint32_t SHIFTR
RTC shift control register, Address offset: 0x2C.
__IO uint32_t CR
RTC control register, Address offset: 0x08.
__IO uint32_t DR
RTC date register, Address offset: 0x04.
__IO uint32_t ALRMBR
RTC alarm B register, Address offset: 0x20.
__IO uint32_t TSDR
RTC time stamp date register, Address offset: 0x34.
__IO uint32_t BKP0R
RTC backup register 0, Address offset: 0x50.
__IO uint32_t OR
RTC option register, Address offset: 0x4C.
__IO uint32_t ALRMASSR
RTC alarm A sub second register, Address offset: 0x44.
__IO uint32_t WPR
RTC write protection register, Address offset: 0x24.
__IO uint32_t ALRMAR
RTC alarm A register, Address offset: 0x1C.
__IO uint32_t WUTR
RTC wakeup timer register, Address offset: 0x14.
__IO uint32_t CALR
RTC calibration register, Address offset: 0x3C.
__IO uint32_t SSR
RTC sub second register, Address offset: 0x28.