STAR
Cal STAR — firmware, DAQ server, and engine design
Loading...
Searching...
No Matches
stm32h7xx_ll_spi.h
Go to the documentation of this file.
1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_SPI_H
21#define STM32H7xx_LL_SPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
36/** @defgroup SPI_LL SPI
37 * @{
38 */
39
40/* Private variables ---------------------------------------------------------*/
41
42/* Private constants ---------------------------------------------------------*/
43
44/* Private macros ------------------------------------------------------------*/
45/** @defgroup SPI_LL_Private_Macros SPI Private Macros
46 * @{
47 */
48/**
49 * @}
50 */
51
52/* Exported types ------------------------------------------------------------*/
53#if defined(USE_FULL_LL_DRIVER)
54/** @defgroup SPI_LL_Exported_Types SPI Exported Types
55 * @{
56 */
57
58/**
59 * @brief SPI Init structures definition
60 */
61typedef struct
62{
63 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
64 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
65
66 This feature can be modified afterwards using unitary function
67 @ref LL_SPI_SetTransferDirection().*/
68
69 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
70 This parameter can be a value of @ref SPI_LL_EC_MODE.
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_SPI_SetMode().*/
74
75 uint32_t DataWidth; /*!< Specifies the SPI data width.
76 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_SPI_SetDataWidth().*/
80
81 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
82 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
83
84 This feature can be modified afterwards using unitary function
85 @ref LL_SPI_SetClockPolarity().*/
86
87 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
88 This parameter can be a value of @ref SPI_LL_EC_PHASE.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_SPI_SetClockPhase().*/
92
93 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
94 or by software using the SSI bit.
95
96 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
97
98 This feature can be modified afterwards using unitary function
99 @ref LL_SPI_SetNSSMode().*/
100
101 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
102 the transmit and receive SCK clock.
103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
104 @note The communication clock is derived from the master clock.
105 The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_SPI_SetTransferBitOrder().*/
115
116 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
117 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
118
119 This feature can be modified afterwards using unitary functions
120 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
121
122 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
123 This parameter must be a number between Min_Data = 0x00
124 and Max_Data = 0xFFFFFFFF.
125
126 This feature can be modified afterwards using unitary function
127 @ref LL_SPI_SetCRCPolynomial().*/
128
129} LL_SPI_InitTypeDef;
130
131/**
132 * @}
133 */
134#endif /*USE_FULL_LL_DRIVER*/
135
136/* Exported types ------------------------------------------------------------*/
137
138/* Exported constants --------------------------------------------------------*/
139/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
140 * @{
141 */
142
143/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
144 * @brief Flags defines which can be used with LL_SPI_ReadReg function
145 * @{
146 */
147#define LL_SPI_SR_RXP (SPI_SR_RXP)
148#define LL_SPI_SR_TXP (SPI_SR_TXP)
149#define LL_SPI_SR_DXP (SPI_SR_DXP)
150#define LL_SPI_SR_EOT (SPI_SR_EOT)
151#define LL_SPI_SR_TXTF (SPI_SR_TXTF)
152#define LL_SPI_SR_UDR (SPI_SR_UDR)
153#define LL_SPI_SR_CRCE (SPI_SR_CRCE)
154#define LL_SPI_SR_MODF (SPI_SR_MODF)
155#define LL_SPI_SR_OVR (SPI_SR_OVR)
156#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
157#define LL_SPI_SR_TSERF (SPI_SR_TSERF)
158#define LL_SPI_SR_SUSP (SPI_SR_SUSP)
159#define LL_SPI_SR_TXC (SPI_SR_TXC)
160#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
161/**
162 * @}
163 */
164
165/** @defgroup SPI_LL_EC_IT IT Defines
166 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
167 * @{
168 */
169#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
170#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
171#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
172#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
173#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
174#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
175#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
176#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
177#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
178#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
179#define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)
180/**
181 * @}
182 */
183
184/** @defgroup SPI_LL_EC_MODE Mode
185 * @{
186 */
187#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
188#define LL_SPI_MODE_SLAVE (0x00000000UL)
189/**
190 * @}
191 */
192
193/** @defgroup SPI_LL_EC_SS_LEVEL SS Level
194 * @{
195 */
196#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
197#define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
198/**
199 * @}
200 */
201
202/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
203 * @{
204 */
205#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
206#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
207#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
208#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
209#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
210#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
211#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
212#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
213#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
214#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
215#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
216#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
217#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
218#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
219#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
220#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
221 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
222/**
223 * @}
224 */
225
226/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
227 * @{
228 */
229#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
230#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
231#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
232#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
233#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
234#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
235#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
236#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
237#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
238#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
239#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
240#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
241#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
242#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
243#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
244#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
245 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
246/**
247 * @}
248 */
249
250/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
251 * @{
252 */
253#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
254#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
255/**
256 * @}
257 */
258
259/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
260 * @{
261 */
262#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
263#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
264/**
265 * @}
266 */
267
268/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
269 * @{
270 */
271#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
272#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
273#define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)
274/**
275 * @}
276 */
277
278/** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data
279 * @{
280 */
281#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
282#define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
283#define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)
284/**
285 * @}
286 */
287
288/** @defgroup SPI_LL_EC_PROTOCOL Protocol
289 * @{
290 */
291#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
292#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
293/**
294 * @}
295 */
296
297/** @defgroup SPI_LL_EC_PHASE Phase
298 * @{
299 */
300#define LL_SPI_PHASE_1EDGE (0x00000000UL)
301#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
302/**
303 * @}
304 */
305
306/** @defgroup SPI_LL_EC_POLARITY Polarity
307 * @{
308 */
309#define LL_SPI_POLARITY_LOW (0x00000000UL)
310#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
311/**
312 * @}
313 */
314
315/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
316 * @{
317 */
318#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
319#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
320/**
321 * @}
322 */
323
324/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
325 * @{
326 */
327#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
328#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
329#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
330#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
331#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
332#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
333#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
334#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
335/**
336 * @}
337 */
338
339/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
340 * @{
341 */
342#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
343#define LL_SPI_MSB_FIRST (0x00000000UL)
344/**
345 * @}
346 */
347
348/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
349 * @{
350 */
351#define LL_SPI_FULL_DUPLEX (0x00000000UL)
352#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
353#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
354#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
355#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
356/**
357 * @}
358 */
359
360/** @defgroup SPI_LL_EC_DATAWIDTH Data Width
361 * @{
362 */
363#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
364#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
365#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
366#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
367#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
368#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
369#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
370#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
371#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
372#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
373#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
374#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
375#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
376 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
377#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
378#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
379#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
380#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
381#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
382#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
383#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
384#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
385 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
386#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
387#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
388#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
389#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
390 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
391#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
392#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
393 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
394#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
395 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
396#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
397 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
398/**
399 * @}
400 */
401
402/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
403 * @{
404 */
405#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
406#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
407#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
408#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
409#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
410#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
411#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
412#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
413#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
414#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
415#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
416#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
417#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
418#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
419#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
420#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
421 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
422/**
423 * @}
424 */
425
426#if defined(USE_FULL_LL_DRIVER)
427
428/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
429 * @{
430 */
431#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
432#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
433/**
434 * @}
435 */
436#endif /* USE_FULL_LL_DRIVER */
437
438/** @defgroup SPI_LL_EC_CRC CRC
439 * @{
440 */
441#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
442#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
443#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
444#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
445#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
446#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
447#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
448#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
449#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
450#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
451#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
452#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
453#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
454 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
455#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
456#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
457#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
458#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
459#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
460#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
461#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
462#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
463 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
464#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
465#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
466#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
467#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
468 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
469#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
470#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
471 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
472#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
473 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
474#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
475 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
476/**
477 * @}
478 */
479
480/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
481 * @{
482 */
483#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
484#define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
485#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
486/**
487 * @}
488 */
489
490/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
491 * @{
492 */
493#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
494#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
495#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
496#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
497/**
498 * @}
499 */
500
501/**
502 * @}
503 */
504
505/* Exported macro ------------------------------------------------------------*/
506/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
507 * @{
508 */
509
510/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
511 * @{
512 */
513
514/**
515 * @brief Write a value in SPI register
516 * @param __INSTANCE__ SPI Instance
517 * @param __REG__ Register to be written
518 * @param __VALUE__ Value to be written in the register
519 * @retval None
520 */
521#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
522
523/**
524 * @brief Read a value in SPI register
525 * @param __INSTANCE__ SPI Instance
526 * @param __REG__ Register to be read
527 * @retval Register value
528 */
529#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
530/**
531 * @}
532 */
533
534/**
535 * @}
536 */
537
538
539/* Exported functions --------------------------------------------------------*/
540
541/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
542 * @{
543 */
544
545/** @defgroup SPI_LL_EF_Configuration Configuration
546 * @{
547 */
548
549/**
550 * @brief Enable SPI peripheral
551 * @rmtoll CR1 SPE LL_SPI_Enable
552 * @param SPIx SPI Instance
553 * @retval None
554 */
555__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
556{
557 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
558}
559
560/**
561 * @brief Disable SPI peripheral
562 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
563 * @rmtoll CR1 SPE LL_SPI_Disable
564 * @param SPIx SPI Instance
565 * @retval None
566 */
567__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
568{
569 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
570}
571
572/**
573 * @brief Check if SPI peripheral is enabled
574 * @rmtoll CR1 SPE LL_SPI_IsEnabled
575 * @param SPIx SPI Instance
576 * @retval State of bit (1 or 0)
577 */
578__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
579{
580 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
581}
582
583/**
584 * @brief Swap the MOSI and MISO pin
585 * @note This configuration can not be changed when SPI is enabled.
586 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
587 * @param SPIx SPI Instance
588 * @retval None
589 */
590__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
591{
592 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
593}
594
595/**
596 * @brief Restore default function for MOSI and MISO pin
597 * @note This configuration can not be changed when SPI is enabled.
598 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
599 * @param SPIx SPI Instance
600 * @retval None
601 */
602__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
603{
604 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
605}
606
607/**
608 * @brief Check if MOSI and MISO pin are swapped
609 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
610 * @param SPIx SPI Instance
611 * @retval State of bit (1 or 0)
612 */
613__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
614{
615 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
616}
617
618/**
619 * @brief Enable GPIO control
620 * @note This configuration can not be changed when SPI is enabled.
621 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
622 * @param SPIx SPI Instance
623 * @retval None
624 */
625__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
626{
627 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
628}
629
630/**
631 * @brief Disable GPIO control
632 * @note This configuration can not be changed when SPI is enabled.
633 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
634 * @param SPIx SPI Instance
635 * @retval None
636 */
637__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
638{
639 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
640}
641
642/**
643 * @brief Check if GPIO control is active
644 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
645 * @param SPIx SPI Instance
646 * @retval State of bit (1 or 0)
647 */
648__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
649{
650 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
651}
652
653/**
654 * @brief Set SPI Mode to Master or Slave
655 * @note This configuration can not be changed when SPI is enabled.
656 * @rmtoll CFG2 MASTER LL_SPI_SetMode
657 * @param SPIx SPI Instance
658 * @param Mode This parameter can be one of the following values:
659 * @arg @ref LL_SPI_MODE_MASTER
660 * @arg @ref LL_SPI_MODE_SLAVE
661 * @retval None
662 */
663__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
664{
665 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
666}
667
668/**
669 * @brief Get SPI Mode (Master or Slave)
670 * @rmtoll CFG2 MASTER LL_SPI_GetMode
671 * @param SPIx SPI Instance
672 * @retval Returned value can be one of the following values:
673 * @arg @ref LL_SPI_MODE_MASTER
674 * @arg @ref LL_SPI_MODE_SLAVE
675 */
676__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
677{
678 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
679}
680
681/**
682 * @brief Configure the Idleness applied by master between active edge of SS and first send data
683 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
684 * @param SPIx SPI Instance
685 * @param MasterSSIdleness This parameter can be one of the following values:
686 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
687 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
688 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
689 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
690 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
691 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
692 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
693 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
694 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
695 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
696 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
697 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
698 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
699 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
700 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
701 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
702 * @retval None
703 */
704__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
705{
706 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
707}
708
709/**
710 * @brief Get the configured Idleness applied by master
711 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
712 * @param SPIx SPI Instance
713 * @retval Returned value can be one of the following values:
714 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
715 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
716 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
717 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
718 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
719 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
720 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
721 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
722 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
723 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
724 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
725 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
726 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
727 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
728 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
729 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
730 */
731__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
732{
733 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
734}
735
736/**
737 * @brief Configure the idleness applied by master between data frame
738 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
739 * @param SPIx SPI Instance
740 * @param MasterInterDataIdleness This parameter can be one of the following values:
741 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
742 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
743 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
744 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
745 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
746 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
747 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
748 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
749 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
750 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
751 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
752 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
753 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
754 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
755 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
756 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
757 * @retval None
758 */
759__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
760{
761 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
762}
763
764/**
765 * @brief Get the configured inter data idleness
766 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
767 * @param SPIx SPI Instance
768 * @retval Returned value can be one of the following values:
769 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
770 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
771 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
772 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
773 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
774 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
775 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
776 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
777 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
778 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
779 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
780 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
781 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
782 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
783 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
784 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
785 */
786__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
787{
788 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
789}
790
791/**
792 * @brief Set transfer size
793 * @note Count is the number of frame to be transferred
794 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
795 * @param SPIx SPI Instance
796 * @param Count 0..0xFFFF
797 * @retval None
798 */
799__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
800{
801 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
802}
803
804/**
805 * @brief Get transfer size
806 * @note Count is the number of frame to be transferred
807 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
808 * @param SPIx SPI Instance
809 * @retval 0..0xFFFF
810 */
811__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
812{
813 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
814}
815
816/**
817 * @brief Set reload transfer size
818 * @note Count is the number of frame to be transferred
819 * @rmtoll CR2 TSER LL_SPI_SetReloadSize
820 * @param SPIx SPI Instance
821 * @param Count 0..0xFFFF
822 * @retval None
823 */
824__STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
825{
826 MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);
827}
828
829/**
830 * @brief Get reload transfer size
831 * @note Count is the number of frame to be transferred
832 * @rmtoll CR2 TSER LL_SPI_GetReloadSize
833 * @param SPIx SPI Instance
834 * @retval 0..0xFFFF
835 */
836__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(const SPI_TypeDef *SPIx)
837{
838 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
839}
840
841/**
842 * @brief Lock the AF configuration of associated IOs
843 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
844 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
845 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
846 * @param SPIx SPI Instance
847 * @retval None
848 */
849__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
850{
851 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
852}
853
854/**
855 * @brief Check if the AF configuration is locked.
856 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
857 * @param SPIx SPI Instance
858 * @retval State of bit (1 or 0)
859 */
860__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
861{
862 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
863}
864
865/**
866 * @brief Set Tx CRC Initialization Pattern
867 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
868 * @param SPIx SPI Instance
869 * @param TXCRCInitAll This parameter can be one of the following values:
870 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
871 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
872 * @retval None
873 */
874__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
875{
876 MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
877}
878
879/**
880 * @brief Get Tx CRC Initialization Pattern
881 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
882 * @param SPIx SPI Instance
883 * @retval Returned value can be one of the following values:
884 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
885 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
886 */
887__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
888{
889 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
890}
891
892/**
893 * @brief Set Rx CRC Initialization Pattern
894 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
895 * @param SPIx SPI Instance
896 * @param RXCRCInitAll This parameter can be one of the following values:
897 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
898 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
899 * @retval None
900 */
901__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
902{
903 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
904}
905
906/**
907 * @brief Get Rx CRC Initialization Pattern
908 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
909 * @param SPIx SPI Instance
910 * @retval Returned value can be one of the following values:
911 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
912 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
913 */
914__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
915{
916 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
917}
918
919/**
920 * @brief Set internal SS input level ignoring what comes from PIN.
921 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
922 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
923 * @param SPIx SPI Instance
924 * @param SSLevel This parameter can be one of the following values:
925 * @arg @ref LL_SPI_SS_LEVEL_HIGH
926 * @arg @ref LL_SPI_SS_LEVEL_LOW
927 * @retval None
928 */
929__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
930{
931 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
932}
933
934/**
935 * @brief Get internal SS input level
936 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
937 * @param SPIx SPI Instance
938 * @retval Returned value can be one of the following values:
939 * @arg @ref LL_SPI_SS_LEVEL_HIGH
940 * @arg @ref LL_SPI_SS_LEVEL_LOW
941 */
942__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
943{
944 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
945}
946
947/**
948 * @brief Enable CRC computation on 33/17 bits
949 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
950 * @param SPIx SPI Instance
951 * @retval None
952 */
953__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
954{
955 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
956}
957
958/**
959 * @brief Disable CRC computation on 33/17 bits
960 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
961 * @param SPIx SPI Instance
962 * @retval None
963 */
964__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
965{
966 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
967}
968
969/**
970 * @brief Check if Enable CRC computation on 33/17 bits is enabled
971 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
972 * @param SPIx SPI Instance
973 * @retval State of bit (1 or 0)
974 */
975__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
976{
977 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
978}
979
980/**
981 * @brief Suspend an ongoing transfer for Master configuration
982 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
983 * @param SPIx SPI Instance
984 * @retval None
985 */
986__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
987{
988 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
989}
990
991/**
992 * @brief Start effective transfer on wire for Master configuration
993 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
994 * @param SPIx SPI Instance
995 * @retval None
996 */
997__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
998{
999 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
1000}
1001
1002/**
1003 * @brief Check if there is an unfinished master transfer
1004 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
1005 * @param SPIx SPI Instance
1006 * @retval State of bit (1 or 0)
1007 */
1008__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
1009{
1010 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
1011}
1012
1013/**
1014 * @brief Enable Master Rx auto suspend in case of overrun
1015 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
1016 * @param SPIx SPI Instance
1017 * @retval None
1018 */
1019__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1020{
1021 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
1022}
1023
1024/**
1025 * @brief Disable Master Rx auto suspend in case of overrun
1026 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
1027 * @param SPIx SPI Instance
1028 * @retval None
1029 */
1030__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1031{
1032 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
1033}
1034
1035/**
1036 * @brief Check if Master Rx auto suspend is activated
1037 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1038 * @param SPIx SPI Instance
1039 * @retval State of bit (1 or 0)
1040 */
1041__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
1042{
1043 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1044}
1045
1046/**
1047 * @brief Set Underrun behavior
1048 * @note This configuration can not be changed when SPI is enabled.
1049 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1050 * @param SPIx SPI Instance
1051 * @param UDRConfig This parameter can be one of the following values:
1052 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1053 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1054 * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
1055 * @retval None
1056 */
1057__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1058{
1059 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1060}
1061
1062/**
1063 * @brief Get Underrun behavior
1064 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1065 * @param SPIx SPI Instance
1066 * @retval Returned value can be one of the following values:
1067 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1068 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1069 * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
1070 */
1071__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
1072{
1073 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1074}
1075
1076/**
1077 * @brief Set Underrun Detection method
1078 * @note This configuration can not be changed when SPI is enabled.
1079 * @rmtoll CFG1 UDRDET LL_SPI_SetUDRDetection
1080 * @param SPIx SPI Instance
1081 * @param UDRDetection This parameter can be one of the following values:
1082 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
1083 * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
1084 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
1085 * @retval None
1086 */
1087__STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)
1088{
1089 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);
1090}
1091
1092/**
1093 * @brief Get Underrun Detection method
1094 * @rmtoll CFG1 UDRDET LL_SPI_GetUDRDetection
1095 * @param SPIx SPI Instance
1096 * @retval Returned value can be one of the following values:
1097 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
1098 * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
1099 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
1100 */
1101__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(const SPI_TypeDef *SPIx)
1102{
1103 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
1104}
1105
1106/**
1107 * @brief Set Serial protocol used
1108 * @note This configuration can not be changed when SPI is enabled.
1109 * @rmtoll CFG2 SP LL_SPI_SetStandard
1110 * @param SPIx SPI Instance
1111 * @param Standard This parameter can be one of the following values:
1112 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1113 * @arg @ref LL_SPI_PROTOCOL_TI
1114 * @retval None
1115 */
1116__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1117{
1118 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1119}
1120
1121/**
1122 * @brief Get Serial protocol used
1123 * @rmtoll CFG2 SP LL_SPI_GetStandard
1124 * @param SPIx SPI Instance
1125 * @retval Returned value can be one of the following values:
1126 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1127 * @arg @ref LL_SPI_PROTOCOL_TI
1128 */
1129__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
1130{
1131 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1132}
1133
1134/**
1135 * @brief Set Clock phase
1136 * @note This configuration can not be changed when SPI is enabled.
1137 * This bit is not used in SPI TI mode.
1138 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1139 * @param SPIx SPI Instance
1140 * @param ClockPhase This parameter can be one of the following values:
1141 * @arg @ref LL_SPI_PHASE_1EDGE
1142 * @arg @ref LL_SPI_PHASE_2EDGE
1143 * @retval None
1144 */
1145__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1146{
1147 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1148}
1149
1150/**
1151 * @brief Get Clock phase
1152 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1153 * @param SPIx SPI Instance
1154 * @retval Returned value can be one of the following values:
1155 * @arg @ref LL_SPI_PHASE_1EDGE
1156 * @arg @ref LL_SPI_PHASE_2EDGE
1157 */
1158__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
1159{
1160 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1161}
1162
1163/**
1164 * @brief Set Clock polarity
1165 * @note This configuration can not be changed when SPI is enabled.
1166 * This bit is not used in SPI TI mode.
1167 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1168 * @param SPIx SPI Instance
1169 * @param ClockPolarity This parameter can be one of the following values:
1170 * @arg @ref LL_SPI_POLARITY_LOW
1171 * @arg @ref LL_SPI_POLARITY_HIGH
1172 * @retval None
1173 */
1174__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1175{
1176 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1177}
1178
1179/**
1180 * @brief Get Clock polarity
1181 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1182 * @param SPIx SPI Instance
1183 * @retval Returned value can be one of the following values:
1184 * @arg @ref LL_SPI_POLARITY_LOW
1185 * @arg @ref LL_SPI_POLARITY_HIGH
1186 */
1187__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
1188{
1189 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1190}
1191
1192/**
1193 * @brief Set NSS polarity
1194 * @note This configuration can not be changed when SPI is enabled.
1195 * This bit is not used in SPI TI mode.
1196 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1197 * @param SPIx SPI Instance
1198 * @param NSSPolarity This parameter can be one of the following values:
1199 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1200 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1201 * @retval None
1202 */
1203__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1204{
1205 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1206}
1207
1208/**
1209 * @brief Get NSS polarity
1210 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1211 * @param SPIx SPI Instance
1212 * @retval Returned value can be one of the following values:
1213 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1214 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1215 */
1216__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
1217{
1218 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1219}
1220
1221/**
1222 * @brief Set Baudrate Prescaler
1223 * @note This configuration can not be changed when SPI is enabled.
1224 * SPI BaudRate = fPCLK/Pescaler.
1225 * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler
1226 * @param SPIx SPI Instance
1227 * @param Baudrate This parameter can be one of the following values:
1228 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1229 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1230 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1231 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1232 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1233 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1234 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1235 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1236 * @retval None
1237 */
1238__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1239{
1240 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);
1241}
1242
1243/**
1244 * @brief Get Baudrate Prescaler
1245 * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler
1246 * @param SPIx SPI Instance
1247 * @retval Returned value can be one of the following values:
1248 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1249 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1250 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1251 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1252 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1253 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1254 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1255 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1256 */
1257__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
1258{
1259 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
1260}
1261
1262/**
1263 * @brief Set Transfer Bit Order
1264 * @note This configuration can not be changed when SPI is enabled.
1265 * This bit is not used in SPI TI mode.
1266 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1267 * @param SPIx SPI Instance
1268 * @param BitOrder This parameter can be one of the following values:
1269 * @arg @ref LL_SPI_LSB_FIRST
1270 * @arg @ref LL_SPI_MSB_FIRST
1271 * @retval None
1272 */
1273__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1274{
1275 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1276}
1277
1278/**
1279 * @brief Get Transfer Bit Order
1280 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1281 * @param SPIx SPI Instance
1282 * @retval Returned value can be one of the following values:
1283 * @arg @ref LL_SPI_LSB_FIRST
1284 * @arg @ref LL_SPI_MSB_FIRST
1285 */
1286__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
1287{
1288 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1289}
1290
1291/**
1292 * @brief Set Transfer Mode
1293 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1294 * using LL_SPI_SetHalfDuplexDirection.
1295 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1296 * CFG2 COMM LL_SPI_SetTransferDirection
1297 * @param SPIx SPI Instance
1298 * @param TransferDirection This parameter can be one of the following values:
1299 * @arg @ref LL_SPI_FULL_DUPLEX
1300 * @arg @ref LL_SPI_SIMPLEX_TX
1301 * @arg @ref LL_SPI_SIMPLEX_RX
1302 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1303 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1304 * @retval None
1305 */
1306__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1307{
1308 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1309 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1310}
1311
1312/**
1313 * @brief Get Transfer Mode
1314 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1315 * CFG2 COMM LL_SPI_GetTransferDirection
1316 * @param SPIx SPI Instance
1317 * @retval Returned value can be one of the following values:
1318 * @arg @ref LL_SPI_FULL_DUPLEX
1319 * @arg @ref LL_SPI_SIMPLEX_TX
1320 * @arg @ref LL_SPI_SIMPLEX_RX
1321 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1322 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1323 */
1324__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
1325{
1326 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1327 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1328 return (Hddir | Comm);
1329}
1330
1331/**
1332 * @brief Set direction for Half-Duplex Mode
1333 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1334 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1335 * @param SPIx SPI Instance
1336 * @param HalfDuplexDirection This parameter can be one of the following values:
1337 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1338 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1339 * @retval None
1340 */
1341__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1342{
1343 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1344}
1345
1346/**
1347 * @brief Get direction for Half-Duplex Mode
1348 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1349 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1350 * @param SPIx SPI Instance
1351 * @retval Returned value can be one of the following values:
1352 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1353 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1354 */
1355__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
1356{
1357 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1358}
1359
1360/**
1361 * @brief Set Frame Data Size
1362 * @note This configuration can not be changed when SPI is enabled.
1363 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1364 * @param SPIx SPI Instance
1365 * @param DataWidth This parameter can be one of the following values:
1366 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1367 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1368 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1369 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1370 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1371 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1372 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1373 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1374 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1375 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1376 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1377 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1378 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1379 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1380 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1381 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1382 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1383 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1384 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1385 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1386 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1387 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1388 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1389 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1390 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1391 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1392 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1393 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1394 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1395 * @retval None
1396 */
1397__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1398{
1399 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1400}
1401
1402/**
1403 * @brief Get Frame Data Size
1404 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1405 * @param SPIx SPI Instance
1406 * @retval Returned value can be one of the following values:
1407 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1408 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1409 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1410 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1411 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1412 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1413 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1414 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1415 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1416 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1417 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1418 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1419 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1420 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1421 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1422 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1423 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1424 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1425 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1426 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1427 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1428 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1429 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1430 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1431 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1432 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1433 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1434 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1435 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1436 */
1437__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
1438{
1439 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1440}
1441
1442/**
1443 * @brief Set threshold of FIFO that triggers a transfer event
1444 * @note This configuration can not be changed when SPI is enabled.
1445 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1446 * @param SPIx SPI Instance
1447 * @param Threshold This parameter can be one of the following values:
1448 * @arg @ref LL_SPI_FIFO_TH_01DATA
1449 * @arg @ref LL_SPI_FIFO_TH_02DATA
1450 * @arg @ref LL_SPI_FIFO_TH_03DATA
1451 * @arg @ref LL_SPI_FIFO_TH_04DATA
1452 * @arg @ref LL_SPI_FIFO_TH_05DATA
1453 * @arg @ref LL_SPI_FIFO_TH_06DATA
1454 * @arg @ref LL_SPI_FIFO_TH_07DATA
1455 * @arg @ref LL_SPI_FIFO_TH_08DATA
1456 * @arg @ref LL_SPI_FIFO_TH_09DATA
1457 * @arg @ref LL_SPI_FIFO_TH_10DATA
1458 * @arg @ref LL_SPI_FIFO_TH_11DATA
1459 * @arg @ref LL_SPI_FIFO_TH_12DATA
1460 * @arg @ref LL_SPI_FIFO_TH_13DATA
1461 * @arg @ref LL_SPI_FIFO_TH_14DATA
1462 * @arg @ref LL_SPI_FIFO_TH_15DATA
1463 * @arg @ref LL_SPI_FIFO_TH_16DATA
1464 * @retval None
1465 */
1466__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1467{
1468 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1469}
1470
1471/**
1472 * @brief Get threshold of FIFO that triggers a transfer event
1473 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1474 * @param SPIx SPI Instance
1475 * @retval Returned value can be one of the following values:
1476 * @arg @ref LL_SPI_FIFO_TH_01DATA
1477 * @arg @ref LL_SPI_FIFO_TH_02DATA
1478 * @arg @ref LL_SPI_FIFO_TH_03DATA
1479 * @arg @ref LL_SPI_FIFO_TH_04DATA
1480 * @arg @ref LL_SPI_FIFO_TH_05DATA
1481 * @arg @ref LL_SPI_FIFO_TH_06DATA
1482 * @arg @ref LL_SPI_FIFO_TH_07DATA
1483 * @arg @ref LL_SPI_FIFO_TH_08DATA
1484 * @arg @ref LL_SPI_FIFO_TH_09DATA
1485 * @arg @ref LL_SPI_FIFO_TH_10DATA
1486 * @arg @ref LL_SPI_FIFO_TH_11DATA
1487 * @arg @ref LL_SPI_FIFO_TH_12DATA
1488 * @arg @ref LL_SPI_FIFO_TH_13DATA
1489 * @arg @ref LL_SPI_FIFO_TH_14DATA
1490 * @arg @ref LL_SPI_FIFO_TH_15DATA
1491 * @arg @ref LL_SPI_FIFO_TH_16DATA
1492 */
1493__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
1494{
1495 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1496}
1497
1498/**
1499 * @brief Enable CRC
1500 * @note This configuration can not be changed when SPI is enabled.
1501 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1502 * @param SPIx SPI Instance
1503 * @retval None
1504 */
1505__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1506{
1507 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1508}
1509
1510/**
1511 * @brief Disable CRC
1512 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1513 * @param SPIx SPI Instance
1514 * @retval None
1515 */
1516__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1517{
1518 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1519}
1520
1521/**
1522 * @brief Check if CRC is enabled
1523 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1524 * @param SPIx SPI Instance
1525 * @retval State of bit (1 or 0).
1526 */
1527__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
1528{
1529 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1530}
1531
1532/**
1533 * @brief Set CRC Length
1534 * @note This configuration can not be changed when SPI is enabled.
1535 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1536 * @param SPIx SPI Instance
1537 * @param CRCLength This parameter can be one of the following values:
1538 * @arg @ref LL_SPI_CRC_4BIT
1539 * @arg @ref LL_SPI_CRC_5BIT
1540 * @arg @ref LL_SPI_CRC_6BIT
1541 * @arg @ref LL_SPI_CRC_7BIT
1542 * @arg @ref LL_SPI_CRC_8BIT
1543 * @arg @ref LL_SPI_CRC_9BIT
1544 * @arg @ref LL_SPI_CRC_10BIT
1545 * @arg @ref LL_SPI_CRC_11BIT
1546 * @arg @ref LL_SPI_CRC_12BIT
1547 * @arg @ref LL_SPI_CRC_13BIT
1548 * @arg @ref LL_SPI_CRC_14BIT
1549 * @arg @ref LL_SPI_CRC_15BIT
1550 * @arg @ref LL_SPI_CRC_16BIT
1551 * @arg @ref LL_SPI_CRC_17BIT
1552 * @arg @ref LL_SPI_CRC_18BIT
1553 * @arg @ref LL_SPI_CRC_19BIT
1554 * @arg @ref LL_SPI_CRC_20BIT
1555 * @arg @ref LL_SPI_CRC_21BIT
1556 * @arg @ref LL_SPI_CRC_22BIT
1557 * @arg @ref LL_SPI_CRC_23BIT
1558 * @arg @ref LL_SPI_CRC_24BIT
1559 * @arg @ref LL_SPI_CRC_25BIT
1560 * @arg @ref LL_SPI_CRC_26BIT
1561 * @arg @ref LL_SPI_CRC_27BIT
1562 * @arg @ref LL_SPI_CRC_28BIT
1563 * @arg @ref LL_SPI_CRC_29BIT
1564 * @arg @ref LL_SPI_CRC_30BIT
1565 * @arg @ref LL_SPI_CRC_31BIT
1566 * @arg @ref LL_SPI_CRC_32BIT
1567 * @retval None
1568 */
1569__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1570{
1571 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1572}
1573
1574/**
1575 * @brief Get CRC Length
1576 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1577 * @param SPIx SPI Instance
1578 * @retval Returned value can be one of the following values:
1579 * @arg @ref LL_SPI_CRC_4BIT
1580 * @arg @ref LL_SPI_CRC_5BIT
1581 * @arg @ref LL_SPI_CRC_6BIT
1582 * @arg @ref LL_SPI_CRC_7BIT
1583 * @arg @ref LL_SPI_CRC_8BIT
1584 * @arg @ref LL_SPI_CRC_9BIT
1585 * @arg @ref LL_SPI_CRC_10BIT
1586 * @arg @ref LL_SPI_CRC_11BIT
1587 * @arg @ref LL_SPI_CRC_12BIT
1588 * @arg @ref LL_SPI_CRC_13BIT
1589 * @arg @ref LL_SPI_CRC_14BIT
1590 * @arg @ref LL_SPI_CRC_15BIT
1591 * @arg @ref LL_SPI_CRC_16BIT
1592 * @arg @ref LL_SPI_CRC_17BIT
1593 * @arg @ref LL_SPI_CRC_18BIT
1594 * @arg @ref LL_SPI_CRC_19BIT
1595 * @arg @ref LL_SPI_CRC_20BIT
1596 * @arg @ref LL_SPI_CRC_21BIT
1597 * @arg @ref LL_SPI_CRC_22BIT
1598 * @arg @ref LL_SPI_CRC_23BIT
1599 * @arg @ref LL_SPI_CRC_24BIT
1600 * @arg @ref LL_SPI_CRC_25BIT
1601 * @arg @ref LL_SPI_CRC_26BIT
1602 * @arg @ref LL_SPI_CRC_27BIT
1603 * @arg @ref LL_SPI_CRC_28BIT
1604 * @arg @ref LL_SPI_CRC_29BIT
1605 * @arg @ref LL_SPI_CRC_30BIT
1606 * @arg @ref LL_SPI_CRC_31BIT
1607 * @arg @ref LL_SPI_CRC_32BIT
1608 */
1609__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
1610{
1611 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1612}
1613
1614/**
1615 * @brief Set NSS Mode
1616 * @note This configuration can not be changed when SPI is enabled.
1617 * This bit is not used in SPI TI mode.
1618 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1619 * CFG2 SSOE LL_SPI_SetNSSMode
1620 * @param SPIx SPI Instance
1621 * @param NSS This parameter can be one of the following values:
1622 * @arg @ref LL_SPI_NSS_SOFT
1623 * @arg @ref LL_SPI_NSS_HARD_INPUT
1624 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1625 * @retval None
1626 */
1627__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1628{
1629 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1630}
1631
1632/**
1633 * @brief Set NSS Mode
1634 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1635 * CFG2 SSOE LL_SPI_GetNSSMode
1636 * @param SPIx SPI Instance
1637 * @retval Returned value can be one of the following values:
1638 * @arg @ref LL_SPI_NSS_SOFT
1639 * @arg @ref LL_SPI_NSS_HARD_INPUT
1640 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1641 */
1642__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
1643{
1644 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1645}
1646
1647/**
1648 * @brief Enable NSS pulse mgt
1649 * @note This configuration can not be changed when SPI is enabled.
1650 * This bit is not used in SPI TI mode.
1651 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1652 * @param SPIx SPI Instance
1653 * @retval None
1654 */
1655__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1656{
1657 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1658}
1659
1660/**
1661 * @brief Disable NSS pulse mgt
1662 * @note This configuration can not be changed when SPI is enabled.
1663 * This bit is not used in SPI TI mode.
1664 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1665 * @param SPIx SPI Instance
1666 * @retval None
1667 */
1668__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1669{
1670 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1671}
1672
1673/**
1674 * @brief Check if NSS pulse is enabled
1675 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1676 * @param SPIx SPI Instance
1677 * @retval State of bit (1 or 0)
1678 */
1679__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
1680{
1681 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1682}
1683
1684/**
1685 * @}
1686 */
1687
1688/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1689 * @{
1690 */
1691
1692/**
1693 * @brief Check if there is enough data in FIFO to read a full packet
1694 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1695 * @param SPIx SPI Instance
1696 * @retval State of bit (1 or 0)
1697 */
1698__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
1699{
1700 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1701}
1702
1703/**
1704 * @brief Check if there is enough space in FIFO to hold a full packet
1705 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1706 * @param SPIx SPI Instance
1707 * @retval State of bit (1 or 0)
1708 */
1709__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
1710{
1711 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1712}
1713
1714/**
1715 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1716 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1717 * @param SPIx SPI Instance
1718 * @retval State of bit (1 or 0)
1719 */
1720__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
1721{
1722 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1723}
1724
1725/**
1726 * @brief Check that end of transfer event occurred
1727 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1728 * @param SPIx SPI Instance
1729 * @retval State of bit (1 or 0).
1730 */
1731__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
1732{
1733 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1734}
1735
1736/**
1737 * @brief Check that all required data has been filled in the fifo according to transfer size
1738 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1739 * @param SPIx SPI Instance
1740 * @retval State of bit (1 or 0).
1741 */
1742__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
1743{
1744 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1745}
1746
1747/**
1748 * @brief Get Underrun error flag
1749 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1750 * @param SPIx SPI Instance
1751 * @retval State of bit (1 or 0).
1752 */
1753__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1754{
1755 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1756}
1757
1758/**
1759 * @brief Get CRC error flag
1760 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1761 * @param SPIx SPI Instance
1762 * @retval State of bit (1 or 0).
1763 */
1764__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
1765{
1766 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1767}
1768
1769/**
1770 * @brief Get Mode fault error flag
1771 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1772 * @param SPIx SPI Instance
1773 * @retval State of bit (1 or 0).
1774 */
1775__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
1776{
1777 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1778}
1779
1780/**
1781 * @brief Get Overrun error flag
1782 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1783 * @param SPIx SPI Instance
1784 * @retval State of bit (1 or 0).
1785 */
1786__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1787{
1788 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1789}
1790
1791/**
1792 * @brief Get TI Frame format error flag
1793 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1794 * @param SPIx SPI Instance
1795 * @retval State of bit (1 or 0).
1796 */
1797__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1798{
1799 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1800}
1801
1802/**
1803 * @brief Check if the additional number of data has been reloaded
1804 * @rmtoll SR TSERF LL_SPI_IsActiveFlag_TSER
1805 * @param SPIx SPI Instance
1806 * @retval State of bit (1 or 0).
1807 */
1808__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(const SPI_TypeDef *SPIx)
1809{
1810 return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
1811}
1812
1813/**
1814 * @brief Check if a suspend operation is done
1815 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1816 * @param SPIx SPI Instance
1817 * @retval State of bit (1 or 0)
1818 */
1819__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
1820{
1821 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1822}
1823
1824/**
1825 * @brief Check if last TxFIFO or CRC frame transmission is completed
1826 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1827 * @param SPIx SPI Instance
1828 * @retval State of bit (1 or 0).
1829 */
1830__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
1831{
1832 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1833}
1834
1835/**
1836 * @brief Check if at least one 32-bit data is available in RxFIFO
1837 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1838 * @param SPIx SPI Instance
1839 * @retval State of bit (1 or 0)
1840 */
1841__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
1842{
1843 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1844}
1845
1846/**
1847 * @brief Get number of data framed remaining in current TSIZE
1848 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1849 * @param SPIx SPI Instance
1850 * @retval 0..0xFFFF
1851 */
1852__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
1853{
1854 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1855}
1856
1857/**
1858 * @brief Get RxFIFO packing Level
1859 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1860 * @param SPIx SPI Instance
1861 * @retval Returned value can be one of the following values:
1862 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1863 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1864 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1865 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1866 */
1867__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
1868{
1869 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1870}
1871
1872/**
1873 * @brief Clear End Of Transfer flag
1874 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1875 * @param SPIx SPI Instance
1876 * @retval None
1877 */
1878__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1879{
1880 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1881}
1882
1883/**
1884 * @brief Clear TXTF flag
1885 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1886 * @param SPIx SPI Instance
1887 * @retval None
1888 */
1889__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1890{
1891 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1892}
1893
1894/**
1895 * @brief Clear Underrun error flag
1896 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1897 * @param SPIx SPI Instance
1898 * @retval None
1899 */
1900__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1901{
1902 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1903}
1904
1905/**
1906 * @brief Clear Overrun error flag
1907 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1908 * @param SPIx SPI Instance
1909 * @retval None
1910 */
1911__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1912{
1913 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1914}
1915
1916/**
1917 * @brief Clear CRC error flag
1918 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1919 * @param SPIx SPI Instance
1920 * @retval None
1921 */
1922__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1923{
1924 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1925}
1926
1927/**
1928 * @brief Clear Mode fault error flag
1929 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1930 * @param SPIx SPI Instance
1931 * @retval None
1932 */
1933__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1934{
1935 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1936}
1937
1938/**
1939 * @brief Clear Frame format error flag
1940 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1941 * @param SPIx SPI Instance
1942 * @retval None
1943 */
1944__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1945{
1946 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1947}
1948
1949/**
1950 * @brief Clear TSER flag
1951 * @rmtoll IFCR TSERFC LL_SPI_ClearFlag_TSER
1952 * @param SPIx SPI Instance
1953 * @retval None
1954 */
1955__STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)
1956{
1957 SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);
1958}
1959
1960/**
1961 * @brief Clear SUSP flag
1962 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1963 * @param SPIx SPI Instance
1964 * @retval None
1965 */
1966__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1967{
1968 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1969}
1970
1971/**
1972 * @}
1973 */
1974
1975/** @defgroup SPI_LL_EF_IT_Management IT_Management
1976 * @{
1977 */
1978
1979/**
1980 * @brief Enable Rx Packet available IT
1981 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1982 * @param SPIx SPI Instance
1983 * @retval None
1984 */
1985__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1986{
1987 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1988}
1989
1990/**
1991 * @brief Enable Tx Packet space available IT
1992 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1993 * @param SPIx SPI Instance
1994 * @retval None
1995 */
1996__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1997{
1998 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1999}
2000
2001/**
2002 * @brief Enable Duplex Packet available IT
2003 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
2004 * @param SPIx SPI Instance
2005 * @retval None
2006 */
2007__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
2008{
2009 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
2010}
2011
2012/**
2013 * @brief Enable End Of Transfer IT
2014 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
2015 * @param SPIx SPI Instance
2016 * @retval None
2017 */
2018__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
2019{
2020 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
2021}
2022
2023/**
2024 * @brief Enable TXTF IT
2025 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
2026 * @param SPIx SPI Instance
2027 * @retval None
2028 */
2029__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
2030{
2031 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
2032}
2033
2034/**
2035 * @brief Enable Underrun IT
2036 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
2037 * @param SPIx SPI Instance
2038 * @retval None
2039 */
2040__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2041{
2042 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2043}
2044
2045/**
2046 * @brief Enable Overrun IT
2047 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
2048 * @param SPIx SPI Instance
2049 * @retval None
2050 */
2051__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2052{
2053 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2054}
2055
2056/**
2057 * @brief Enable CRC Error IT
2058 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
2059 * @param SPIx SPI Instance
2060 * @retval None
2061 */
2062__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2063{
2064 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2065}
2066
2067/**
2068 * @brief Enable TI Frame Format Error IT
2069 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
2070 * @param SPIx SPI Instance
2071 * @retval None
2072 */
2073__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2074{
2075 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2076}
2077
2078/**
2079 * @brief Enable MODF IT
2080 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
2081 * @param SPIx SPI Instance
2082 * @retval None
2083 */
2084__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2085{
2086 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2087}
2088
2089/**
2090 * @brief Enable TSER reload IT
2091 * @rmtoll IER TSERFIE LL_SPI_EnableIT_TSER
2092 * @param SPIx SPI Instance
2093 * @retval None
2094 */
2095__STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)
2096{
2097 SET_BIT(SPIx->IER, SPI_IER_TSERFIE);
2098}
2099
2100/**
2101 * @brief Disable Rx Packet available IT
2102 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2103 * @param SPIx SPI Instance
2104 * @retval None
2105 */
2106__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2107{
2108 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2109}
2110
2111/**
2112 * @brief Disable Tx Packet space available IT
2113 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2114 * @param SPIx SPI Instance
2115 * @retval None
2116 */
2117__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2118{
2119 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2120}
2121
2122/**
2123 * @brief Disable Duplex Packet available IT
2124 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2125 * @param SPIx SPI Instance
2126 * @retval None
2127 */
2128__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2129{
2130 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2131}
2132
2133/**
2134 * @brief Disable End Of Transfer IT
2135 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2136 * @param SPIx SPI Instance
2137 * @retval None
2138 */
2139__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2140{
2141 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2142}
2143
2144/**
2145 * @brief Disable TXTF IT
2146 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2147 * @param SPIx SPI Instance
2148 * @retval None
2149 */
2150__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2151{
2152 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2153}
2154
2155/**
2156 * @brief Disable Underrun IT
2157 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2158 * @param SPIx SPI Instance
2159 * @retval None
2160 */
2161__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2162{
2163 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2164}
2165
2166/**
2167 * @brief Disable Overrun IT
2168 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2169 * @param SPIx SPI Instance
2170 * @retval None
2171 */
2172__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2173{
2174 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2175}
2176
2177/**
2178 * @brief Disable CRC Error IT
2179 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2180 * @param SPIx SPI Instance
2181 * @retval None
2182 */
2183__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2184{
2185 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2186}
2187
2188/**
2189 * @brief Disable TI Frame Format Error IT
2190 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2191 * @param SPIx SPI Instance
2192 * @retval None
2193 */
2194__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2195{
2196 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2197}
2198
2199/**
2200 * @brief Disable MODF IT
2201 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2202 * @param SPIx SPI Instance
2203 * @retval None
2204 */
2205__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2206{
2207 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2208}
2209
2210/**
2211 * @brief Disable TSER reload IT
2212 * @rmtoll IER TSERFIE LL_SPI_DisableIT_TSER
2213 * @param SPIx SPI Instance
2214 * @retval None
2215 */
2216__STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
2217{
2218 CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);
2219}
2220
2221/**
2222 * @brief Check if Rx Packet available IT is enabled
2223 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2224 * @param SPIx SPI Instance
2225 * @retval State of bit (1 or 0)
2226 */
2227__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
2228{
2229 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2230}
2231
2232/**
2233 * @brief Check if Tx Packet space available IT is enabled
2234 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2235 * @param SPIx SPI Instance
2236 * @retval State of bit (1 or 0)
2237 */
2238__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
2239{
2240 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2241}
2242
2243/**
2244 * @brief Check if Duplex Packet available IT is enabled
2245 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2246 * @param SPIx SPI Instance
2247 * @retval State of bit (1 or 0)
2248 */
2249__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
2250{
2251 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2252}
2253
2254/**
2255 * @brief Check if End Of Transfer IT is enabled
2256 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2257 * @param SPIx SPI Instance
2258 * @retval State of bit (1 or 0)
2259 */
2260__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
2261{
2262 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2263}
2264
2265/**
2266 * @brief Check if TXTF IT is enabled
2267 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2268 * @param SPIx SPI Instance
2269 * @retval State of bit (1 or 0)
2270 */
2271__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
2272{
2273 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2274}
2275
2276/**
2277 * @brief Check if Underrun IT is enabled
2278 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2279 * @param SPIx SPI Instance
2280 * @retval State of bit (1 or 0)
2281 */
2282__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
2283{
2284 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2285}
2286
2287/**
2288 * @brief Check if Overrun IT is enabled
2289 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2290 * @param SPIx SPI Instance
2291 * @retval State of bit (1 or 0)
2292 */
2293__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
2294{
2295 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2296}
2297
2298/**
2299 * @brief Check if CRC Error IT is enabled
2300 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2301 * @param SPIx SPI Instance
2302 * @retval State of bit (1 or 0)
2303 */
2304__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
2305{
2306 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2307}
2308
2309/**
2310 * @brief Check if TI Frame Format Error IT is enabled
2311 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2312 * @param SPIx SPI Instance
2313 * @retval State of bit (1 or 0)
2314 */
2315__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
2316{
2317 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2318}
2319
2320/**
2321 * @brief Check if MODF IT is enabled
2322 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2323 * @param SPIx SPI Instance
2324 * @retval State of bit (1 or 0)
2325 */
2326__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
2327{
2328 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2329}
2330
2331/**
2332 * @brief Check if TSER reload IT is enabled
2333 * @rmtoll IER TSERFIE LL_SPI_IsEnabledIT_TSER
2334 * @param SPIx SPI Instance
2335 * @retval State of bit (1 or 0)
2336 */
2337__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(const SPI_TypeDef *SPIx)
2338{
2339 return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
2340}
2341
2342/**
2343 * @}
2344 */
2345
2346/** @defgroup SPI_LL_EF_DMA_Management DMA Management
2347 * @{
2348 */
2349
2350/**
2351 * @brief Enable DMA Rx
2352 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2353 * @param SPIx SPI Instance
2354 * @retval None
2355 */
2356__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2357{
2358 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2359}
2360
2361/**
2362 * @brief Disable DMA Rx
2363 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2364 * @param SPIx SPI Instance
2365 * @retval None
2366 */
2367__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2368{
2369 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2370}
2371
2372/**
2373 * @brief Check if DMA Rx is enabled
2374 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2375 * @param SPIx SPI Instance
2376 * @retval State of bit (1 or 0)
2377 */
2378__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
2379{
2380 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2381}
2382
2383/**
2384 * @brief Enable DMA Tx
2385 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2386 * @param SPIx SPI Instance
2387 * @retval None
2388 */
2389__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2390{
2391 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2392}
2393
2394/**
2395 * @brief Disable DMA Tx
2396 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2397 * @param SPIx SPI Instance
2398 * @retval None
2399 */
2400__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2401{
2402 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2403}
2404
2405/**
2406 * @brief Check if DMA Tx is enabled
2407 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2408 * @param SPIx SPI Instance
2409 * @retval State of bit (1 or 0)
2410 */
2411__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
2412{
2413 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2414}
2415/**
2416 * @brief Get the data register address used for DMA transfer
2417 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2418 * @param SPIx SPI Instance
2419 * @retval Address of data register
2420 */
2421__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
2422{
2423 return (uint32_t) &(SPIx->TXDR);
2424}
2425
2426/**
2427 * @brief Get the data register address used for DMA transfer
2428 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2429 * @param SPIx SPI Instance
2430 * @retval Address of data register
2431 */
2432__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
2433{
2434 return (uint32_t) &(SPIx->RXDR);
2435}
2436/**
2437 * @}
2438 */
2439
2440/** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2441 * @{
2442 */
2443
2444/**
2445 * @brief Read Data Register
2446 * @rmtoll RXDR . LL_SPI_ReceiveData8
2447 * @param SPIx SPI Instance
2448 * @retval 0..0xFF
2449 */
2450__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2451{
2452 return (*((__IO uint8_t *)&SPIx->RXDR));
2453}
2454
2455/**
2456 * @brief Read Data Register
2457 * @rmtoll RXDR . LL_SPI_ReceiveData16
2458 * @param SPIx SPI Instance
2459 * @retval 0..0xFFFF
2460 */
2461__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2462{
2463#if defined (__GNUC__)
2464 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2465 return (*spirxdr);
2466#else
2467 return (*((__IO uint16_t *)&SPIx->RXDR));
2468#endif /* __GNUC__ */
2469}
2470
2471/**
2472 * @brief Read Data Register
2473 * @rmtoll RXDR . LL_SPI_ReceiveData32
2474 * @param SPIx SPI Instance
2475 * @retval 0..0xFFFFFFFF
2476 */
2477__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2478{
2479 return (*((__IO uint32_t *)&SPIx->RXDR));
2480}
2481
2482/**
2483 * @brief Write Data Register
2484 * @rmtoll TXDR . LL_SPI_TransmitData8
2485 * @param SPIx SPI Instance
2486 * @param TxData 0..0xFF
2487 * @retval None
2488 */
2489__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2490{
2491 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2492}
2493
2494/**
2495 * @brief Write Data Register
2496 * @rmtoll TXDR . LL_SPI_TransmitData16
2497 * @param SPIx SPI Instance
2498 * @param TxData 0..0xFFFF
2499 * @retval None
2500 */
2501__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2502{
2503#if defined (__GNUC__)
2504 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2505 *spitxdr = TxData;
2506#else
2507 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2508#endif /* __GNUC__ */
2509}
2510
2511/**
2512 * @brief Write Data Register
2513 * @rmtoll TXDR . LL_SPI_TransmitData32
2514 * @param SPIx SPI Instance
2515 * @param TxData 0..0xFFFFFFFF
2516 * @retval None
2517 */
2518__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2519{
2520 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2521}
2522
2523/**
2524 * @brief Set polynomial for CRC calcul
2525 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2526 * @param SPIx SPI Instance
2527 * @param CRCPoly 0..0xFFFFFFFF
2528 * @retval None
2529 */
2530__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2531{
2532 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2533}
2534
2535/**
2536 * @brief Get polynomial for CRC calcul
2537 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2538 * @param SPIx SPI Instance
2539 * @retval 0..0xFFFFFFFF
2540 */
2541__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
2542{
2543 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2544}
2545
2546/**
2547 * @brief Set the underrun pattern
2548 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2549 * @param SPIx SPI Instance
2550 * @param Pattern 0..0xFFFFFFFF
2551 * @retval None
2552 */
2553__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2554{
2555 WRITE_REG(SPIx->UDRDR, Pattern);
2556}
2557
2558/**
2559 * @brief Get the underrun pattern
2560 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2561 * @param SPIx SPI Instance
2562 * @retval 0..0xFFFFFFFF
2563 */
2564__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
2565{
2566 return (uint32_t)(READ_REG(SPIx->UDRDR));
2567}
2568
2569/**
2570 * @brief Get Rx CRC
2571 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2572 * @param SPIx SPI Instance
2573 * @retval 0..0xFFFFFFFF
2574 */
2575__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
2576{
2577 return (uint32_t)(READ_REG(SPIx->RXCRC));
2578}
2579
2580/**
2581 * @brief Get Tx CRC
2582 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2583 * @param SPIx SPI Instance
2584 * @retval 0..0xFFFFFFFF
2585 */
2586__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
2587{
2588 return (uint32_t)(READ_REG(SPIx->TXCRC));
2589}
2590
2591/**
2592 * @}
2593 */
2594
2595#if defined(USE_FULL_LL_DRIVER)
2596/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2597 * @{
2598 */
2599
2600ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
2601ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2602void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2603
2604/**
2605 * @}
2606 */
2607#endif /* USE_FULL_LL_DRIVER */
2608/**
2609 * @}
2610 */
2611/**
2612 * @}
2613 */
2614
2615/** @defgroup I2S_LL I2S
2616 * @{
2617 */
2618
2619/* Private variables ---------------------------------------------------------*/
2620/* Private constants ---------------------------------------------------------*/
2621/* Private macros ------------------------------------------------------------*/
2622
2623/* Exported types ------------------------------------------------------------*/
2624#if defined(USE_FULL_LL_DRIVER)
2625/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
2626 * @{
2627 */
2628
2629/**
2630 * @brief I2S Init structure definition
2631 */
2632
2633typedef struct
2634{
2635 uint32_t Mode; /*!< Specifies the I2S operating mode.
2636 This parameter can be a value of @ref I2S_LL_EC_MODE
2637
2638 This feature can be modified afterwards using unitary function
2639 @ref LL_I2S_SetTransferMode().*/
2640
2641 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
2642 This parameter can be a value of @ref I2S_LL_EC_STANDARD
2643
2644 This feature can be modified afterwards using unitary function
2645 @ref LL_I2S_SetStandard().*/
2646
2647
2648 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
2649 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
2650
2651 This feature can be modified afterwards using unitary function
2652 @ref LL_I2S_SetDataFormat().*/
2653
2654
2655 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
2656 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
2657
2658 This feature can be modified afterwards using unitary functions
2659 @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
2660
2661
2662 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
2663 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
2664
2665 Audio Frequency can be modified afterwards using Reference manual formulas
2666 to calculate Prescaler Linear, Parity and unitary functions
2667 @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
2668 to set it.*/
2669
2670
2671 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
2672 This parameter can be a value of @ref I2S_LL_EC_POLARITY
2673
2674 This feature can be modified afterwards using unitary function
2675 @ref LL_I2S_SetClockPolarity().*/
2676
2677} LL_I2S_InitTypeDef;
2678
2679/**
2680 * @}
2681 */
2682#endif /*USE_FULL_LL_DRIVER*/
2683
2684/* Exported constants --------------------------------------------------------*/
2685/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
2686 * @{
2687 */
2688
2689/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
2690 * @{
2691 */
2692#define LL_I2S_DATAFORMAT_16B (0x00000000UL)
2693#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
2694#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
2695#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
2696#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
2697/**
2698 * @}
2699 */
2700
2701/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
2702 * @{
2703 */
2704#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
2705#define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
2706/**
2707 * @}
2708 */
2709
2710/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
2711 * @{
2712 */
2713#define LL_I2S_POLARITY_LOW (0x00000000UL)
2714#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
2715/**
2716 * @}
2717 */
2718
2719/** @defgroup I2S_LL_EC_STANDARD I2S Standard
2720 * @{
2721 */
2722#define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
2723#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
2724#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
2725#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
2726#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
2727/**
2728 * @}
2729 */
2730
2731/** @defgroup I2S_LL_EC_MODE Operation Mode
2732 * @{
2733 */
2734#define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
2735#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
2736#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
2737#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
2738#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
2739#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
2740/**
2741 * @}
2742 */
2743
2744/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
2745 * @{
2746 */
2747#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
2748#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
2749/**
2750 * @}
2751 */
2752
2753/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
2754 * @{
2755 */
2756#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
2757#define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
2758#define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
2759#define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
2760#define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
2761#define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
2762#define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
2763#define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
2764/**
2765 * @}
2766 */
2767
2768/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
2769 * @{
2770 */
2771#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
2772#define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
2773/**
2774 * @}
2775 */
2776
2777#if defined(USE_FULL_LL_DRIVER)
2778
2779/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
2780 * @{
2781 */
2782#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
2783#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
2784/**
2785 * @}
2786 */
2787
2788/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
2789 * @{
2790 */
2791
2792#define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */
2793#define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */
2794#define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */
2795#define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */
2796#define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */
2797#define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */
2798#define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */
2799#define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */
2800#define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */
2801#define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */
2802/**
2803 * @}
2804 */
2805#endif /* USE_FULL_LL_DRIVER */
2806
2807/**
2808 * @}
2809 */
2810
2811/* Exported macro ------------------------------------------------------------*/
2812/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
2813 * @{
2814 */
2815
2816/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
2817 * @{
2818 */
2819
2820/**
2821 * @brief Write a value in I2S register
2822 * @param __INSTANCE__ I2S Instance
2823 * @param __REG__ Register to be written
2824 * @param __VALUE__ Value to be written in the register
2825 * @retval None
2826 */
2827#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2828
2829/**
2830 * @brief Read a value in I2S register
2831 * @param __INSTANCE__ I2S Instance
2832 * @param __REG__ Register to be read
2833 * @retval Register value
2834 */
2835#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2836/**
2837 * @}
2838 */
2839
2840/**
2841 * @}
2842 */
2843
2844
2845/* Exported functions --------------------------------------------------------*/
2846
2847/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
2848 * @{
2849 */
2850
2851/** @defgroup I2S_LL_EF_Configuration Configuration
2852 * @{
2853 */
2854
2855/**
2856 * @brief Set I2S Data frame format
2857 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
2858 * I2SCFGR CHLEN LL_I2S_SetDataFormat\n
2859 * I2SCFGR DATFMT LL_I2S_SetDataFormat
2860 * @param SPIx SPI Handle
2861 * @param DataLength This parameter can be one of the following values:
2862 * @arg @ref LL_I2S_DATAFORMAT_16B
2863 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2864 * @arg @ref LL_I2S_DATAFORMAT_24B
2865 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2866 * @arg @ref LL_I2S_DATAFORMAT_32B
2867 * @retval None
2868 */
2869__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
2870{
2871 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
2872}
2873
2874/**
2875 * @brief Get I2S Data frame format
2876 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
2877 * I2SCFGR CHLEN LL_I2S_GetDataFormat\n
2878 * I2SCFGR DATFMT LL_I2S_GetDataFormat
2879 * @param SPIx SPI Handle
2880 * @retval Return value can be one of the following values:
2881 * @arg @ref LL_I2S_DATAFORMAT_16B
2882 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2883 * @arg @ref LL_I2S_DATAFORMAT_24B
2884 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2885 * @arg @ref LL_I2S_DATAFORMAT_32B
2886 */
2887__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
2888{
2889 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
2890}
2891
2892/**
2893 * @brief Set I2S Channel Length Type
2894 * @note This feature is useful with SLAVE only
2895 * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
2896 * @param SPIx SPI Handle
2897 * @param ChannelLengthType This parameter can be one of the following values:
2898 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2899 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2900 * @retval None
2901 */
2902__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
2903{
2904 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
2905}
2906
2907/**
2908 * @brief Get I2S Channel Length Type
2909 * @note This feature is useful with SLAVE only
2910 * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
2911 * @param SPIx SPI Handle
2912 * @retval Return value can be one of the following values:
2913 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2914 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2915 */
2916__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx)
2917{
2918 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
2919}
2920
2921/**
2922 * @brief Invert the default polarity of WS signal
2923 * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
2924 * @param SPIx SPI Handle
2925 * @retval None
2926 */
2927__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
2928{
2929 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2930}
2931
2932/**
2933 * @brief Use the default polarity of WS signal
2934 * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
2935 * @param SPIx SPI Handle
2936 * @retval None
2937 */
2938__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
2939{
2940 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2941}
2942
2943/**
2944 * @brief Check if polarity of WS signal is inverted
2945 * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
2946 * @param SPIx SPI Handle
2947 * @retval State of bit (1 or 0)
2948 */
2949__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx)
2950{
2951 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
2952}
2953
2954/**
2955 * @brief Set 2S Clock Polarity
2956 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
2957 * @param SPIx SPI Handle
2958 * @param ClockPolarity This parameter can be one of the following values:
2959 * @arg @ref LL_I2S_POLARITY_LOW
2960 * @arg @ref LL_I2S_POLARITY_HIGH
2961 * @retval None
2962 */
2963__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
2964{
2965 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
2966}
2967
2968/**
2969 * @brief Get 2S Clock Polarity
2970 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
2971 * @param SPIx SPI Handle
2972 * @retval Return value can be one of the following values:
2973 * @arg @ref LL_I2S_POLARITY_LOW
2974 * @arg @ref LL_I2S_POLARITY_HIGH
2975 */
2976__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
2977{
2978 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
2979}
2980
2981/**
2982 * @brief Set I2S standard
2983 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
2984 * I2SCFGR PCMSYNC LL_I2S_SetStandard
2985 * @param SPIx SPI Handle
2986 * @param Standard This parameter can be one of the following values:
2987 * @arg @ref LL_I2S_STANDARD_PHILIPS
2988 * @arg @ref LL_I2S_STANDARD_MSB
2989 * @arg @ref LL_I2S_STANDARD_LSB
2990 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2991 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2992 * @retval None
2993 */
2994__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
2995{
2996 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
2997}
2998
2999/**
3000 * @brief Get I2S standard
3001 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
3002 * I2SCFGR PCMSYNC LL_I2S_GetStandard
3003 * @param SPIx SPI Handle
3004 * @retval Return value can be one of the following values:
3005 * @arg @ref LL_I2S_STANDARD_PHILIPS
3006 * @arg @ref LL_I2S_STANDARD_MSB
3007 * @arg @ref LL_I2S_STANDARD_LSB
3008 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
3009 * @arg @ref LL_I2S_STANDARD_PCM_LONG
3010 */
3011__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
3012{
3013 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
3014}
3015
3016/**
3017 * @brief Set I2S config
3018 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
3019 * @param SPIx SPI Handle
3020 * @param Standard This parameter can be one of the following values:
3021 * @arg @ref LL_I2S_MODE_SLAVE_TX
3022 * @arg @ref LL_I2S_MODE_SLAVE_RX
3023 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
3024 * @arg @ref LL_I2S_MODE_MASTER_TX
3025 * @arg @ref LL_I2S_MODE_MASTER_RX
3026 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
3027 * @retval None
3028 */
3029__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
3030{
3031 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
3032}
3033
3034/**
3035 * @brief Get I2S config
3036 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
3037 * @param SPIx SPI Handle
3038 * @retval Return value can be one of the following values:
3039 * @arg @ref LL_I2S_MODE_SLAVE_TX
3040 * @arg @ref LL_I2S_MODE_SLAVE_RX
3041 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
3042 * @arg @ref LL_I2S_MODE_MASTER_TX
3043 * @arg @ref LL_I2S_MODE_MASTER_RX
3044 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
3045 */
3046__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
3047{
3048 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
3049}
3050
3051/**
3052 * @brief Select I2S mode and Enable I2S peripheral
3053 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
3054 * CR1 SPE LL_I2S_Enable
3055 * @param SPIx SPI Handle
3056 * @retval None
3057 */
3058__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
3059{
3060 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3061 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
3062}
3063
3064/**
3065 * @brief Disable I2S peripheral and disable I2S mode
3066 * @rmtoll CR1 SPE LL_I2S_Disable\n
3067 * I2SCFGR I2SMOD LL_I2S_Disable
3068 * @param SPIx SPI Handle
3069 * @retval None
3070 */
3071__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
3072{
3073 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
3074 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3075}
3076
3077/**
3078 * @brief Swap the SDO and SDI pin
3079 * @note This configuration can not be changed when I2S is enabled.
3080 * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap
3081 * @param SPIx SPI Instance
3082 * @retval None
3083 */
3084__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
3085{
3086 LL_SPI_EnableIOSwap(SPIx);
3087}
3088
3089/**
3090 * @brief Restore default function for SDO and SDI pin
3091 * @note This configuration can not be changed when I2S is enabled.
3092 * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap
3093 * @param SPIx SPI Instance
3094 * @retval None
3095 */
3096__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
3097{
3098 LL_SPI_DisableIOSwap(SPIx);
3099}
3100
3101/**
3102 * @brief Check if SDO and SDI pin are swapped
3103 * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap
3104 * @param SPIx SPI Instance
3105 * @retval State of bit (1 or 0)
3106 */
3107__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
3108{
3109 return LL_SPI_IsEnabledIOSwap(SPIx);
3110}
3111
3112/**
3113 * @brief Enable GPIO control
3114 * @note This configuration can not be changed when I2S is enabled.
3115 * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl
3116 * @param SPIx SPI Instance
3117 * @retval None
3118 */
3119__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
3120{
3121 LL_SPI_EnableGPIOControl(SPIx);
3122}
3123
3124/**
3125 * @brief Disable GPIO control
3126 * @note This configuration can not be changed when I2S is enabled.
3127 * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl
3128 * @param SPIx SPI Instance
3129 * @retval None
3130 */
3131__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
3132{
3133 LL_SPI_DisableGPIOControl(SPIx);
3134}
3135
3136/**
3137 * @brief Check if GPIO control is active
3138 * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
3139 * @param SPIx SPI Instance
3140 * @retval State of bit (1 or 0)
3141 */
3142__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
3143{
3144 return LL_SPI_IsEnabledGPIOControl(SPIx);
3145}
3146
3147/**
3148 * @brief Lock the AF configuration of associated IOs
3149 * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
3150 * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
3151 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
3152 * @param SPIx SPI Instance
3153 * @retval None
3154 */
3155__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
3156{
3157 LL_SPI_EnableIOLock(SPIx);
3158}
3159
3160/**
3161 * @brief Check if the the SPI_CFG2 register is locked
3162 * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock
3163 * @param SPIx SPI Instance
3164 * @retval State of bit (1 or 0)
3165 */
3166__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx)
3167{
3168 return LL_SPI_IsEnabledIOLock(SPIx);
3169}
3170
3171/**
3172 * @brief Set Transfer Bit Order
3173 * @note This configuration can not be changed when I2S is enabled.
3174 * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder
3175 * @param SPIx SPI Instance
3176 * @param BitOrder This parameter can be one of the following values:
3177 * @arg @ref LL_I2S_LSB_FIRST
3178 * @arg @ref LL_I2S_MSB_FIRST
3179 * @retval None
3180 */
3181__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
3182{
3183 LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
3184}
3185/**
3186 * @brief Get Transfer Bit Order
3187 * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder
3188 * @param SPIx SPI Instance
3189 * @retval Returned value can be one of the following values:
3190 * @arg @ref LL_I2S_LSB_FIRST
3191 * @arg @ref LL_I2S_MSB_FIRST
3192 */
3193__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx)
3194{
3195 return LL_SPI_GetTransferBitOrder(SPIx);
3196}
3197
3198/**
3199 * @brief Start effective transfer on wire
3200 * @rmtoll CR1 CSTART LL_I2S_StartTransfer
3201 * @param SPIx SPI Instance
3202 * @retval None
3203 */
3204__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
3205{
3206 LL_SPI_StartMasterTransfer(SPIx);
3207}
3208
3209/**
3210 * @brief Check if there is an unfinished transfer
3211 * @rmtoll CR1 CSTART LL_I2S_IsActiveTransfer
3212 * @param SPIx SPI Instance
3213 * @retval State of bit (1 or 0)
3214 */
3215__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx)
3216{
3217 return LL_SPI_IsActiveMasterTransfer(SPIx);
3218}
3219
3220/**
3221 * @brief Set threshold of FIFO that triggers a transfer event
3222 * @note This configuration can not be changed when I2S is enabled.
3223 * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold
3224 * @param SPIx SPI Instance
3225 * @param Threshold This parameter can be one of the following values:
3226 * @arg @ref LL_I2S_FIFO_TH_01DATA
3227 * @arg @ref LL_I2S_FIFO_TH_02DATA
3228 * @arg @ref LL_I2S_FIFO_TH_03DATA
3229 * @arg @ref LL_I2S_FIFO_TH_04DATA
3230 * @arg @ref LL_I2S_FIFO_TH_05DATA
3231 * @arg @ref LL_I2S_FIFO_TH_06DATA
3232 * @arg @ref LL_I2S_FIFO_TH_07DATA
3233 * @arg @ref LL_I2S_FIFO_TH_08DATA
3234 * @retval None
3235 */
3236__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
3237{
3238 LL_SPI_SetFIFOThreshold(SPIx, Threshold);
3239}
3240
3241/**
3242 * @brief Get threshold of FIFO that triggers a transfer event
3243 * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold
3244 * @param SPIx SPI Instance
3245 * @retval Returned value can be one of the following values:
3246 * @arg @ref LL_I2S_FIFO_TH_01DATA
3247 * @arg @ref LL_I2S_FIFO_TH_02DATA
3248 * @arg @ref LL_I2S_FIFO_TH_03DATA
3249 * @arg @ref LL_I2S_FIFO_TH_04DATA
3250 * @arg @ref LL_I2S_FIFO_TH_05DATA
3251 * @arg @ref LL_I2S_FIFO_TH_06DATA
3252 * @arg @ref LL_I2S_FIFO_TH_07DATA
3253 * @arg @ref LL_I2S_FIFO_TH_08DATA
3254 */
3255__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx)
3256{
3257 return LL_SPI_GetFIFOThreshold(SPIx);
3258}
3259
3260/**
3261 * @brief Set I2S linear prescaler
3262 * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
3263 * @param SPIx SPI Instance
3264 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3265 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
3266 * @retval None
3267 */
3268__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
3269{
3270 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
3271}
3272
3273/**
3274 * @brief Get I2S linear prescaler
3275 * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
3276 * @param SPIx SPI Instance
3277 * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3278 */
3279__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
3280{
3281 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
3282}
3283
3284/**
3285 * @brief Set I2S parity prescaler
3286 * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity
3287 * @param SPIx SPI Instance
3288 * @param PrescalerParity This parameter can be one of the following values:
3289 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3290 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3291 * @retval None
3292 */
3293__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
3294{
3295 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
3296}
3297
3298/**
3299 * @brief Get I2S parity prescaler
3300 * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity
3301 * @param SPIx SPI Instance
3302 * @retval Returned value can be one of the following values:
3303 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3304 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3305 */
3306__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
3307{
3308 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
3309}
3310
3311/**
3312 * @brief Enable the Master Clock Output (Pin MCK)
3313 * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock
3314 * @param SPIx SPI Handle
3315 * @retval None
3316 */
3317__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
3318{
3319 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3320}
3321
3322/**
3323 * @brief Disable the Master Clock Output (Pin MCK)
3324 * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
3325 * @param SPIx SPI Handle
3326 * @retval None
3327 */
3328__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
3329{
3330 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3331}
3332
3333/**
3334 * @brief Check if the master clock output (Pin MCK) is enabled
3335 * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
3336 * @param SPIx SPI Instance
3337 * @retval State of bit (1 or 0)
3338 */
3339__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
3340{
3341 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
3342}
3343
3344/**
3345 * @}
3346 */
3347
3348
3349/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
3350 * @{
3351 */
3352
3353/**
3354 * @brief Check if there enough data in FIFO to read a full packet
3355 * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP
3356 * @param SPIx SPI Instance
3357 * @retval State of bit (1 or 0)
3358 */
3359__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
3360{
3361 return LL_SPI_IsActiveFlag_RXP(SPIx);
3362}
3363
3364/**
3365 * @brief Check if there enough space in FIFO to hold a full packet
3366 * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP
3367 * @param SPIx SPI Instance
3368 * @retval State of bit (1 or 0)
3369 */
3370__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
3371{
3372 return LL_SPI_IsActiveFlag_TXP(SPIx);
3373}
3374
3375/**
3376 * @brief Get Underrun error flag
3377 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
3378 * @param SPIx SPI Instance
3379 * @retval State of bit (1 or 0)
3380 */
3381__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
3382{
3383 return LL_SPI_IsActiveFlag_UDR(SPIx);
3384}
3385
3386/**
3387 * @brief Get Overrun error flag
3388 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
3389 * @param SPIx SPI Instance
3390 * @retval State of bit (1 or 0).
3391 */
3392__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
3393{
3394 return LL_SPI_IsActiveFlag_OVR(SPIx);
3395}
3396
3397/**
3398 * @brief Get TI Frame format error flag
3399 * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE
3400 * @param SPIx SPI Instance
3401 * @retval State of bit (1 or 0).
3402 */
3403__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
3404{
3405 return LL_SPI_IsActiveFlag_FRE(SPIx);
3406}
3407
3408/**
3409 * @brief Clear Underrun error flag
3410 * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR
3411 * @param SPIx SPI Instance
3412 * @retval None
3413 */
3414__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
3415{
3416 LL_SPI_ClearFlag_UDR(SPIx);
3417}
3418
3419/**
3420 * @brief Clear Overrun error flag
3421 * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR
3422 * @param SPIx SPI Instance
3423 * @retval None
3424 */
3425__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
3426{
3427 LL_SPI_ClearFlag_OVR(SPIx);
3428}
3429
3430/**
3431 * @brief Clear Frame format error flag
3432 * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE
3433 * @param SPIx SPI Instance
3434 * @retval None
3435 */
3436__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
3437{
3438 LL_SPI_ClearFlag_FRE(SPIx);
3439}
3440
3441/**
3442 * @}
3443 */
3444
3445/** @defgroup I2S_LL_EF_IT_Management IT_Management
3446 * @{
3447 */
3448
3449/**
3450 * @brief Enable Rx Packet available IT
3451 * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP
3452 * @param SPIx SPI Instance
3453 * @retval None
3454 */
3455__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
3456{
3457 LL_SPI_EnableIT_RXP(SPIx);
3458}
3459
3460/**
3461 * @brief Enable Tx Packet space available IT
3462 * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP
3463 * @param SPIx SPI Instance
3464 * @retval None
3465 */
3466__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
3467{
3468 LL_SPI_EnableIT_TXP(SPIx);
3469}
3470
3471/**
3472 * @brief Enable Underrun IT
3473 * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR
3474 * @param SPIx SPI Instance
3475 * @retval None
3476 */
3477__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
3478{
3479 LL_SPI_EnableIT_UDR(SPIx);
3480}
3481
3482/**
3483 * @brief Enable Overrun IT
3484 * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR
3485 * @param SPIx SPI Instance
3486 * @retval None
3487 */
3488__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
3489{
3490 LL_SPI_EnableIT_OVR(SPIx);
3491}
3492
3493/**
3494 * @brief Enable TI Frame Format Error IT
3495 * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE
3496 * @param SPIx SPI Instance
3497 * @retval None
3498 */
3499__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
3500{
3501 LL_SPI_EnableIT_FRE(SPIx);
3502}
3503
3504/**
3505 * @brief Disable Rx Packet available IT
3506 * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP
3507 * @param SPIx SPI Instance
3508 * @retval None
3509 */
3510__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
3511{
3512 LL_SPI_DisableIT_RXP(SPIx);
3513}
3514
3515/**
3516 * @brief Disable Tx Packet space available IT
3517 * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP
3518 * @param SPIx SPI Instance
3519 * @retval None
3520 */
3521__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
3522{
3523 LL_SPI_DisableIT_TXP(SPIx);
3524}
3525
3526/**
3527 * @brief Disable Underrun IT
3528 * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR
3529 * @param SPIx SPI Instance
3530 * @retval None
3531 */
3532__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
3533{
3534 LL_SPI_DisableIT_UDR(SPIx);
3535}
3536
3537/**
3538 * @brief Disable Overrun IT
3539 * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR
3540 * @param SPIx SPI Instance
3541 * @retval None
3542 */
3543__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
3544{
3545 LL_SPI_DisableIT_OVR(SPIx);
3546}
3547
3548/**
3549 * @brief Disable TI Frame Format Error IT
3550 * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE
3551 * @param SPIx SPI Instance
3552 * @retval None
3553 */
3554__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
3555{
3556 LL_SPI_DisableIT_FRE(SPIx);
3557}
3558
3559/**
3560 * @brief Check if Rx Packet available IT is enabled
3561 * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP
3562 * @param SPIx SPI Instance
3563 * @retval State of bit (1 or 0)
3564 */
3565__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
3566{
3567 return LL_SPI_IsEnabledIT_RXP(SPIx);
3568}
3569
3570/**
3571 * @brief Check if Tx Packet space available IT is enabled
3572 * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP
3573 * @param SPIx SPI Instance
3574 * @retval State of bit (1 or 0)
3575 */
3576__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
3577{
3578 return LL_SPI_IsEnabledIT_TXP(SPIx);
3579}
3580
3581/**
3582 * @brief Check if Underrun IT is enabled
3583 * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR
3584 * @param SPIx SPI Instance
3585 * @retval State of bit (1 or 0)
3586 */
3587__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
3588{
3589 return LL_SPI_IsEnabledIT_UDR(SPIx);
3590}
3591
3592/**
3593 * @brief Check if Overrun IT is enabled
3594 * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR
3595 * @param SPIx SPI Instance
3596 * @retval State of bit (1 or 0)
3597 */
3598__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
3599{
3600 return LL_SPI_IsEnabledIT_OVR(SPIx);
3601}
3602
3603/**
3604 * @brief Check if TI Frame Format Error IT is enabled
3605 * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE
3606 * @param SPIx SPI Instance
3607 * @retval State of bit (1 or 0)
3608 */
3609__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
3610{
3611 return LL_SPI_IsEnabledIT_FRE(SPIx);
3612}
3613
3614/**
3615 * @}
3616 */
3617
3618/** @defgroup I2S_LL_EF_DMA_Management DMA_Management
3619 * @{
3620 */
3621
3622/**
3623 * @brief Enable DMA Rx
3624 * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
3625 * @param SPIx SPI Instance
3626 * @retval None
3627 */
3628__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
3629{
3630 LL_SPI_EnableDMAReq_RX(SPIx);
3631}
3632
3633/**
3634 * @brief Disable DMA Rx
3635 * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
3636 * @param SPIx SPI Instance
3637 * @retval None
3638 */
3639__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
3640{
3641 LL_SPI_DisableDMAReq_RX(SPIx);
3642}
3643
3644/**
3645 * @brief Check if DMA Rx is enabled
3646 * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
3647 * @param SPIx SPI Instance
3648 * @retval State of bit (1 or 0)
3649 */
3650__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
3651{
3652 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
3653}
3654
3655/**
3656 * @brief Enable DMA Tx
3657 * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
3658 * @param SPIx SPI Instance
3659 * @retval None
3660 */
3661__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
3662{
3663 LL_SPI_EnableDMAReq_TX(SPIx);
3664}
3665
3666/**
3667 * @brief Disable DMA Tx
3668 * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
3669 * @param SPIx SPI Instance
3670 * @retval None
3671 */
3672__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
3673{
3674 LL_SPI_DisableDMAReq_TX(SPIx);
3675}
3676
3677/**
3678 * @brief Check if DMA Tx is enabled
3679 * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
3680 * @param SPIx SPI Instance
3681 * @retval State of bit (1 or 0)
3682 */
3683__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
3684{
3685 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
3686}
3687
3688/**
3689 * @}
3690 */
3691
3692/** @defgroup I2S_LL_EF_DATA_Management DATA_Management
3693 * @{
3694 */
3695
3696/**
3697 * @brief Read Data Register
3698 * @rmtoll RXDR . LL_I2S_ReceiveData16
3699 * @param SPIx SPI Instance
3700 * @retval 0..0xFFFF
3701 */
3702__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
3703{
3704 return LL_SPI_ReceiveData16(SPIx);
3705}
3706
3707/**
3708 * @brief Read Data Register
3709 * @rmtoll RXDR . LL_I2S_ReceiveData32
3710 * @param SPIx SPI Instance
3711 * @retval 0..0xFFFFFFFF
3712 */
3713__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
3714{
3715 return LL_SPI_ReceiveData32(SPIx);
3716}
3717
3718/**
3719 * @brief Write Data Register
3720 * @rmtoll TXDR . LL_I2S_TransmitData16
3721 * @param SPIx SPI Instance
3722 * @param TxData 0..0xFFFF
3723 * @retval None
3724 */
3725__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
3726{
3727 LL_SPI_TransmitData16(SPIx, TxData);
3728}
3729
3730/**
3731 * @brief Write Data Register
3732 * @rmtoll TXDR . LL_I2S_TransmitData32
3733 * @param SPIx SPI Instance
3734 * @param TxData 0..0xFFFFFFFF
3735 * @retval None
3736 */
3737__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
3738{
3739 LL_SPI_TransmitData32(SPIx, TxData);
3740}
3741
3742
3743/**
3744 * @}
3745 */
3746
3747
3748#if defined(USE_FULL_LL_DRIVER)
3749/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
3750 * @{
3751 */
3752
3753ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
3754ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
3755void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
3756void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
3757
3758/**
3759 * @}
3760 */
3761#endif /* USE_FULL_LL_DRIVER */
3762
3763/**
3764 * @}
3765 */
3766
3767/**
3768 * @}
3769 */
3770
3771#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
3772
3773/**
3774 * @}
3775 */
3776
3777#ifdef __cplusplus
3778}
3779#endif
3780
3781#endif /* STM32H7xx_LL_SPI_H */
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
__IO
#define __IO
Defines 'read / write' permissions.
Definition core_armv81mml.h:290
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
READ_REG
#define READ_REG(REG)
Definition stm32h7xx.h:217
ErrorStatus
ErrorStatus
Definition stm32h7xx.h:194
SPI_IER_TIFREIE
#define SPI_IER_TIFREIE
TI Frame Error interrupt enable.
Definition stm32h723xx.h:18558
SPI_SR_RXPLVL
#define SPI_SR_RXPLVL
RxFIFO Packing Level.
Definition stm32h723xx.h:18608
SPI_IFCR_EOTC
#define SPI_IFCR_EOTC
End Of Transfer flag clear.
Definition stm32h723xx.h:18621
SPI_CR1_CSTART
#define SPI_CR1_CSTART
Master transfer start.
Definition stm32h723xx.h:18378
SPI_IFCR_UDRC
#define SPI_IFCR_UDRC
Underrun flag clear.
Definition stm32h723xx.h:18627
SPI_SR_UDR
#define SPI_SR_UDR
UDR at Slave transmission.
Definition stm32h723xx.h:18584
SPI_SR_TXC
#define SPI_SR_TXC
TxFIFO transmission complete.
Definition stm32h723xx.h:18605
SPI_IER_TSERFIE
#define SPI_IER_TSERFIE
TSERF interrupt enable.
Definition stm32h723xx.h:18564
SPI_CFG2_COMM
#define SPI_CFG2_COMM
COMM [1:0]: SPI Communication Mode.
Definition stm32h723xx.h:18490
SPI_I2SCFGR_I2SDIV_Pos
#define SPI_I2SCFGR_I2SDIV_Pos
Definition stm32h723xx.h:18715
SPI_I2SCFGR_DATFMT
#define SPI_I2SCFGR_DATFMT
Data format.
Definition stm32h723xx.h:18714
SPI_CFG1_CRCEN
#define SPI_CFG1_CRCEN
Hardware CRC computation enable.
Definition stm32h723xx.h:18458
SPI_CFG2_CPHA
#define SPI_CFG2_CPHA
Clock Phase.
Definition stm32h723xx.h:18509
SPI_IER_CRCEIE
#define SPI_IER_CRCEIE
CRCE interrupt enable.
Definition stm32h723xx.h:18555
SPI_I2SCFGR_I2SDIV
#define SPI_I2SCFGR_I2SDIV
I2S Linear prescaler.
Definition stm32h723xx.h:18717
SPI_SR_SUSP
#define SPI_SR_SUSP
SUSP is set by hardware.
Definition stm32h723xx.h:18602
SPI_IER_UDRIE
#define SPI_IER_UDRIE
UDR interrupt enable.
Definition stm32h723xx.h:18549
SPI_IFCR_MODFC
#define SPI_IFCR_MODFC
Mode Fault flag clear.
Definition stm32h723xx.h:18639
SPI_I2SCFGR_ODD
#define SPI_I2SCFGR_ODD
Odd factor for the prescaler.
Definition stm32h723xx.h:18720
SPI_IER_TXPIE
#define SPI_IER_TXPIE
TXP interrupt enable.
Definition stm32h723xx.h:18537
SPI_IFCR_TXTFC
#define SPI_IFCR_TXTFC
Transmission Transfer Filled flag clear.
Definition stm32h723xx.h:18624
SPI_CFG1_MBR
#define SPI_CFG1_MBR
Master baud rate.
Definition stm32h723xx.h:18462
SPI_SR_CRCE
#define SPI_SR_CRCE
CRC Error Detected.
Definition stm32h723xx.h:18590
SPI_SR_TSERF
#define SPI_SR_TSERF
Number of SPI data to be transacted reloaded.
Definition stm32h723xx.h:18599
SPI_CFG1_FTHLV
#define SPI_CFG1_FTHLV
FTHVL [3:0]: FIFO threshold level.
Definition stm32h723xx.h:18421
SPI_I2SCFGR_CKPOL
#define SPI_I2SCFGR_CKPOL
Steady state clock polarity.
Definition stm32h723xx.h:18705
SPI_CR2_TSER_Pos
#define SPI_CR2_TSER_Pos
Definition stm32h723xx.h:18402
SPI_CR1_SSI
#define SPI_CR1_SSI
Internal SS signal input level.
Definition stm32h723xx.h:18387
SPI_IER_DXPIE
#define SPI_IER_DXPIE
DXP interrupt enable.
Definition stm32h723xx.h:18540
SPI_CFG2_SP
#define SPI_CFG2_SP
SP[2:0]: Serial Protocol.
Definition stm32h723xx.h:18496
SPI_IFCR_SUSPC
#define SPI_IFCR_SUSPC
SUSPend flag clear.
Definition stm32h723xx.h:18645
SPI_I2SCFGR_PCMSYNC
#define SPI_I2SCFGR_PCMSYNC
PCM frame synchronization.
Definition stm32h723xx.h:18694
SPI_CR2_TSER
#define SPI_CR2_TSER
Number of data transfer extension.
Definition stm32h723xx.h:18404
SPI_CFG2_IOSWP
#define SPI_CFG2_IOSWP
Swap functionality of MISO and MOSI pins.
Definition stm32h723xx.h:18486
SPI_IER_OVRIE
#define SPI_IER_OVRIE
OVR interrupt enable.
Definition stm32h723xx.h:18552
SPI_IER_MODFIE
#define SPI_IER_MODFIE
MODF interrupt enable.
Definition stm32h723xx.h:18561
SPI_SR_CTSIZE
#define SPI_SR_CTSIZE
Number of data frames remaining in TSIZE.
Definition stm32h723xx.h:18616
SPI_CR1_HDDIR
#define SPI_CR1_HDDIR
Rx/Tx direction at Half-duplex mode.
Definition stm32h723xx.h:18384
SPI_SR_DXP
#define SPI_SR_DXP
Duplex Packet available.
Definition stm32h723xx.h:18575
SPI_I2SCFGR_I2SSTD
#define SPI_I2SCFGR_I2SSTD
I2SSTD[1:0] I2S standard selection.
Definition stm32h723xx.h:18689
SPI_CFG2_MSSI
#define SPI_CFG2_MSSI
Master SS Idleness.
Definition stm32h723xx.h:18470
SPI_I2SCFGR_ODD_Pos
#define SPI_I2SCFGR_ODD_Pos
Definition stm32h723xx.h:18718
SPI_IER_RXPIE
#define SPI_IER_RXPIE
RXP Interrupt Enable.
Definition stm32h723xx.h:18534
SPI_CR1_IOLOCK
#define SPI_CR1_IOLOCK
Locking the AF configuration of associated IOs.
Definition stm32h723xx.h:18399
SPI_SR_RXP
#define SPI_SR_RXP
Rx-Packet available.
Definition stm32h723xx.h:18569
SPI_I2SCFGR_CHLEN
#define SPI_I2SCFGR_CHLEN
Channel length (number of bits per audio channel).
Definition stm32h723xx.h:18702
SPI_CFG2_SSOE
#define SPI_CFG2_SSOE
SS output enable.
Definition stm32h723xx.h:18522
SPI_SR_TXP
#define SPI_SR_TXP
Tx-Packet space available.
Definition stm32h723xx.h:18572
SPI_CFG2_SSIOP
#define SPI_CFG2_SSIOP
SS input/output polarity.
Definition stm32h723xx.h:18519
SPI_CFG1_RXDMAEN
#define SPI_CFG1_RXDMAEN
Rx DMA stream enable.
Definition stm32h723xx.h:18442
SPI_IFCR_CRCEC
#define SPI_IFCR_CRCEC
CRC Error flag clear.
Definition stm32h723xx.h:18633
SPI_SR_OVR
#define SPI_SR_OVR
Rx-Packet available.
Definition stm32h723xx.h:18587
SPI_CR1_CRC33_17
#define SPI_CR1_CRC33_17
32-bit CRC polynomial configuration
Definition stm32h723xx.h:18390
SPI_CR1_RCRCINI
#define SPI_CR1_RCRCINI
CRC init pattern control for receiver.
Definition stm32h723xx.h:18393
SPI_CR1_TCRCINI
#define SPI_CR1_TCRCINI
CRC init pattern control for transmitter.
Definition stm32h723xx.h:18396
SPI_CFG2_LSBFRST
#define SPI_CFG2_LSBFRST
Data frame format.
Definition stm32h723xx.h:18506
SPI_SR_RXWNE
#define SPI_SR_RXWNE
Rx FIFO Word Not Empty.
Definition stm32h723xx.h:18613
SPI_CFG2_MIDI
#define SPI_CFG2_MIDI
Master Inter-Data Idleness.
Definition stm32h723xx.h:18478
SPI_CFG1_DSIZE
#define SPI_CFG1_DSIZE
DSIZE[4:0]: Bits number in single SPI data frame.
Definition stm32h723xx.h:18412
SPI_SR_MODF
#define SPI_SR_MODF
Mode Fault Detected.
Definition stm32h723xx.h:18596
SPI_CFG1_UDRDET
#define SPI_CFG1_UDRDET
UDRDET[1:0]: Detection of underrun condition.
Definition stm32h723xx.h:18436
SPI_CFG2_SSOM
#define SPI_CFG2_SSOM
SS output management in master mode.
Definition stm32h723xx.h:18525
SPI_I2SCFGR_WSINV
#define SPI_I2SCFGR_WSINV
Word select inversion.
Definition stm32h723xx.h:18711
SPI_SR_TXTF
#define SPI_SR_TXTF
Transmission Transfer Filled.
Definition stm32h723xx.h:18581
SPI_CR1_CSUSP
#define SPI_CR1_CSUSP
Master SUSPend request.
Definition stm32h723xx.h:18381
SPI_CFG1_TXDMAEN
#define SPI_CFG1_TXDMAEN
Tx DMA stream enable.
Definition stm32h723xx.h:18445
SPI_CR1_SPE
#define SPI_CR1_SPE
Serial Peripheral Enable.
Definition stm32h723xx.h:18372
SPI_I2SCFGR_DATLEN
#define SPI_I2SCFGR_DATLEN
DATLEN[1:0] Data length to be transferred.
Definition stm32h723xx.h:18697
SPI_I2SCFGR_MCKOE
#define SPI_I2SCFGR_MCKOE
Master Clock Output Enable.
Definition stm32h723xx.h:18723
SPI_IFCR_TSERFC
#define SPI_IFCR_TSERFC
TSERFC flag clear.
Definition stm32h723xx.h:18642
SPI_CFG2_SSM
#define SPI_CFG2_SSM
Software slave management.
Definition stm32h723xx.h:18515
SPI_SR_CTSIZE_Pos
#define SPI_SR_CTSIZE_Pos
Definition stm32h723xx.h:18614
SPI_IER_EOTIE
#define SPI_IER_EOTIE
EOT/SUSP/TXC interrupt enable.
Definition stm32h723xx.h:18543
SPI_IFCR_TIFREC
#define SPI_IFCR_TIFREC
TI frame format error flag clear.
Definition stm32h723xx.h:18636
SPI_SR_EOT
#define SPI_SR_EOT
Duplex Packet available.
Definition stm32h723xx.h:18578
SPI_CFG1_CRCSIZE
#define SPI_CFG1_CRCSIZE
CRCSIZE [4:0]: Length of CRC frame.
Definition stm32h723xx.h:18449
SPI_CFG2_MASTER
#define SPI_CFG2_MASTER
SPI Master.
Definition stm32h723xx.h:18503
SPI_CR1_MASRX
#define SPI_CR1_MASRX
Master automatic SUSP in Receive mode.
Definition stm32h723xx.h:18375
SPI_I2SCFGR_I2SMOD
#define SPI_I2SCFGR_I2SMOD
I2S mode selection.
Definition stm32h723xx.h:18680
SPI_I2SCFGR_I2SCFG
#define SPI_I2SCFGR_I2SCFG
I2SCFG[2:0] I2S configuration mode.
Definition stm32h723xx.h:18683
SPI_CFG2_AFCNTR
#define SPI_CFG2_AFCNTR
Alternate function GPIOs control.
Definition stm32h723xx.h:18529
SPI_IER_TXTFIE
#define SPI_IER_TXTFIE
TXTF interrupt enable.
Definition stm32h723xx.h:18546
SPI_SR_TIFRE
#define SPI_SR_TIFRE
TI frame format error Detected.
Definition stm32h723xx.h:18593
SPI_CR2_TSIZE
#define SPI_CR2_TSIZE
Number of data at current transfer.
Definition stm32h723xx.h:18407
SPI_I2SCFGR_FIXCH
#define SPI_I2SCFGR_FIXCH
Fixed channel length in SLAVE.
Definition stm32h723xx.h:18708
SPI_CFG2_CPOL
#define SPI_CFG2_CPOL
Clock Polarity.
Definition stm32h723xx.h:18512
SPI_CFG1_UDRCFG
#define SPI_CFG1_UDRCFG
UDRCFG[1:0]: Behavior of transmitter at underrun.
Definition stm32h723xx.h:18429
SPI_IFCR_OVRC
#define SPI_IFCR_OVRC
Overrun flag clear.
Definition stm32h723xx.h:18630
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32h723xx.h:1479
SPI_TypeDef::RXDR
__IO uint32_t RXDR
SPI/I2S Receive data register, Address offset: 0x30.
Definition stm32h723xx.h:1490
SPI_TypeDef::CRCPOLY
__IO uint32_t CRCPOLY
SPI CRC Polynomial register, Address offset: 0x40.
Definition stm32h723xx.h:1492
SPI_TypeDef::UDRDR
__IO uint32_t UDRDR
SPI Underrun data register, Address offset: 0x4C.
Definition stm32h723xx.h:1495
SPI_TypeDef::CFG1
__IO uint32_t CFG1
SPI Configuration register 1, Address offset: 0x08.
Definition stm32h723xx.h:1482
SPI_TypeDef::SR
__IO uint32_t SR
SPI/I2S Status register, Address offset: 0x14.
Definition stm32h723xx.h:1485
SPI_TypeDef::CR2
__IO uint32_t CR2
SPI Control register 2, Address offset: 0x04.
Definition stm32h723xx.h:1481
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
I2S Configuration register, Address offset: 0x50.
Definition stm32h723xx.h:1496
SPI_TypeDef::TXDR
__IO uint32_t TXDR
SPI/I2S Transmit data register, Address offset: 0x20.
Definition stm32h723xx.h:1488
SPI_TypeDef::CR1
__IO uint32_t CR1
SPI/I2S Control register 1, Address offset: 0x00.
Definition stm32h723xx.h:1480
SPI_TypeDef::TXCRC
__IO uint32_t TXCRC
SPI Transmitter CRC register, Address offset: 0x44.
Definition stm32h723xx.h:1493
SPI_TypeDef::RXCRC
__IO uint32_t RXCRC
SPI Receiver CRC register, Address offset: 0x48.
Definition stm32h723xx.h:1494
SPI_TypeDef::CFG2
__IO uint32_t CFG2
SPI Configuration register 2, Address offset: 0x0C.
Definition stm32h723xx.h:1483
SPI_TypeDef::IFCR
__IO uint32_t IFCR
SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18.
Definition stm32h723xx.h:1486
SPI_TypeDef::IER
__IO uint32_t IER
SPI/I2S Interrupt Enable register, Address offset: 0x10.
Definition stm32h723xx.h:1484