Serial Peripheral Interface. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR1
	SPI/I2S Control register 1, Address offset: 0x00.
__IO uint32_t	CR2
	SPI Control register 2, Address offset: 0x04.
__IO uint32_t	CFG1
	SPI Configuration register 1, Address offset: 0x08.
__IO uint32_t	CFG2
	SPI Configuration register 2, Address offset: 0x0C.
__IO uint32_t	IER
	SPI/I2S Interrupt Enable register, Address offset: 0x10.
__IO uint32_t	SR
	SPI/I2S Status register, Address offset: 0x14.
__IO uint32_t	IFCR
	SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18.
uint32_t	RESERVED0
	Reserved, 0x1C.
__IO uint32_t	TXDR
	SPI/I2S Transmit data register, Address offset: 0x20.
uint32_t	RESERVED1 [3]
	Reserved, 0x24-0x2C.
__IO uint32_t	RXDR
	SPI/I2S Receive data register, Address offset: 0x30.
uint32_t	RESERVED2 [3]
	Reserved, 0x34-0x3C.
__IO uint32_t	CRCPOLY
	SPI CRC Polynomial register, Address offset: 0x40.
__IO uint32_t	TXCRC
	SPI Transmitter CRC register, Address offset: 0x44.
__IO uint32_t	RXCRC
	SPI Receiver CRC register, Address offset: 0x48.
__IO uint32_t	UDRDR
	SPI Underrun data register, Address offset: 0x4C.
__IO uint32_t	I2SCFGR
	I2S Configuration register, Address offset: 0x50.

Detailed Description

Serial Peripheral Interface.

Definition at line 1478 of file stm32h723xx.h.

Member Data Documentation

◆ CFG1

__IO uint32_t SPI_TypeDef::CFG1

SPI Configuration register 1, Address offset: 0x08.

Definition at line 1482 of file stm32h723xx.h.

◆ CFG2

__IO uint32_t SPI_TypeDef::CFG2

SPI Configuration register 2, Address offset: 0x0C.

Definition at line 1483 of file stm32h723xx.h.

◆ CR1

__IO uint32_t SPI_TypeDef::CR1

SPI/I2S Control register 1, Address offset: 0x00.

Definition at line 1480 of file stm32h723xx.h.

◆ CR2

__IO uint32_t SPI_TypeDef::CR2

SPI Control register 2, Address offset: 0x04.

Definition at line 1481 of file stm32h723xx.h.

◆ CRCPOLY

__IO uint32_t SPI_TypeDef::CRCPOLY

SPI CRC Polynomial register, Address offset: 0x40.

Definition at line 1492 of file stm32h723xx.h.

◆ I2SCFGR

__IO uint32_t SPI_TypeDef::I2SCFGR

I2S Configuration register, Address offset: 0x50.

Definition at line 1496 of file stm32h723xx.h.

◆ IER

__IO uint32_t SPI_TypeDef::IER

SPI/I2S Interrupt Enable register, Address offset: 0x10.

Definition at line 1484 of file stm32h723xx.h.

◆ IFCR

__IO uint32_t SPI_TypeDef::IFCR

SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18.

Definition at line 1486 of file stm32h723xx.h.

◆ RESERVED0

uint32_t SPI_TypeDef::RESERVED0

Reserved, 0x1C.

Definition at line 1487 of file stm32h723xx.h.

◆ RESERVED1

uint32_t SPI_TypeDef::RESERVED1[3]

Reserved, 0x24-0x2C.

Definition at line 1489 of file stm32h723xx.h.

◆ RESERVED2

uint32_t SPI_TypeDef::RESERVED2[3]

Reserved, 0x34-0x3C.

Definition at line 1491 of file stm32h723xx.h.

◆ RXCRC

__IO uint32_t SPI_TypeDef::RXCRC

SPI Receiver CRC register, Address offset: 0x48.

Definition at line 1494 of file stm32h723xx.h.

◆ RXDR

__IO uint32_t SPI_TypeDef::RXDR

SPI/I2S Receive data register, Address offset: 0x30.

Definition at line 1490 of file stm32h723xx.h.

◆ SR

__IO uint32_t SPI_TypeDef::SR

SPI/I2S Status register, Address offset: 0x14.

Definition at line 1485 of file stm32h723xx.h.

◆ TXCRC

__IO uint32_t SPI_TypeDef::TXCRC

SPI Transmitter CRC register, Address offset: 0x44.

Definition at line 1493 of file stm32h723xx.h.

◆ TXDR

__IO uint32_t SPI_TypeDef::TXDR

SPI/I2S Transmit data register, Address offset: 0x20.

Definition at line 1488 of file stm32h723xx.h.

◆ UDRDR

__IO uint32_t SPI_TypeDef::UDRDR

SPI Underrun data register, Address offset: 0x4C.

Definition at line 1495 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes