STAR
Cal STAR — firmware, DAQ server, and engine design
Loading...
Searching...
No Matches
stm32h7xx_ll_tim.h
Go to the documentation of this file.
1/**
2 ******************************************************************************
3 * @file stm32h7xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32H7xx_LL_TIM_H
21#define __STM32H7xx_LL_TIM_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
30/** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
35
36/** @defgroup TIM_LL TIM
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45static const uint8_t OFFSET_TAB_CCMRx[] =
46{
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56};
57
58static const uint8_t SHIFT_TAB_OCxx[] =
59{
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69};
70
71static const uint8_t SHIFT_TAB_ICxx[] =
72{
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82};
83
84static const uint8_t SHIFT_TAB_CCxP[] =
85{
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95};
96
97static const uint8_t SHIFT_TAB_OISx[] =
98{
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108};
109/**
110 * @}
111 */
112
113/* Private constants ---------------------------------------------------------*/
114/** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118#if defined(TIM_BREAK_INPUT_SUPPORT)
119/* Defines used for the bit position in the register and perform offsets */
120#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
121
122/* Generic bit definitions for TIMx_AF1 register */
123#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
124#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
125#endif /* TIM_BREAK_INPUT_SUPPORT */
126
127
128/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
129#define DT_DELAY_1 ((uint8_t)0x7F)
130#define DT_DELAY_2 ((uint8_t)0x3F)
131#define DT_DELAY_3 ((uint8_t)0x1F)
132#define DT_DELAY_4 ((uint8_t)0x1F)
133
134/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
135#define DT_RANGE_1 ((uint8_t)0x00)
136#define DT_RANGE_2 ((uint8_t)0x80)
137#define DT_RANGE_3 ((uint8_t)0xC0)
138#define DT_RANGE_4 ((uint8_t)0xE0)
139
140
141/**
142 * @}
143 */
144
145/* Private macros ------------------------------------------------------------*/
146/** @defgroup TIM_LL_Private_Macros TIM Private Macros
147 * @{
148 */
149/** @brief Convert channel id into channel index.
150 * @param __CHANNEL__ This parameter can be one of the following values:
151 * @arg @ref LL_TIM_CHANNEL_CH1
152 * @arg @ref LL_TIM_CHANNEL_CH1N
153 * @arg @ref LL_TIM_CHANNEL_CH2
154 * @arg @ref LL_TIM_CHANNEL_CH2N
155 * @arg @ref LL_TIM_CHANNEL_CH3
156 * @arg @ref LL_TIM_CHANNEL_CH3N
157 * @arg @ref LL_TIM_CHANNEL_CH4
158 * @arg @ref LL_TIM_CHANNEL_CH5
159 * @arg @ref LL_TIM_CHANNEL_CH6
160 * @retval none
161 */
162#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
163 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
164 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
171
172/** @brief Calculate the deadtime sampling period(in ps).
173 * @param __TIMCLK__ timer input clock frequency (in Hz).
174 * @param __CKD__ This parameter can be one of the following values:
175 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
178 * @retval none
179 */
180#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
181 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
182 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
183 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
184/**
185 * @}
186 */
187
188
189/* Exported types ------------------------------------------------------------*/
190#if defined(USE_FULL_LL_DRIVER)
191/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
192 * @{
193 */
194
195/**
196 * @brief TIM Time Base configuration structure definition.
197 */
198typedef struct
199{
200 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
201 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
202
203 This feature can be modified afterwards using unitary function
204 @ref LL_TIM_SetPrescaler().*/
205
206 uint32_t CounterMode; /*!< Specifies the counter mode.
207 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
208
209 This feature can be modified afterwards using unitary function
210 @ref LL_TIM_SetCounterMode().*/
211
212 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
213 Auto-Reload Register at the next update event.
214 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
215 Some timer instances may support 32 bits counters. In that case this parameter must
216 be a number between 0x0000 and 0xFFFFFFFF.
217
218 This feature can be modified afterwards using unitary function
219 @ref LL_TIM_SetAutoReload().*/
220
221 uint32_t ClockDivision; /*!< Specifies the clock division.
222 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
223
224 This feature can be modified afterwards using unitary function
225 @ref LL_TIM_SetClockDivision().*/
226
227 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
228 reaches zero, an update event is generated and counting restarts
229 from the RCR value (N).
230 This means in PWM mode that (N+1) corresponds to:
231 - the number of PWM periods in edge-aligned mode
232 - the number of half PWM period in center-aligned mode
233 GP timers: this parameter must be a number between Min_Data = 0x00 and
234 Max_Data = 0xFF.
235 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
236 Max_Data = 0xFFFF.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetRepetitionCounter().*/
240} LL_TIM_InitTypeDef;
241
242/**
243 * @brief TIM Output Compare configuration structure definition.
244 */
245typedef struct
246{
247 uint32_t OCMode; /*!< Specifies the output mode.
248 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
249
250 This feature can be modified afterwards using unitary function
251 @ref LL_TIM_OC_SetMode().*/
252
253 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
254 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
255
256 This feature can be modified afterwards using unitary functions
257 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
258
259 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
260 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
261
262 This feature can be modified afterwards using unitary functions
263 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
264
265 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
266 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
267
268 This feature can be modified afterwards using unitary function
269 LL_TIM_OC_SetCompareCHx (x=1..6).*/
270
271 uint32_t OCPolarity; /*!< Specifies the output polarity.
272 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
273
274 This feature can be modified afterwards using unitary function
275 @ref LL_TIM_OC_SetPolarity().*/
276
277 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
278 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
279
280 This feature can be modified afterwards using unitary function
281 @ref LL_TIM_OC_SetPolarity().*/
282
283
284 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
285 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
286
287 This feature can be modified afterwards using unitary function
288 @ref LL_TIM_OC_SetIdleState().*/
289
290 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
291 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
292
293 This feature can be modified afterwards using unitary function
294 @ref LL_TIM_OC_SetIdleState().*/
295} LL_TIM_OC_InitTypeDef;
296
297/**
298 * @brief TIM Input Capture configuration structure definition.
299 */
300
301typedef struct
302{
303
304 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
305 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_IC_SetPolarity().*/
309
310 uint32_t ICActiveInput; /*!< Specifies the input.
311 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_IC_SetActiveInput().*/
315
316 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
317 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_IC_SetPrescaler().*/
321
322 uint32_t ICFilter; /*!< Specifies the input capture filter.
323 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetFilter().*/
327} LL_TIM_IC_InitTypeDef;
328
329
330/**
331 * @brief TIM Encoder interface configuration structure definition.
332 */
333typedef struct
334{
335 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
336 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
337
338 This feature can be modified afterwards using unitary function
339 @ref LL_TIM_SetEncoderMode().*/
340
341 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
343
344 This feature can be modified afterwards using unitary function
345 @ref LL_TIM_IC_SetPolarity().*/
346
347 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
348 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_IC_SetActiveInput().*/
352
353 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
354 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
355
356 This feature can be modified afterwards using unitary function
357 @ref LL_TIM_IC_SetPrescaler().*/
358
359 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
360 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
361
362 This feature can be modified afterwards using unitary function
363 @ref LL_TIM_IC_SetFilter().*/
364
365 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
366 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
367
368 This feature can be modified afterwards using unitary function
369 @ref LL_TIM_IC_SetPolarity().*/
370
371 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
372 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
373
374 This feature can be modified afterwards using unitary function
375 @ref LL_TIM_IC_SetActiveInput().*/
376
377 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
378 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
379
380 This feature can be modified afterwards using unitary function
381 @ref LL_TIM_IC_SetPrescaler().*/
382
383 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
384 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetFilter().*/
388
389} LL_TIM_ENCODER_InitTypeDef;
390
391/**
392 * @brief TIM Hall sensor interface configuration structure definition.
393 */
394typedef struct
395{
396
397 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
398 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetPolarity().*/
402
403 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
404 Prescaler must be set to get a maximum counter period longer than the
405 time interval between 2 consecutive changes on the Hall inputs.
406 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
407
408 This feature can be modified afterwards using unitary function
409 @ref LL_TIM_IC_SetPrescaler().*/
410
411 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
412 This parameter can be a value of
413 @ref TIM_LL_EC_IC_FILTER.
414
415 This feature can be modified afterwards using unitary function
416 @ref LL_TIM_IC_SetFilter().*/
417
418 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
419 A positive pulse (TRGO event) is generated with a programmable delay every time
420 a change occurs on the Hall inputs.
421 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
422
423 This feature can be modified afterwards using unitary function
424 @ref LL_TIM_OC_SetCompareCH2().*/
425} LL_TIM_HALLSENSOR_InitTypeDef;
426
427/**
428 * @brief BDTR (Break and Dead Time) structure definition
429 */
430typedef struct
431{
432 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
433 This parameter can be a value of @ref TIM_LL_EC_OSSR
434
435 This feature can be modified afterwards using unitary function
436 @ref LL_TIM_SetOffStates()
437
438 @note This bit-field cannot be modified as long as LOCK level 2 has been
439 programmed. */
440
441 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
442 This parameter can be a value of @ref TIM_LL_EC_OSSI
443
444 This feature can be modified afterwards using unitary function
445 @ref LL_TIM_SetOffStates()
446
447 @note This bit-field cannot be modified as long as LOCK level 2 has been
448 programmed. */
449
450 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
451 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
452
453 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
454 register has been written, their content is frozen until the next reset.*/
455
456 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
457 switching-on of the outputs.
458 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
459
460 This feature can be modified afterwards using unitary function
461 @ref LL_TIM_OC_SetDeadTime()
462
463 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
464 programmed. */
465
466 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
467 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
468
469 This feature can be modified afterwards using unitary functions
470 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
471
472 @note This bit-field can not be modified as long as LOCK level 1 has been
473 programmed. */
474
475 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
476 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
477
478 This feature can be modified afterwards using unitary function
479 @ref LL_TIM_ConfigBRK()
480
481 @note This bit-field can not be modified as long as LOCK level 1 has been
482 programmed. */
483
484 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
485 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
486
487 This feature can be modified afterwards using unitary function
488 @ref LL_TIM_ConfigBRK()
489
490 @note This bit-field can not be modified as long as LOCK level 1 has been
491 programmed. */
492
493#if defined(TIM_BDTR_BKBID)
494 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
495 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
496
497 This feature can be modified afterwards using unitary functions
498 @ref LL_TIM_ConfigBRK()
499
500 @note Bidirectional break input is only supported by advanced timers instances.
501
502 @note This bit-field can not be modified as long as LOCK level 1 has been
503 programmed. */
504
505#endif /*TIM_BDTR_BKBID */
506 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
507 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
508
509 This feature can be modified afterwards using unitary functions
510 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
511
512 @note This bit-field can not be modified as long as LOCK level 1 has been
513 programmed. */
514
515 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
516 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
517
518 This feature can be modified afterwards using unitary function
519 @ref LL_TIM_ConfigBRK2()
520
521 @note This bit-field can not be modified as long as LOCK level 1 has been
522 programmed. */
523
524 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
525 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
526
527 This feature can be modified afterwards using unitary function
528 @ref LL_TIM_ConfigBRK2()
529
530 @note This bit-field can not be modified as long as LOCK level 1 has been
531 programmed. */
532#if defined(TIM_BDTR_BK2BID)
533
534 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
535 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
536
537 This feature can be modified afterwards using unitary functions
538 @ref LL_TIM_ConfigBRK2()
539
540 @note Bidirectional break input is only supported by advanced timers instances.
541
542 @note This bit-field can not be modified as long as LOCK level 1 has been
543 programmed. */
544#endif /*TIM_BDTR_BK2BID */
545
546 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
547 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
548
549 This feature can be modified afterwards using unitary functions
550 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
551
552 @note This bit-field can not be modified as long as LOCK level 1 has been
553 programmed. */
554} LL_TIM_BDTR_InitTypeDef;
555
556/**
557 * @}
558 */
559#endif /* USE_FULL_LL_DRIVER */
560
561/* Exported constants --------------------------------------------------------*/
562/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
563 * @{
564 */
565
566/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
567 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
568 * @{
569 */
570#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
571#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
572#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
573#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
574#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
575#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
576#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
577#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
578#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
579#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
580#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
581#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
582#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
583#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
584#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
585#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
586/**
587 * @}
588 */
589
590#if defined(USE_FULL_LL_DRIVER)
591/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
592 * @{
593 */
594#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
595#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
596/**
597 * @}
598 */
599
600/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
601 * @{
602 */
603#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
604#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
605/**
606 * @}
607 */
608
609/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
610 * @{
611 */
612#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
613#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
614/**
615 * @}
616 */
617#endif /* USE_FULL_LL_DRIVER */
618
619/** @defgroup TIM_LL_EC_IT IT Defines
620 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
621 * @{
622 */
623#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
624#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
625#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
626#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
627#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
628#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
629#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
630#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
631/**
632 * @}
633 */
634
635/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
636 * @{
637 */
638#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
639#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
640/**
641 * @}
642 */
643
644/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
645 * @{
646 */
647#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
648#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
649/**
650 * @}
651 */
652
653/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
654 * @{
655 */
656#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
657#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
658#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
659#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
660#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
661/**
662 * @}
663 */
664
665/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
666 * @{
667 */
668#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
669#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
670#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
671/**
672 * @}
673 */
674
675/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
676 * @{
677 */
678#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
679#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
680/**
681 * @}
682 */
683
684/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
685 * @{
686 */
687#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
688#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
689/**
690 * @}
691 */
692
693/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
694 * @{
695 */
696#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
697#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
698/**
699 * @}
700 */
701
702/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
703 * @{
704 */
705#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
706#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
707#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
708#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
709/**
710 * @}
711 */
712
713/** @defgroup TIM_LL_EC_CHANNEL Channel
714 * @{
715 */
716#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
717#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
718#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
719#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
720#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
721#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
722#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
723#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
724#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
725/**
726 * @}
727 */
728
729#if defined(USE_FULL_LL_DRIVER)
730/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
731 * @{
732 */
733#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
734#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
735/**
736 * @}
737 */
738#endif /* USE_FULL_LL_DRIVER */
739
740/** Legacy definitions for compatibility purpose
741@cond 0
742 */
743#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
744#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
745/**
746@endcond
747 */
748
749/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
750 * @{
751 */
752#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
753#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
754#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
755#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
756#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
757#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
758#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
759#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
760#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
761#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
762#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
763#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
764#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
765#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
766/**
767 * @}
768 */
769
770/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
771 * @{
772 */
773#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
774#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
775/**
776 * @}
777 */
778
779/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
780 * @{
781 */
782#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
783#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
784/**
785 * @}
786 */
787
788/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
789 * @{
790 */
791#define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
792#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
793#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
794#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
795/**
796 * @}
797 */
798
799/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
800 * @{
801 */
802#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
803#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
804#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
805/**
806 * @}
807 */
808
809/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
810 * @{
811 */
812#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
813#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
814#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
815#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
816/**
817 * @}
818 */
819
820/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
821 * @{
822 */
823#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
824#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
825#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
826#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
827#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
828#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
829#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
830#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
831#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
832#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
833#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
834#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
835#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
836#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
837#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
838#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
839/**
840 * @}
841 */
842
843/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
844 * @{
845 */
846#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
847#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
848#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
849/**
850 * @}
851 */
852
853/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
854 * @{
855 */
856#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
857#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
858#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
859/**
860 * @}
861 */
862
863/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
864 * @{
865 */
866#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
867#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
868#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
869/**
870 * @}
871 */
872
873/** @defgroup TIM_LL_EC_TRGO Trigger Output
874 * @{
875 */
876#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
877#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
878#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
879#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
880#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
881#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
882#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
883#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
884/**
885 * @}
886 */
887
888/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
889 * @{
890 */
891#define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
892#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
893#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
894#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
895#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
896#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
897#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
898#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
899#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
900#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
901#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
902#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
903#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
904#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
905#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
906#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
907/**
908 * @}
909 */
910
911/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
912 * @{
913 */
914#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
915#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
916#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
917#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
918#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
919/**
920 * @}
921 */
922
923/** @defgroup TIM_LL_EC_TS Trigger Selection
924 * @{
925 */
926#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
927#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
928#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
929#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
930#define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
931#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
932#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
933#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
934#define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
935#define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
936#define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
937#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
938#define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
939#define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
940#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
941#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
942#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
943#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
944/**
945 * @}
946 */
947
948/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
949 * @{
950 */
951#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
952#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
953/**
954 * @}
955 */
956
957/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
958 * @{
959 */
960#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
961#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
962#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
963#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
964/**
965 * @}
966 */
967
968/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
969 * @{
970 */
971#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
972#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
973#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
974#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
975#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
976#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
977#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
978#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
979#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
980#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
981#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
982#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
983#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
984#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
985#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
986#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
987/**
988 * @}
989 */
990
991#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */
992#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */
993#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */
994#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
995#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */
996#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
997#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */
998#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
999#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */
1000
1001#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */
1002#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */
1003#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */
1004#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */
1005#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */
1006#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */
1007#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */
1008#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
1009#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */
1010
1011#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */
1012#define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */
1013#define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */
1014#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */
1015#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
1016#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */
1017
1018#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */
1019#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */
1020
1021#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */
1022#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */
1023#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */
1024#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */
1025#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */
1026
1027#define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */
1028#define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */
1029#define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */
1030
1031#define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */
1032#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */
1033#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */
1034#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */
1035#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */
1036
1037/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1038 * @{
1039 */
1040#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1041#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1042/**
1043 * @}
1044 */
1045
1046/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1047 * @{
1048 */
1049#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1050#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1051#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1052#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1053#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1054#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1055#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1056#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1057#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1058#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1059#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1060#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1061#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1062#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1063#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1064#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1065/**
1066 * @}
1067 */
1068
1069/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1070 * @{
1071 */
1072#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1073#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1074/**
1075 * @}
1076 */
1077
1078/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1079 * @{
1080 */
1081#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1082#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1083#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1084#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1085#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1086#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1087#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1088#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1089#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1090#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1091#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1092#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1093#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1094#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1095#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1096#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1097/**
1098 * @}
1099 */
1100
1101/** @defgroup TIM_LL_EC_OSSI OSSI
1102 * @{
1103 */
1104#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1105#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1106/**
1107 * @}
1108 */
1109
1110/** @defgroup TIM_LL_EC_OSSR OSSR
1111 * @{
1112 */
1113#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1114#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1115/**
1116 * @}
1117 */
1118
1119#if defined(TIM_BREAK_INPUT_SUPPORT)
1120/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1121 * @{
1122 */
1123#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1124#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1125/**
1126 * @}
1127 */
1128
1129/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1130 * @{
1131 */
1132#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1133#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1134#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1135#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1136/**
1137 * @}
1138 */
1139
1140/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1141 * @{
1142 */
1143#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1144#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1145/**
1146 * @}
1147 */
1148#endif /* TIM_BREAK_INPUT_SUPPORT */
1149
1150#if defined(TIM_BDTR_BKBID)
1151/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1152 * @{
1153 */
1154#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1155#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1156/**
1157 * @}
1158 */
1159
1160/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1161 * @{
1162 */
1163#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1164#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1165/**
1166 * @}
1167 */
1168
1169/** Legacy definitions for compatibility purpose
1170@cond 0
1171 */
1172#define LL_TIM_ReArmBRK(_PARAM_)
1173#define LL_TIM_ReArmBRK2(_PARAM_)
1174/**
1175@endcond
1176 */
1177
1178#endif /*TIM_BDTR_BKBID */
1179/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1180 * @{
1181 */
1182#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1183#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1184#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1185#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1186#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1187#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1188#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1189#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1190#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1191#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1192#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1193#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1194#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1195#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1196#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1197#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1198#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1199#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1200#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1201#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1202#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1203#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
1204#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1205#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1206#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
1207#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1208/**
1209 * @}
1210 */
1211
1212/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1213 * @{
1214 */
1215#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1216#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1217#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1218#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1219#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1220#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1221#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1222#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1223#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1224#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1225#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1226#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1227#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1228#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1229#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1230#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1231#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1232#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1233/**
1234 * @}
1235 */
1236
1237/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1238 * @{
1239 */
1240#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1241#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1 OUT */
1242/**
1243 * @}
1244 */
1245
1246/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1247 * @{
1248 */
1249#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
1250#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP2 OUT */
1251/**
1252 * @}
1253 */
1254
1255/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1256 * @{
1257 */
1258#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
1259#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1 OUT */
1260#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2 OUT */
1261#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
1262/**
1263 * @}
1264 */
1265
1266/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1267 * @{
1268 */
1269#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1270#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1 OUT */
1271#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2 OUT */
1272#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
1273/**
1274 * @}
1275 */
1276
1277/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1278 * @{
1279 */
1280#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
1281#define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to CAN TMP */
1282#define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to CAN RTP */
1283/**
1284 * @}
1285 */
1286
1287/** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap
1288 * @{
1289 */
1290#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /*!< TIM12 input 1 is connected to GPIO */
1291#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 input 1 is connected to SPDIF FS */
1292/**
1293 * @}
1294 */
1295
1296/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1297 * @{
1298 */
1299#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1300#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 CH1 */
1301#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 CH1 */
1302#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */
1303#define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15 input 1 is connected to RCC LSE */
1304#define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI */
1305#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */
1306/**
1307 * @}
1308 */
1309
1310/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1311 * @{
1312 */
1313#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1314#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to TIM2 CH2 */
1315#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM3 CH2 */
1316#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */
1317/**
1318 * @}
1319 */
1320
1321/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1322 * @{
1323 */
1324#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1325#define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to RCC LSI */
1326#define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to RCC LSE */
1327#define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */
1328/**
1329 * @}
1330 */
1331
1332/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1333 * @{
1334 */
1335#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1336#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to SPDIF FS */
1337#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */
1338#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */
1339/**
1340 * @}
1341 */
1342
1343/** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap
1344 * @{
1345 */
1346#define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /*!< TIM23 input 4 is connected to GPIO */
1347#define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23 input 4 is connected to COMP1 OUT */
1348#define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23 input 4 is connected to COMP2 OUT */
1349#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
1350/**
1351 * @}
1352 */
1353
1354/** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap
1355 * @{
1356 */
1357#define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /*!< TIM24 input 1 is connected to GPIO */
1358#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */
1359#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */
1360#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
1361/**
1362 * @}
1363 */
1364
1365#if defined(TIM_BREAK_INPUT_SUPPORT)
1366/** Legacy definitions for compatibility purpose
1367@cond 0
1368 */
1369#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1370/**
1371@endcond
1372 */
1373#endif /* TIM_BREAK_INPUT_SUPPORT */
1374
1375/**
1376 * @}
1377 */
1378
1379/* Exported macro ------------------------------------------------------------*/
1380/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1381 * @{
1382 */
1383
1384/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1385 * @{
1386 */
1387/**
1388 * @brief Write a value in TIM register.
1389 * @param __INSTANCE__ TIM Instance
1390 * @param __REG__ Register to be written
1391 * @param __VALUE__ Value to be written in the register
1392 * @retval None
1393 */
1394#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1395
1396/**
1397 * @brief Read a value in TIM register.
1398 * @param __INSTANCE__ TIM Instance
1399 * @param __REG__ Register to be read
1400 * @retval Register value
1401 */
1402#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1403/**
1404 * @}
1405 */
1406
1407/**
1408 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1409 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1410 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1411 * to TIMx_CNT register bit 31)
1412 * @param __CNT__ Counter value
1413 * @retval UIF status bit
1414 */
1415#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1416 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1417
1418/**
1419 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1420 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1421 * @param __TIMCLK__ timer input clock frequency (in Hz)
1422 * @param __CKD__ This parameter can be one of the following values:
1423 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1424 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1425 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1426 * @param __DT__ deadtime duration (in ns)
1427 * @retval DTG[0:7]
1428 */
1429#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1430 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1431 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1432 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1433 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1434 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1435 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1436 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1437 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1438 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1439 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1440 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1441 0U)
1442
1443/**
1444 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1445 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1446 * @param __TIMCLK__ timer input clock frequency (in Hz)
1447 * @param __CNTCLK__ counter clock frequency (in Hz)
1448 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1449 */
1450#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1451 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1452
1453/**
1454 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1455 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1456 * @param __TIMCLK__ timer input clock frequency (in Hz)
1457 * @param __PSC__ prescaler
1458 * @param __FREQ__ output signal frequency (in Hz)
1459 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1460 */
1461#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1462 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1463
1464/**
1465 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1466 * active/inactive delay.
1467 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1468 * @param __TIMCLK__ timer input clock frequency (in Hz)
1469 * @param __PSC__ prescaler
1470 * @param __DELAY__ timer output compare active/inactive delay (in us)
1471 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1472 */
1473#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1474 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1475 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1476
1477/**
1478 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1479 * (when the timer operates in one pulse mode).
1480 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1481 * @param __TIMCLK__ timer input clock frequency (in Hz)
1482 * @param __PSC__ prescaler
1483 * @param __DELAY__ timer output compare active/inactive delay (in us)
1484 * @param __PULSE__ pulse duration (in us)
1485 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1486 */
1487#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1488 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1489 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1490
1491/**
1492 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1493 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1494 * @param __ICPSC__ This parameter can be one of the following values:
1495 * @arg @ref LL_TIM_ICPSC_DIV1
1496 * @arg @ref LL_TIM_ICPSC_DIV2
1497 * @arg @ref LL_TIM_ICPSC_DIV4
1498 * @arg @ref LL_TIM_ICPSC_DIV8
1499 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1500 */
1501#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1502 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1503
1504
1505/**
1506 * @}
1507 */
1508
1509/* Exported functions --------------------------------------------------------*/
1510/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1511 * @{
1512 */
1513
1514/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1515 * @{
1516 */
1517/**
1518 * @brief Enable timer counter.
1519 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1520 * @param TIMx Timer instance
1521 * @retval None
1522 */
1523__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1524{
1525 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1526}
1527
1528/**
1529 * @brief Disable timer counter.
1530 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1531 * @param TIMx Timer instance
1532 * @retval None
1533 */
1534__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1535{
1536 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1537}
1538
1539/**
1540 * @brief Indicates whether the timer counter is enabled.
1541 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1542 * @param TIMx Timer instance
1543 * @retval State of bit (1 or 0).
1544 */
1545__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1546{
1547 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1548}
1549
1550/**
1551 * @brief Enable update event generation.
1552 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1553 * @param TIMx Timer instance
1554 * @retval None
1555 */
1556__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1557{
1558 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1559}
1560
1561/**
1562 * @brief Disable update event generation.
1563 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1564 * @param TIMx Timer instance
1565 * @retval None
1566 */
1567__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1568{
1569 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1570}
1571
1572/**
1573 * @brief Indicates whether update event generation is enabled.
1574 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1575 * @param TIMx Timer instance
1576 * @retval Inverted state of bit (0 or 1).
1577 */
1578__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1579{
1580 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1581}
1582
1583/**
1584 * @brief Set update event source
1585 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1586 * generate an update interrupt or DMA request if enabled:
1587 * - Counter overflow/underflow
1588 * - Setting the UG bit
1589 * - Update generation through the slave mode controller
1590 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1591 * overflow/underflow generates an update interrupt or DMA request if enabled.
1592 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1593 * @param TIMx Timer instance
1594 * @param UpdateSource This parameter can be one of the following values:
1595 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1596 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1597 * @retval None
1598 */
1599__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1600{
1601 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1602}
1603
1604/**
1605 * @brief Get actual event update source
1606 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1607 * @param TIMx Timer instance
1608 * @retval Returned value can be one of the following values:
1609 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1610 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1611 */
1612__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1613{
1614 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1615}
1616
1617/**
1618 * @brief Set one pulse mode (one shot v.s. repetitive).
1619 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1620 * @param TIMx Timer instance
1621 * @param OnePulseMode This parameter can be one of the following values:
1622 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1623 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1624 * @retval None
1625 */
1626__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1627{
1628 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1629}
1630
1631/**
1632 * @brief Get actual one pulse mode.
1633 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1634 * @param TIMx Timer instance
1635 * @retval Returned value can be one of the following values:
1636 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1637 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1638 */
1639__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1640{
1641 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1642}
1643
1644/**
1645 * @brief Set the timer counter counting mode.
1646 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1647 * check whether or not the counter mode selection feature is supported
1648 * by a timer instance.
1649 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1650 * requires a timer reset to avoid unexpected direction
1651 * due to DIR bit readonly in center aligned mode.
1652 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1653 * CR1 CMS LL_TIM_SetCounterMode
1654 * @param TIMx Timer instance
1655 * @param CounterMode This parameter can be one of the following values:
1656 * @arg @ref LL_TIM_COUNTERMODE_UP
1657 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1658 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1659 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1660 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1661 * @retval None
1662 */
1663__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1664{
1665 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1666}
1667
1668/**
1669 * @brief Get actual counter mode.
1670 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1671 * check whether or not the counter mode selection feature is supported
1672 * by a timer instance.
1673 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1674 * CR1 CMS LL_TIM_GetCounterMode
1675 * @param TIMx Timer instance
1676 * @retval Returned value can be one of the following values:
1677 * @arg @ref LL_TIM_COUNTERMODE_UP
1678 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1679 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1680 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1681 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1682 */
1683__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1684{
1685 uint32_t counter_mode;
1686
1687 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1688
1689 if (counter_mode == 0U)
1690 {
1691 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1692 }
1693
1694 return counter_mode;
1695}
1696
1697/**
1698 * @brief Enable auto-reload (ARR) preload.
1699 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1700 * @param TIMx Timer instance
1701 * @retval None
1702 */
1703__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1704{
1705 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1706}
1707
1708/**
1709 * @brief Disable auto-reload (ARR) preload.
1710 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1711 * @param TIMx Timer instance
1712 * @retval None
1713 */
1714__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1715{
1716 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1717}
1718
1719/**
1720 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1721 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1722 * @param TIMx Timer instance
1723 * @retval State of bit (1 or 0).
1724 */
1725__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1726{
1727 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1728}
1729
1730/**
1731 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1732 * (when supported) and the digital filters.
1733 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1734 * whether or not the clock division feature is supported by the timer
1735 * instance.
1736 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1737 * @param TIMx Timer instance
1738 * @param ClockDivision This parameter can be one of the following values:
1739 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1740 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1741 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1742 * @retval None
1743 */
1744__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1745{
1746 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1747}
1748
1749/**
1750 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1751 * generators (when supported) and the digital filters.
1752 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1753 * whether or not the clock division feature is supported by the timer
1754 * instance.
1755 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1756 * @param TIMx Timer instance
1757 * @retval Returned value can be one of the following values:
1758 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1759 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1760 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1761 */
1762__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1763{
1764 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1765}
1766
1767/**
1768 * @brief Set the counter value.
1769 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1770 * whether or not a timer instance supports a 32 bits counter.
1771 * @rmtoll CNT CNT LL_TIM_SetCounter
1772 * @param TIMx Timer instance
1773 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1774 * @retval None
1775 */
1776__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1777{
1778 WRITE_REG(TIMx->CNT, Counter);
1779}
1780
1781/**
1782 * @brief Get the counter value.
1783 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1784 * whether or not a timer instance supports a 32 bits counter.
1785 * @rmtoll CNT CNT LL_TIM_GetCounter
1786 * @param TIMx Timer instance
1787 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1788 */
1789__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1790{
1791 return (uint32_t)(READ_REG(TIMx->CNT));
1792}
1793
1794/**
1795 * @brief Get the current direction of the counter
1796 * @rmtoll CR1 DIR LL_TIM_GetDirection
1797 * @param TIMx Timer instance
1798 * @retval Returned value can be one of the following values:
1799 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1800 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1801 */
1802__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1803{
1804 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1805}
1806
1807/**
1808 * @brief Set the prescaler value.
1809 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1810 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1811 * prescaler ratio is taken into account at the next update event.
1812 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1813 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1814 * @param TIMx Timer instance
1815 * @param Prescaler between Min_Data=0 and Max_Data=65535
1816 * @retval None
1817 */
1818__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1819{
1820 WRITE_REG(TIMx->PSC, Prescaler);
1821}
1822
1823/**
1824 * @brief Get the prescaler value.
1825 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1826 * @param TIMx Timer instance
1827 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1828 */
1829__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1830{
1831 return (uint32_t)(READ_REG(TIMx->PSC));
1832}
1833
1834/**
1835 * @brief Set the auto-reload value.
1836 * @note The counter is blocked while the auto-reload value is null.
1837 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1838 * whether or not a timer instance supports a 32 bits counter.
1839 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1840 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1841 * @param TIMx Timer instance
1842 * @param AutoReload between Min_Data=0 and Max_Data=65535
1843 * @retval None
1844 */
1845__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1846{
1847 WRITE_REG(TIMx->ARR, AutoReload);
1848}
1849
1850/**
1851 * @brief Get the auto-reload value.
1852 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1853 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1854 * whether or not a timer instance supports a 32 bits counter.
1855 * @param TIMx Timer instance
1856 * @retval Auto-reload value
1857 */
1858__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1859{
1860 return (uint32_t)(READ_REG(TIMx->ARR));
1861}
1862
1863/**
1864 * @brief Set the repetition counter value.
1865 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1866 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1867 * whether or not a timer instance supports a repetition counter.
1868 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1869 * @param TIMx Timer instance
1870 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1871 * @retval None
1872 */
1873__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1874{
1875 WRITE_REG(TIMx->RCR, RepetitionCounter);
1876}
1877
1878/**
1879 * @brief Get the repetition counter value.
1880 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1881 * whether or not a timer instance supports a repetition counter.
1882 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1883 * @param TIMx Timer instance
1884 * @retval Repetition counter value
1885 */
1886__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1887{
1888 return (uint32_t)(READ_REG(TIMx->RCR));
1889}
1890
1891/**
1892 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1893 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1894 * in an atomic way.
1895 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1896 * @param TIMx Timer instance
1897 * @retval None
1898 */
1899__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1900{
1901 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1902}
1903
1904/**
1905 * @brief Disable update interrupt flag (UIF) remapping.
1906 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1907 * @param TIMx Timer instance
1908 * @retval None
1909 */
1910__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1911{
1912 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1913}
1914
1915/**
1916 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1917 * @param Counter Counter value
1918 * @retval State of bit (1 or 0).
1919 */
1920__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1921{
1922 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1923}
1924
1925/**
1926 * @}
1927 */
1928
1929/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1930 * @{
1931 */
1932/**
1933 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1934 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1935 * they are updated only when a commutation event (COM) occurs.
1936 * @note Only on channels that have a complementary output.
1937 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1938 * whether or not a timer instance is able to generate a commutation event.
1939 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1940 * @param TIMx Timer instance
1941 * @retval None
1942 */
1943__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1944{
1945 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1946}
1947
1948/**
1949 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1950 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1951 * whether or not a timer instance is able to generate a commutation event.
1952 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1953 * @param TIMx Timer instance
1954 * @retval None
1955 */
1956__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1957{
1958 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1959}
1960
1961/**
1962 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1963 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1964 * @param TIMx Timer instance
1965 * @retval State of bit (1 or 0).
1966 */
1967__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1968{
1969 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1970}
1971
1972/**
1973 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1974 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1975 * whether or not a timer instance is able to generate a commutation event.
1976 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1977 * @param TIMx Timer instance
1978 * @param CCUpdateSource This parameter can be one of the following values:
1979 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1980 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1981 * @retval None
1982 */
1983__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1984{
1985 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1986}
1987
1988/**
1989 * @brief Set the trigger of the capture/compare DMA request.
1990 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1991 * @param TIMx Timer instance
1992 * @param DMAReqTrigger This parameter can be one of the following values:
1993 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1994 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1995 * @retval None
1996 */
1997__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1998{
1999 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2000}
2001
2002/**
2003 * @brief Get actual trigger of the capture/compare DMA request.
2004 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2005 * @param TIMx Timer instance
2006 * @retval Returned value can be one of the following values:
2007 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2008 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2009 */
2010__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2011{
2012 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2013}
2014
2015/**
2016 * @brief Set the lock level to freeze the
2017 * configuration of several capture/compare parameters.
2018 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2019 * the lock mechanism is supported by a timer instance.
2020 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2021 * @param TIMx Timer instance
2022 * @param LockLevel This parameter can be one of the following values:
2023 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2024 * @arg @ref LL_TIM_LOCKLEVEL_1
2025 * @arg @ref LL_TIM_LOCKLEVEL_2
2026 * @arg @ref LL_TIM_LOCKLEVEL_3
2027 * @retval None
2028 */
2029__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2030{
2031 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2032}
2033
2034/**
2035 * @brief Enable capture/compare channels.
2036 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2037 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2038 * CCER CC2E LL_TIM_CC_EnableChannel\n
2039 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2040 * CCER CC3E LL_TIM_CC_EnableChannel\n
2041 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2042 * CCER CC4E LL_TIM_CC_EnableChannel\n
2043 * CCER CC5E LL_TIM_CC_EnableChannel\n
2044 * CCER CC6E LL_TIM_CC_EnableChannel
2045 * @param TIMx Timer instance
2046 * @param Channels This parameter can be a combination of the following values:
2047 * @arg @ref LL_TIM_CHANNEL_CH1
2048 * @arg @ref LL_TIM_CHANNEL_CH1N
2049 * @arg @ref LL_TIM_CHANNEL_CH2
2050 * @arg @ref LL_TIM_CHANNEL_CH2N
2051 * @arg @ref LL_TIM_CHANNEL_CH3
2052 * @arg @ref LL_TIM_CHANNEL_CH3N
2053 * @arg @ref LL_TIM_CHANNEL_CH4
2054 * @arg @ref LL_TIM_CHANNEL_CH5
2055 * @arg @ref LL_TIM_CHANNEL_CH6
2056 * @retval None
2057 */
2058__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2059{
2060 SET_BIT(TIMx->CCER, Channels);
2061}
2062
2063/**
2064 * @brief Disable capture/compare channels.
2065 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2066 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2067 * CCER CC2E LL_TIM_CC_DisableChannel\n
2068 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2069 * CCER CC3E LL_TIM_CC_DisableChannel\n
2070 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2071 * CCER CC4E LL_TIM_CC_DisableChannel\n
2072 * CCER CC5E LL_TIM_CC_DisableChannel\n
2073 * CCER CC6E LL_TIM_CC_DisableChannel
2074 * @param TIMx Timer instance
2075 * @param Channels This parameter can be a combination of the following values:
2076 * @arg @ref LL_TIM_CHANNEL_CH1
2077 * @arg @ref LL_TIM_CHANNEL_CH1N
2078 * @arg @ref LL_TIM_CHANNEL_CH2
2079 * @arg @ref LL_TIM_CHANNEL_CH2N
2080 * @arg @ref LL_TIM_CHANNEL_CH3
2081 * @arg @ref LL_TIM_CHANNEL_CH3N
2082 * @arg @ref LL_TIM_CHANNEL_CH4
2083 * @arg @ref LL_TIM_CHANNEL_CH5
2084 * @arg @ref LL_TIM_CHANNEL_CH6
2085 * @retval None
2086 */
2087__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2088{
2089 CLEAR_BIT(TIMx->CCER, Channels);
2090}
2091
2092/**
2093 * @brief Indicate whether channel(s) is(are) enabled.
2094 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2095 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2096 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2097 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2098 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2099 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2100 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2101 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2102 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2103 * @param TIMx Timer instance
2104 * @param Channels This parameter can be a combination of the following values:
2105 * @arg @ref LL_TIM_CHANNEL_CH1
2106 * @arg @ref LL_TIM_CHANNEL_CH1N
2107 * @arg @ref LL_TIM_CHANNEL_CH2
2108 * @arg @ref LL_TIM_CHANNEL_CH2N
2109 * @arg @ref LL_TIM_CHANNEL_CH3
2110 * @arg @ref LL_TIM_CHANNEL_CH3N
2111 * @arg @ref LL_TIM_CHANNEL_CH4
2112 * @arg @ref LL_TIM_CHANNEL_CH5
2113 * @arg @ref LL_TIM_CHANNEL_CH6
2114 * @retval State of bit (1 or 0).
2115 */
2116__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2117{
2118 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2119}
2120
2121/**
2122 * @}
2123 */
2124
2125/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2126 * @{
2127 */
2128/**
2129 * @brief Configure an output channel.
2130 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2131 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2132 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2133 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2134 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2135 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2136 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2137 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2138 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2139 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2140 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2141 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2142 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2143 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2144 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2145 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2146 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2147 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2148 * @param TIMx Timer instance
2149 * @param Channel This parameter can be one of the following values:
2150 * @arg @ref LL_TIM_CHANNEL_CH1
2151 * @arg @ref LL_TIM_CHANNEL_CH2
2152 * @arg @ref LL_TIM_CHANNEL_CH3
2153 * @arg @ref LL_TIM_CHANNEL_CH4
2154 * @arg @ref LL_TIM_CHANNEL_CH5
2155 * @arg @ref LL_TIM_CHANNEL_CH6
2156 * @param Configuration This parameter must be a combination of all the following values:
2157 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2158 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2159 * @retval None
2160 */
2161__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2162{
2163 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2164 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2165 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2166 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2167 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2168 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2169 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2170}
2171
2172/**
2173 * @brief Define the behavior of the output reference signal OCxREF from which
2174 * OCx and OCxN (when relevant) are derived.
2175 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2176 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2177 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2178 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2179 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2180 * CCMR3 OC6M LL_TIM_OC_SetMode
2181 * @param TIMx Timer instance
2182 * @param Channel This parameter can be one of the following values:
2183 * @arg @ref LL_TIM_CHANNEL_CH1
2184 * @arg @ref LL_TIM_CHANNEL_CH2
2185 * @arg @ref LL_TIM_CHANNEL_CH3
2186 * @arg @ref LL_TIM_CHANNEL_CH4
2187 * @arg @ref LL_TIM_CHANNEL_CH5
2188 * @arg @ref LL_TIM_CHANNEL_CH6
2189 * @param Mode This parameter can be one of the following values:
2190 * @arg @ref LL_TIM_OCMODE_FROZEN
2191 * @arg @ref LL_TIM_OCMODE_ACTIVE
2192 * @arg @ref LL_TIM_OCMODE_INACTIVE
2193 * @arg @ref LL_TIM_OCMODE_TOGGLE
2194 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2195 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2196 * @arg @ref LL_TIM_OCMODE_PWM1
2197 * @arg @ref LL_TIM_OCMODE_PWM2
2198 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2199 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2200 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2201 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2202 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2203 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2204 * @retval None
2205 */
2206__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2207{
2208 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2209 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2210 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2211}
2212
2213/**
2214 * @brief Get the output compare mode of an output channel.
2215 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2216 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2217 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2218 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2219 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2220 * CCMR3 OC6M LL_TIM_OC_GetMode
2221 * @param TIMx Timer instance
2222 * @param Channel This parameter can be one of the following values:
2223 * @arg @ref LL_TIM_CHANNEL_CH1
2224 * @arg @ref LL_TIM_CHANNEL_CH2
2225 * @arg @ref LL_TIM_CHANNEL_CH3
2226 * @arg @ref LL_TIM_CHANNEL_CH4
2227 * @arg @ref LL_TIM_CHANNEL_CH5
2228 * @arg @ref LL_TIM_CHANNEL_CH6
2229 * @retval Returned value can be one of the following values:
2230 * @arg @ref LL_TIM_OCMODE_FROZEN
2231 * @arg @ref LL_TIM_OCMODE_ACTIVE
2232 * @arg @ref LL_TIM_OCMODE_INACTIVE
2233 * @arg @ref LL_TIM_OCMODE_TOGGLE
2234 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2235 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2236 * @arg @ref LL_TIM_OCMODE_PWM1
2237 * @arg @ref LL_TIM_OCMODE_PWM2
2238 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2239 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2240 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2241 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2242 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2243 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2244 */
2245__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2246{
2247 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2248 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2249 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2250}
2251
2252/**
2253 * @brief Set the polarity of an output channel.
2254 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2255 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2256 * CCER CC2P LL_TIM_OC_SetPolarity\n
2257 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2258 * CCER CC3P LL_TIM_OC_SetPolarity\n
2259 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2260 * CCER CC4P LL_TIM_OC_SetPolarity\n
2261 * CCER CC5P LL_TIM_OC_SetPolarity\n
2262 * CCER CC6P LL_TIM_OC_SetPolarity
2263 * @param TIMx Timer instance
2264 * @param Channel This parameter can be one of the following values:
2265 * @arg @ref LL_TIM_CHANNEL_CH1
2266 * @arg @ref LL_TIM_CHANNEL_CH1N
2267 * @arg @ref LL_TIM_CHANNEL_CH2
2268 * @arg @ref LL_TIM_CHANNEL_CH2N
2269 * @arg @ref LL_TIM_CHANNEL_CH3
2270 * @arg @ref LL_TIM_CHANNEL_CH3N
2271 * @arg @ref LL_TIM_CHANNEL_CH4
2272 * @arg @ref LL_TIM_CHANNEL_CH5
2273 * @arg @ref LL_TIM_CHANNEL_CH6
2274 * @param Polarity This parameter can be one of the following values:
2275 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2276 * @arg @ref LL_TIM_OCPOLARITY_LOW
2277 * @retval None
2278 */
2279__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2280{
2281 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2282 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2283}
2284
2285/**
2286 * @brief Get the polarity of an output channel.
2287 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2288 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2289 * CCER CC2P LL_TIM_OC_GetPolarity\n
2290 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2291 * CCER CC3P LL_TIM_OC_GetPolarity\n
2292 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2293 * CCER CC4P LL_TIM_OC_GetPolarity\n
2294 * CCER CC5P LL_TIM_OC_GetPolarity\n
2295 * CCER CC6P LL_TIM_OC_GetPolarity
2296 * @param TIMx Timer instance
2297 * @param Channel This parameter can be one of the following values:
2298 * @arg @ref LL_TIM_CHANNEL_CH1
2299 * @arg @ref LL_TIM_CHANNEL_CH1N
2300 * @arg @ref LL_TIM_CHANNEL_CH2
2301 * @arg @ref LL_TIM_CHANNEL_CH2N
2302 * @arg @ref LL_TIM_CHANNEL_CH3
2303 * @arg @ref LL_TIM_CHANNEL_CH3N
2304 * @arg @ref LL_TIM_CHANNEL_CH4
2305 * @arg @ref LL_TIM_CHANNEL_CH5
2306 * @arg @ref LL_TIM_CHANNEL_CH6
2307 * @retval Returned value can be one of the following values:
2308 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2309 * @arg @ref LL_TIM_OCPOLARITY_LOW
2310 */
2311__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2312{
2313 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2314 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2315}
2316
2317/**
2318 * @brief Set the IDLE state of an output channel
2319 * @note This function is significant only for the timer instances
2320 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2321 * can be used to check whether or not a timer instance provides
2322 * a break input.
2323 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2324 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2325 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2326 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2327 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2328 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2329 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2330 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2331 * CR2 OIS6 LL_TIM_OC_SetIdleState
2332 * @param TIMx Timer instance
2333 * @param Channel This parameter can be one of the following values:
2334 * @arg @ref LL_TIM_CHANNEL_CH1
2335 * @arg @ref LL_TIM_CHANNEL_CH1N
2336 * @arg @ref LL_TIM_CHANNEL_CH2
2337 * @arg @ref LL_TIM_CHANNEL_CH2N
2338 * @arg @ref LL_TIM_CHANNEL_CH3
2339 * @arg @ref LL_TIM_CHANNEL_CH3N
2340 * @arg @ref LL_TIM_CHANNEL_CH4
2341 * @arg @ref LL_TIM_CHANNEL_CH5
2342 * @arg @ref LL_TIM_CHANNEL_CH6
2343 * @param IdleState This parameter can be one of the following values:
2344 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2345 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2346 * @retval None
2347 */
2348__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2349{
2350 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2351 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2352}
2353
2354/**
2355 * @brief Get the IDLE state of an output channel
2356 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2357 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2358 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2359 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2360 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2361 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2362 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2363 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2364 * CR2 OIS6 LL_TIM_OC_GetIdleState
2365 * @param TIMx Timer instance
2366 * @param Channel This parameter can be one of the following values:
2367 * @arg @ref LL_TIM_CHANNEL_CH1
2368 * @arg @ref LL_TIM_CHANNEL_CH1N
2369 * @arg @ref LL_TIM_CHANNEL_CH2
2370 * @arg @ref LL_TIM_CHANNEL_CH2N
2371 * @arg @ref LL_TIM_CHANNEL_CH3
2372 * @arg @ref LL_TIM_CHANNEL_CH3N
2373 * @arg @ref LL_TIM_CHANNEL_CH4
2374 * @arg @ref LL_TIM_CHANNEL_CH5
2375 * @arg @ref LL_TIM_CHANNEL_CH6
2376 * @retval Returned value can be one of the following values:
2377 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2378 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2379 */
2380__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2381{
2382 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2383 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2384}
2385
2386/**
2387 * @brief Enable fast mode for the output channel.
2388 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2389 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2390 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2391 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2392 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2393 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2394 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2395 * @param TIMx Timer instance
2396 * @param Channel This parameter can be one of the following values:
2397 * @arg @ref LL_TIM_CHANNEL_CH1
2398 * @arg @ref LL_TIM_CHANNEL_CH2
2399 * @arg @ref LL_TIM_CHANNEL_CH3
2400 * @arg @ref LL_TIM_CHANNEL_CH4
2401 * @arg @ref LL_TIM_CHANNEL_CH5
2402 * @arg @ref LL_TIM_CHANNEL_CH6
2403 * @retval None
2404 */
2405__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2406{
2407 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2408 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2409 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2410
2411}
2412
2413/**
2414 * @brief Disable fast mode for the output channel.
2415 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2416 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2417 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2418 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2419 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2420 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2421 * @param TIMx Timer instance
2422 * @param Channel This parameter can be one of the following values:
2423 * @arg @ref LL_TIM_CHANNEL_CH1
2424 * @arg @ref LL_TIM_CHANNEL_CH2
2425 * @arg @ref LL_TIM_CHANNEL_CH3
2426 * @arg @ref LL_TIM_CHANNEL_CH4
2427 * @arg @ref LL_TIM_CHANNEL_CH5
2428 * @arg @ref LL_TIM_CHANNEL_CH6
2429 * @retval None
2430 */
2431__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2432{
2433 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2434 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2435 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2436
2437}
2438
2439/**
2440 * @brief Indicates whether fast mode is enabled for the output channel.
2441 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2442 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2443 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2444 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2445 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2446 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2447 * @param TIMx Timer instance
2448 * @param Channel This parameter can be one of the following values:
2449 * @arg @ref LL_TIM_CHANNEL_CH1
2450 * @arg @ref LL_TIM_CHANNEL_CH2
2451 * @arg @ref LL_TIM_CHANNEL_CH3
2452 * @arg @ref LL_TIM_CHANNEL_CH4
2453 * @arg @ref LL_TIM_CHANNEL_CH5
2454 * @arg @ref LL_TIM_CHANNEL_CH6
2455 * @retval State of bit (1 or 0).
2456 */
2457__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2458{
2459 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2460 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2461 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2462 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2463}
2464
2465/**
2466 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2467 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2468 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2469 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2470 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2471 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2472 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2473 * @param TIMx Timer instance
2474 * @param Channel This parameter can be one of the following values:
2475 * @arg @ref LL_TIM_CHANNEL_CH1
2476 * @arg @ref LL_TIM_CHANNEL_CH2
2477 * @arg @ref LL_TIM_CHANNEL_CH3
2478 * @arg @ref LL_TIM_CHANNEL_CH4
2479 * @arg @ref LL_TIM_CHANNEL_CH5
2480 * @arg @ref LL_TIM_CHANNEL_CH6
2481 * @retval None
2482 */
2483__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2484{
2485 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2486 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2487 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2488}
2489
2490/**
2491 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2492 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2493 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2494 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2495 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2496 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2497 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2498 * @param TIMx Timer instance
2499 * @param Channel This parameter can be one of the following values:
2500 * @arg @ref LL_TIM_CHANNEL_CH1
2501 * @arg @ref LL_TIM_CHANNEL_CH2
2502 * @arg @ref LL_TIM_CHANNEL_CH3
2503 * @arg @ref LL_TIM_CHANNEL_CH4
2504 * @arg @ref LL_TIM_CHANNEL_CH5
2505 * @arg @ref LL_TIM_CHANNEL_CH6
2506 * @retval None
2507 */
2508__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2509{
2510 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2511 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2512 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2513}
2514
2515/**
2516 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2517 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2518 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2519 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2520 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2521 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2522 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2523 * @param TIMx Timer instance
2524 * @param Channel This parameter can be one of the following values:
2525 * @arg @ref LL_TIM_CHANNEL_CH1
2526 * @arg @ref LL_TIM_CHANNEL_CH2
2527 * @arg @ref LL_TIM_CHANNEL_CH3
2528 * @arg @ref LL_TIM_CHANNEL_CH4
2529 * @arg @ref LL_TIM_CHANNEL_CH5
2530 * @arg @ref LL_TIM_CHANNEL_CH6
2531 * @retval State of bit (1 or 0).
2532 */
2533__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2534{
2535 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2536 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2537 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2538 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2539}
2540
2541/**
2542 * @brief Enable clearing the output channel on an external event.
2543 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2544 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2545 * or not a timer instance can clear the OCxREF signal on an external event.
2546 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2547 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2548 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2549 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2550 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2551 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2552 * @param TIMx Timer instance
2553 * @param Channel This parameter can be one of the following values:
2554 * @arg @ref LL_TIM_CHANNEL_CH1
2555 * @arg @ref LL_TIM_CHANNEL_CH2
2556 * @arg @ref LL_TIM_CHANNEL_CH3
2557 * @arg @ref LL_TIM_CHANNEL_CH4
2558 * @arg @ref LL_TIM_CHANNEL_CH5
2559 * @arg @ref LL_TIM_CHANNEL_CH6
2560 * @retval None
2561 */
2562__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2563{
2564 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2565 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2566 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2567}
2568
2569/**
2570 * @brief Disable clearing the output channel on an external event.
2571 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2572 * or not a timer instance can clear the OCxREF signal on an external event.
2573 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2574 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2575 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2576 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2577 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2578 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2579 * @param TIMx Timer instance
2580 * @param Channel This parameter can be one of the following values:
2581 * @arg @ref LL_TIM_CHANNEL_CH1
2582 * @arg @ref LL_TIM_CHANNEL_CH2
2583 * @arg @ref LL_TIM_CHANNEL_CH3
2584 * @arg @ref LL_TIM_CHANNEL_CH4
2585 * @arg @ref LL_TIM_CHANNEL_CH5
2586 * @arg @ref LL_TIM_CHANNEL_CH6
2587 * @retval None
2588 */
2589__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2590{
2591 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2592 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2593 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2594}
2595
2596/**
2597 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2598 * @note This function enables clearing the output channel on an external event.
2599 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2600 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2601 * or not a timer instance can clear the OCxREF signal on an external event.
2602 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2603 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2604 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2605 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2606 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2607 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2608 * @param TIMx Timer instance
2609 * @param Channel This parameter can be one of the following values:
2610 * @arg @ref LL_TIM_CHANNEL_CH1
2611 * @arg @ref LL_TIM_CHANNEL_CH2
2612 * @arg @ref LL_TIM_CHANNEL_CH3
2613 * @arg @ref LL_TIM_CHANNEL_CH4
2614 * @arg @ref LL_TIM_CHANNEL_CH5
2615 * @arg @ref LL_TIM_CHANNEL_CH6
2616 * @retval State of bit (1 or 0).
2617 */
2618__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2619{
2620 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2621 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2622 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2623 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2624}
2625
2626/**
2627 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2628 * the Ocx and OCxN signals).
2629 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2630 * dead-time insertion feature is supported by a timer instance.
2631 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2632 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2633 * @param TIMx Timer instance
2634 * @param DeadTime between Min_Data=0 and Max_Data=255
2635 * @retval None
2636 */
2637__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2638{
2639 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2640}
2641
2642/**
2643 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2644 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2645 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2646 * whether or not a timer instance supports a 32 bits counter.
2647 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2648 * output channel 1 is supported by a timer instance.
2649 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2650 * @param TIMx Timer instance
2651 * @param CompareValue between Min_Data=0 and Max_Data=65535
2652 * @retval None
2653 */
2654__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2655{
2656 WRITE_REG(TIMx->CCR1, CompareValue);
2657}
2658
2659/**
2660 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2661 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2662 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2663 * whether or not a timer instance supports a 32 bits counter.
2664 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2665 * output channel 2 is supported by a timer instance.
2666 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2667 * @param TIMx Timer instance
2668 * @param CompareValue between Min_Data=0 and Max_Data=65535
2669 * @retval None
2670 */
2671__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2672{
2673 WRITE_REG(TIMx->CCR2, CompareValue);
2674}
2675
2676/**
2677 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2678 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2679 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2680 * whether or not a timer instance supports a 32 bits counter.
2681 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2682 * output channel is supported by a timer instance.
2683 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2684 * @param TIMx Timer instance
2685 * @param CompareValue between Min_Data=0 and Max_Data=65535
2686 * @retval None
2687 */
2688__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2689{
2690 WRITE_REG(TIMx->CCR3, CompareValue);
2691}
2692
2693/**
2694 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2695 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2696 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2697 * whether or not a timer instance supports a 32 bits counter.
2698 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2699 * output channel 4 is supported by a timer instance.
2700 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2701 * @param TIMx Timer instance
2702 * @param CompareValue between Min_Data=0 and Max_Data=65535
2703 * @retval None
2704 */
2705__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2706{
2707 WRITE_REG(TIMx->CCR4, CompareValue);
2708}
2709
2710/**
2711 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2712 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2713 * output channel 5 is supported by a timer instance.
2714 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2715 * @param TIMx Timer instance
2716 * @param CompareValue between Min_Data=0 and Max_Data=65535
2717 * @retval None
2718 */
2719__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2720{
2721 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2722}
2723
2724/**
2725 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2726 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2727 * output channel 6 is supported by a timer instance.
2728 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2729 * @param TIMx Timer instance
2730 * @param CompareValue between Min_Data=0 and Max_Data=65535
2731 * @retval None
2732 */
2733__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2734{
2735 WRITE_REG(TIMx->CCR6, CompareValue);
2736}
2737
2738/**
2739 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2740 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2741 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2742 * whether or not a timer instance supports a 32 bits counter.
2743 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2744 * output channel 1 is supported by a timer instance.
2745 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2746 * @param TIMx Timer instance
2747 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2748 */
2749__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2750{
2751 return (uint32_t)(READ_REG(TIMx->CCR1));
2752}
2753
2754/**
2755 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2756 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2757 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2758 * whether or not a timer instance supports a 32 bits counter.
2759 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2760 * output channel 2 is supported by a timer instance.
2761 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2762 * @param TIMx Timer instance
2763 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2764 */
2765__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2766{
2767 return (uint32_t)(READ_REG(TIMx->CCR2));
2768}
2769
2770/**
2771 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2772 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2773 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2774 * whether or not a timer instance supports a 32 bits counter.
2775 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2776 * output channel 3 is supported by a timer instance.
2777 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2778 * @param TIMx Timer instance
2779 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2780 */
2781__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2782{
2783 return (uint32_t)(READ_REG(TIMx->CCR3));
2784}
2785
2786/**
2787 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2788 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2789 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2790 * whether or not a timer instance supports a 32 bits counter.
2791 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2792 * output channel 4 is supported by a timer instance.
2793 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2794 * @param TIMx Timer instance
2795 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2796 */
2797__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2798{
2799 return (uint32_t)(READ_REG(TIMx->CCR4));
2800}
2801
2802/**
2803 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2804 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2805 * output channel 5 is supported by a timer instance.
2806 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2807 * @param TIMx Timer instance
2808 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2809 */
2810__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2811{
2812 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2813}
2814
2815/**
2816 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2817 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2818 * output channel 6 is supported by a timer instance.
2819 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2820 * @param TIMx Timer instance
2821 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2822 */
2823__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2824{
2825 return (uint32_t)(READ_REG(TIMx->CCR6));
2826}
2827
2828/**
2829 * @brief Select on which reference signal the OC5REF is combined to.
2830 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2831 * whether or not a timer instance supports the combined 3-phase PWM mode.
2832 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2833 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2834 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2835 * @param TIMx Timer instance
2836 * @param GroupCH5 This parameter can be a combination of the following values:
2837 * @arg @ref LL_TIM_GROUPCH5_NONE
2838 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2839 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2840 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2841 * @retval None
2842 */
2843__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2844{
2845 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2846}
2847
2848/**
2849 * @}
2850 */
2851
2852/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2853 * @{
2854 */
2855/**
2856 * @brief Configure input channel.
2857 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2858 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2859 * CCMR1 IC1F LL_TIM_IC_Config\n
2860 * CCMR1 CC2S LL_TIM_IC_Config\n
2861 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2862 * CCMR1 IC2F LL_TIM_IC_Config\n
2863 * CCMR2 CC3S LL_TIM_IC_Config\n
2864 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2865 * CCMR2 IC3F LL_TIM_IC_Config\n
2866 * CCMR2 CC4S LL_TIM_IC_Config\n
2867 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2868 * CCMR2 IC4F LL_TIM_IC_Config\n
2869 * CCER CC1P LL_TIM_IC_Config\n
2870 * CCER CC1NP LL_TIM_IC_Config\n
2871 * CCER CC2P LL_TIM_IC_Config\n
2872 * CCER CC2NP LL_TIM_IC_Config\n
2873 * CCER CC3P LL_TIM_IC_Config\n
2874 * CCER CC3NP LL_TIM_IC_Config\n
2875 * CCER CC4P LL_TIM_IC_Config\n
2876 * CCER CC4NP LL_TIM_IC_Config
2877 * @param TIMx Timer instance
2878 * @param Channel This parameter can be one of the following values:
2879 * @arg @ref LL_TIM_CHANNEL_CH1
2880 * @arg @ref LL_TIM_CHANNEL_CH2
2881 * @arg @ref LL_TIM_CHANNEL_CH3
2882 * @arg @ref LL_TIM_CHANNEL_CH4
2883 * @param Configuration This parameter must be a combination of all the following values:
2884 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2885 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2886 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2887 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2888 * @retval None
2889 */
2890__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2891{
2892 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2893 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2894 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2895 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2896 << SHIFT_TAB_ICxx[iChannel]);
2897 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2898 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2899}
2900
2901/**
2902 * @brief Set the active input.
2903 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2904 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2905 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2906 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2907 * @param TIMx Timer instance
2908 * @param Channel This parameter can be one of the following values:
2909 * @arg @ref LL_TIM_CHANNEL_CH1
2910 * @arg @ref LL_TIM_CHANNEL_CH2
2911 * @arg @ref LL_TIM_CHANNEL_CH3
2912 * @arg @ref LL_TIM_CHANNEL_CH4
2913 * @param ICActiveInput This parameter can be one of the following values:
2914 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2915 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2916 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2917 * @retval None
2918 */
2919__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2920{
2921 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2922 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2923 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2924}
2925
2926/**
2927 * @brief Get the current active input.
2928 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2929 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2930 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2931 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2932 * @param TIMx Timer instance
2933 * @param Channel This parameter can be one of the following values:
2934 * @arg @ref LL_TIM_CHANNEL_CH1
2935 * @arg @ref LL_TIM_CHANNEL_CH2
2936 * @arg @ref LL_TIM_CHANNEL_CH3
2937 * @arg @ref LL_TIM_CHANNEL_CH4
2938 * @retval Returned value can be one of the following values:
2939 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2940 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2941 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2942 */
2943__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2944{
2945 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2946 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2947 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2948}
2949
2950/**
2951 * @brief Set the prescaler of input channel.
2952 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2953 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2954 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2955 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2956 * @param TIMx Timer instance
2957 * @param Channel This parameter can be one of the following values:
2958 * @arg @ref LL_TIM_CHANNEL_CH1
2959 * @arg @ref LL_TIM_CHANNEL_CH2
2960 * @arg @ref LL_TIM_CHANNEL_CH3
2961 * @arg @ref LL_TIM_CHANNEL_CH4
2962 * @param ICPrescaler This parameter can be one of the following values:
2963 * @arg @ref LL_TIM_ICPSC_DIV1
2964 * @arg @ref LL_TIM_ICPSC_DIV2
2965 * @arg @ref LL_TIM_ICPSC_DIV4
2966 * @arg @ref LL_TIM_ICPSC_DIV8
2967 * @retval None
2968 */
2969__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2970{
2971 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2972 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2973 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2974}
2975
2976/**
2977 * @brief Get the current prescaler value acting on an input channel.
2978 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2979 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2980 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2981 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2982 * @param TIMx Timer instance
2983 * @param Channel This parameter can be one of the following values:
2984 * @arg @ref LL_TIM_CHANNEL_CH1
2985 * @arg @ref LL_TIM_CHANNEL_CH2
2986 * @arg @ref LL_TIM_CHANNEL_CH3
2987 * @arg @ref LL_TIM_CHANNEL_CH4
2988 * @retval Returned value can be one of the following values:
2989 * @arg @ref LL_TIM_ICPSC_DIV1
2990 * @arg @ref LL_TIM_ICPSC_DIV2
2991 * @arg @ref LL_TIM_ICPSC_DIV4
2992 * @arg @ref LL_TIM_ICPSC_DIV8
2993 */
2994__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2995{
2996 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2997 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2998 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2999}
3000
3001/**
3002 * @brief Set the input filter duration.
3003 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3004 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3005 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3006 * CCMR2 IC4F LL_TIM_IC_SetFilter
3007 * @param TIMx Timer instance
3008 * @param Channel This parameter can be one of the following values:
3009 * @arg @ref LL_TIM_CHANNEL_CH1
3010 * @arg @ref LL_TIM_CHANNEL_CH2
3011 * @arg @ref LL_TIM_CHANNEL_CH3
3012 * @arg @ref LL_TIM_CHANNEL_CH4
3013 * @param ICFilter This parameter can be one of the following values:
3014 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3015 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3016 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3017 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3018 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3019 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3020 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3021 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3022 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3023 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3024 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3025 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3026 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3027 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3028 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3029 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3030 * @retval None
3031 */
3032__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3033{
3034 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3035 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3036 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3037}
3038
3039/**
3040 * @brief Get the input filter duration.
3041 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3042 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3043 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3044 * CCMR2 IC4F LL_TIM_IC_GetFilter
3045 * @param TIMx Timer instance
3046 * @param Channel This parameter can be one of the following values:
3047 * @arg @ref LL_TIM_CHANNEL_CH1
3048 * @arg @ref LL_TIM_CHANNEL_CH2
3049 * @arg @ref LL_TIM_CHANNEL_CH3
3050 * @arg @ref LL_TIM_CHANNEL_CH4
3051 * @retval Returned value can be one of the following values:
3052 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3053 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3054 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3055 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3056 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3057 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3058 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3059 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3060 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3061 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3062 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3063 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3064 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3065 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3066 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3067 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3068 */
3069__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3070{
3071 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3072 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3073 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3074}
3075
3076/**
3077 * @brief Set the input channel polarity.
3078 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3079 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3080 * CCER CC2P LL_TIM_IC_SetPolarity\n
3081 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3082 * CCER CC3P LL_TIM_IC_SetPolarity\n
3083 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3084 * CCER CC4P LL_TIM_IC_SetPolarity\n
3085 * CCER CC4NP LL_TIM_IC_SetPolarity
3086 * @param TIMx Timer instance
3087 * @param Channel This parameter can be one of the following values:
3088 * @arg @ref LL_TIM_CHANNEL_CH1
3089 * @arg @ref LL_TIM_CHANNEL_CH2
3090 * @arg @ref LL_TIM_CHANNEL_CH3
3091 * @arg @ref LL_TIM_CHANNEL_CH4
3092 * @param ICPolarity This parameter can be one of the following values:
3093 * @arg @ref LL_TIM_IC_POLARITY_RISING
3094 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3095 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3096 * @retval None
3097 */
3098__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3099{
3100 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3101 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3102 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3103}
3104
3105/**
3106 * @brief Get the current input channel polarity.
3107 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3108 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3109 * CCER CC2P LL_TIM_IC_GetPolarity\n
3110 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3111 * CCER CC3P LL_TIM_IC_GetPolarity\n
3112 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3113 * CCER CC4P LL_TIM_IC_GetPolarity\n
3114 * CCER CC4NP LL_TIM_IC_GetPolarity
3115 * @param TIMx Timer instance
3116 * @param Channel This parameter can be one of the following values:
3117 * @arg @ref LL_TIM_CHANNEL_CH1
3118 * @arg @ref LL_TIM_CHANNEL_CH2
3119 * @arg @ref LL_TIM_CHANNEL_CH3
3120 * @arg @ref LL_TIM_CHANNEL_CH4
3121 * @retval Returned value can be one of the following values:
3122 * @arg @ref LL_TIM_IC_POLARITY_RISING
3123 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3124 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3125 */
3126__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3127{
3128 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3129 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3130 SHIFT_TAB_CCxP[iChannel]);
3131}
3132
3133/**
3134 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3135 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3136 * a timer instance provides an XOR input.
3137 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3138 * @param TIMx Timer instance
3139 * @retval None
3140 */
3141__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3142{
3143 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3144}
3145
3146/**
3147 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3148 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3149 * a timer instance provides an XOR input.
3150 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3151 * @param TIMx Timer instance
3152 * @retval None
3153 */
3154__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3155{
3156 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3157}
3158
3159/**
3160 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3161 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3162 * a timer instance provides an XOR input.
3163 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3164 * @param TIMx Timer instance
3165 * @retval State of bit (1 or 0).
3166 */
3167__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3168{
3169 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3170}
3171
3172/**
3173 * @brief Get captured value for input channel 1.
3174 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3175 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3176 * whether or not a timer instance supports a 32 bits counter.
3177 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3178 * input channel 1 is supported by a timer instance.
3179 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3180 * @param TIMx Timer instance
3181 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3182 */
3183__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3184{
3185 return (uint32_t)(READ_REG(TIMx->CCR1));
3186}
3187
3188/**
3189 * @brief Get captured value for input channel 2.
3190 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3191 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3192 * whether or not a timer instance supports a 32 bits counter.
3193 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3194 * input channel 2 is supported by a timer instance.
3195 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3196 * @param TIMx Timer instance
3197 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3198 */
3199__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3200{
3201 return (uint32_t)(READ_REG(TIMx->CCR2));
3202}
3203
3204/**
3205 * @brief Get captured value for input channel 3.
3206 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3207 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3208 * whether or not a timer instance supports a 32 bits counter.
3209 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3210 * input channel 3 is supported by a timer instance.
3211 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3212 * @param TIMx Timer instance
3213 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3214 */
3215__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3216{
3217 return (uint32_t)(READ_REG(TIMx->CCR3));
3218}
3219
3220/**
3221 * @brief Get captured value for input channel 4.
3222 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3223 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3224 * whether or not a timer instance supports a 32 bits counter.
3225 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3226 * input channel 4 is supported by a timer instance.
3227 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3228 * @param TIMx Timer instance
3229 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3230 */
3231__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3232{
3233 return (uint32_t)(READ_REG(TIMx->CCR4));
3234}
3235
3236/**
3237 * @}
3238 */
3239
3240/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3241 * @{
3242 */
3243/**
3244 * @brief Enable external clock mode 2.
3245 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3246 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3247 * whether or not a timer instance supports external clock mode2.
3248 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3249 * @param TIMx Timer instance
3250 * @retval None
3251 */
3252__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3253{
3254 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3255}
3256
3257/**
3258 * @brief Disable external clock mode 2.
3259 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3260 * whether or not a timer instance supports external clock mode2.
3261 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3262 * @param TIMx Timer instance
3263 * @retval None
3264 */
3265__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3266{
3267 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3268}
3269
3270/**
3271 * @brief Indicate whether external clock mode 2 is enabled.
3272 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3273 * whether or not a timer instance supports external clock mode2.
3274 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3275 * @param TIMx Timer instance
3276 * @retval State of bit (1 or 0).
3277 */
3278__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3279{
3280 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3281}
3282
3283/**
3284 * @brief Set the clock source of the counter clock.
3285 * @note when selected clock source is external clock mode 1, the timer input
3286 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3287 * function. This timer input must be configured by calling
3288 * the @ref LL_TIM_IC_Config() function.
3289 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3290 * whether or not a timer instance supports external clock mode1.
3291 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3292 * whether or not a timer instance supports external clock mode2.
3293 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3294 * SMCR ECE LL_TIM_SetClockSource
3295 * @param TIMx Timer instance
3296 * @param ClockSource This parameter can be one of the following values:
3297 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3298 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3299 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3300 * @retval None
3301 */
3302__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3303{
3304 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3305}
3306
3307/**
3308 * @brief Set the encoder interface mode.
3309 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3310 * whether or not a timer instance supports the encoder mode.
3311 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3312 * @param TIMx Timer instance
3313 * @param EncoderMode This parameter can be one of the following values:
3314 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3315 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3316 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3317 * @retval None
3318 */
3319__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3320{
3321 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3322}
3323
3324/**
3325 * @}
3326 */
3327
3328/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3329 * @{
3330 */
3331/**
3332 * @brief Set the trigger output (TRGO) used for timer synchronization .
3333 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3334 * whether or not a timer instance can operate as a master timer.
3335 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3336 * @param TIMx Timer instance
3337 * @param TimerSynchronization This parameter can be one of the following values:
3338 * @arg @ref LL_TIM_TRGO_RESET
3339 * @arg @ref LL_TIM_TRGO_ENABLE
3340 * @arg @ref LL_TIM_TRGO_UPDATE
3341 * @arg @ref LL_TIM_TRGO_CC1IF
3342 * @arg @ref LL_TIM_TRGO_OC1REF
3343 * @arg @ref LL_TIM_TRGO_OC2REF
3344 * @arg @ref LL_TIM_TRGO_OC3REF
3345 * @arg @ref LL_TIM_TRGO_OC4REF
3346 * @retval None
3347 */
3348__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3349{
3350 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3351}
3352
3353/**
3354 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3355 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3356 * whether or not a timer instance can be used for ADC synchronization.
3357 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3358 * @param TIMx Timer Instance
3359 * @param ADCSynchronization This parameter can be one of the following values:
3360 * @arg @ref LL_TIM_TRGO2_RESET
3361 * @arg @ref LL_TIM_TRGO2_ENABLE
3362 * @arg @ref LL_TIM_TRGO2_UPDATE
3363 * @arg @ref LL_TIM_TRGO2_CC1F
3364 * @arg @ref LL_TIM_TRGO2_OC1
3365 * @arg @ref LL_TIM_TRGO2_OC2
3366 * @arg @ref LL_TIM_TRGO2_OC3
3367 * @arg @ref LL_TIM_TRGO2_OC4
3368 * @arg @ref LL_TIM_TRGO2_OC5
3369 * @arg @ref LL_TIM_TRGO2_OC6
3370 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3371 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3372 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3373 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3374 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3375 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3376 * @retval None
3377 */
3378__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3379{
3380 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3381}
3382
3383/**
3384 * @brief Set the synchronization mode of a slave timer.
3385 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3386 * a timer instance can operate as a slave timer.
3387 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3388 * @param TIMx Timer instance
3389 * @param SlaveMode This parameter can be one of the following values:
3390 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3391 * @arg @ref LL_TIM_SLAVEMODE_RESET
3392 * @arg @ref LL_TIM_SLAVEMODE_GATED
3393 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3394 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3395 * @retval None
3396 */
3397__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3398{
3399 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3400}
3401
3402/**
3403 * @brief Set the selects the trigger input to be used to synchronize the counter.
3404 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3405 * a timer instance can operate as a slave timer.
3406 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3407 * @param TIMx Timer instance
3408 * @param TriggerInput This parameter can be one of the following values:
3409 * @arg @ref LL_TIM_TS_ITR0
3410 * @arg @ref LL_TIM_TS_ITR1
3411 * @arg @ref LL_TIM_TS_ITR2
3412 * @arg @ref LL_TIM_TS_ITR3
3413 * @arg @ref LL_TIM_TS_ITR4
3414 * @arg @ref LL_TIM_TS_ITR5
3415 * @arg @ref LL_TIM_TS_ITR6
3416 * @arg @ref LL_TIM_TS_ITR7
3417 * @arg @ref LL_TIM_TS_ITR8 (*)
3418 * @arg @ref LL_TIM_TS_ITR9 (*)
3419 * @arg @ref LL_TIM_TS_ITR10 (*)
3420 * @arg @ref LL_TIM_TS_ITR11 (*)
3421 * @arg @ref LL_TIM_TS_ITR12 (*)
3422 * @arg @ref LL_TIM_TS_ITR13 (*)
3423 * @arg @ref LL_TIM_TS_TI1F_ED
3424 * @arg @ref LL_TIM_TS_TI1FP1
3425 * @arg @ref LL_TIM_TS_TI2FP2
3426 * @arg @ref LL_TIM_TS_ETRF
3427 *
3428 * (*) Value not defined in all devices.
3429 * @retval None
3430 */
3431__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3432{
3433 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3434}
3435
3436/**
3437 * @brief Enable the Master/Slave mode.
3438 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3439 * a timer instance can operate as a slave timer.
3440 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3441 * @param TIMx Timer instance
3442 * @retval None
3443 */
3444__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3445{
3446 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3447}
3448
3449/**
3450 * @brief Disable the Master/Slave mode.
3451 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3452 * a timer instance can operate as a slave timer.
3453 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3454 * @param TIMx Timer instance
3455 * @retval None
3456 */
3457__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3458{
3459 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3460}
3461
3462/**
3463 * @brief Indicates whether the Master/Slave mode is enabled.
3464 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3465 * a timer instance can operate as a slave timer.
3466 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3467 * @param TIMx Timer instance
3468 * @retval State of bit (1 or 0).
3469 */
3470__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3471{
3472 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3473}
3474
3475/**
3476 * @brief Configure the external trigger (ETR) input.
3477 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3478 * a timer instance provides an external trigger input.
3479 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3480 * SMCR ETPS LL_TIM_ConfigETR\n
3481 * SMCR ETF LL_TIM_ConfigETR
3482 * @param TIMx Timer instance
3483 * @param ETRPolarity This parameter can be one of the following values:
3484 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3485 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3486 * @param ETRPrescaler This parameter can be one of the following values:
3487 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3488 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3489 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3490 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3491 * @param ETRFilter This parameter can be one of the following values:
3492 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3493 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3494 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3495 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3496 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3497 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3498 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3499 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3500 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3501 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3502 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3503 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3504 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3505 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3506 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3507 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3508 * @retval None
3509 */
3510__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3511 uint32_t ETRFilter)
3512{
3513 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3514}
3515
3516/**
3517 * @brief Select the external trigger (ETR) input source.
3518 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3519 * not a timer instance supports ETR source selection.
3520 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3521 * @param TIMx Timer instance
3522 * @param ETRSource This parameter can be one of the following values:
3523 * For TIM1, the parameter is one of the following values:
3524 * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO
3525 * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output
3526 * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output
3527 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
3528 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
3529 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
3530 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
3531 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
3532 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
3533 *
3534 * For TIM2, the parameter is one of the following values:
3535 * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO
3536 * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output
3537 * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output
3538 * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE
3539 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
3540 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
3541 *
3542 * For TIM3, the parameter is one of the following values:
3543 * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO
3544 * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output
3545 *
3546 * For TIM5, the parameter is one of the following values:
3547 * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO
3548 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3549 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3550 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3551 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3552 *
3553 * For TIM8, the parameter is one of the following values:
3554 * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO
3555 * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output
3556 * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output
3557 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
3558 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
3559 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
3560 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
3561 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
3562 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
3563 *
3564 * For TIM23, the parameter is one of the following values: (*)
3565 * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO
3566 * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output
3567 * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output
3568 *
3569 * For TIM24, the parameter is one of the following values: (*)
3570 * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO
3571 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
3572 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
3573 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
3574 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
3575 *
3576 * (*) Value not defined in all devices.
3577 * @retval None
3578 */
3579__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3580{
3581 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3582}
3583
3584/**
3585 * @}
3586 */
3587
3588/** @defgroup TIM_LL_EF_Break_Function Break function configuration
3589 * @{
3590 */
3591/**
3592 * @brief Enable the break function.
3593 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3594 * a timer instance provides a break input.
3595 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3596 * @param TIMx Timer instance
3597 * @retval None
3598 */
3599__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3600{
3601 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3602}
3603
3604/**
3605 * @brief Disable the break function.
3606 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3607 * @param TIMx Timer instance
3608 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3609 * a timer instance provides a break input.
3610 * @retval None
3611 */
3612__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3613{
3614 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3615}
3616
3617#if defined(TIM_BDTR_BKBID)
3618/**
3619 * @brief Configure the break input.
3620 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3621 * a timer instance provides a break input.
3622 * @note Bidirectional mode is only supported by advanced timer instances.
3623 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3624 * a timer instance is an advanced-control timer.
3625 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3626 * in input mode and in open drain output mode. Any active Break event will
3627 * assert a low logic level on the Break input to indicate an internal break
3628 * event to external devices.
3629 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3630 * LL_TIM_BREAK_AFMODE_INPUT.
3631 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3632 * BDTR BKF LL_TIM_ConfigBRK\n
3633 * BDTR BKBID LL_TIM_ConfigBRK
3634 * @param TIMx Timer instance
3635 * @param BreakPolarity This parameter can be one of the following values:
3636 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3637 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3638 * @param BreakFilter This parameter can be one of the following values:
3639 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3640 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3641 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3642 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3643 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3644 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3645 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3646 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3647 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3648 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3649 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3650 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3651 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3652 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3653 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3654 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3655 * @param BreakAFMode This parameter can be one of the following values:
3656 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3657 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3658 * @retval None
3659 */
3660__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3661 uint32_t BreakAFMode)
3662{
3663 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3664}
3665
3666#else
3667/**
3668 * @brief Configure the break input.
3669 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3670 * a timer instance provides a break input.
3671 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3672 * BDTR BKF LL_TIM_ConfigBRK
3673 * @param TIMx Timer instance
3674 * @param BreakPolarity This parameter can be one of the following values:
3675 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3676 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3677 * @param BreakFilter This parameter can be one of the following values:
3678 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3679 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3680 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3681 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3682 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3683 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3684 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3685 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3686 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3687 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3688 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3689 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3690 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3691 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3692 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3693 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3694 * @retval None
3695 */
3696__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3697 uint32_t BreakFilter)
3698{
3699 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3700}
3701
3702#endif /* TIM_BDTR_BKBID */
3703#if defined(TIM_BDTR_BKBID)
3704/**
3705 * @brief Disarm the break input (when it operates in bidirectional mode).
3706 * @note The break input can be disarmed only when it is configured in
3707 * bidirectional mode and when when MOE is reset.
3708 * @note Purpose is to be able to have the input voltage back to high-state,
3709 * whatever the time constant on the output .
3710 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3711 * @param TIMx Timer instance
3712 * @retval None
3713 */
3714__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3715{
3716 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3717}
3718
3719#endif /*TIM_BDTR_BKBID */
3720/**
3721 * @brief Enable the break 2 function.
3722 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3723 * a timer instance provides a second break input.
3724 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3725 * @param TIMx Timer instance
3726 * @retval None
3727 */
3728__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3729{
3730 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3731}
3732
3733/**
3734 * @brief Disable the break 2 function.
3735 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3736 * a timer instance provides a second break input.
3737 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3738 * @param TIMx Timer instance
3739 * @retval None
3740 */
3741__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3742{
3743 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3744}
3745
3746#if defined(TIM_BDTR_BKBID)
3747/**
3748 * @brief Configure the break 2 input.
3749 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3750 * a timer instance provides a second break input.
3751 * @note Bidirectional mode is only supported by advanced timer instances.
3752 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3753 * a timer instance is an advanced-control timer.
3754 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3755 * in input mode and in open drain output mode. Any active Break event will
3756 * assert a low logic level on the Break 2 input to indicate an internal break
3757 * event to external devices.
3758 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3759 * LL_TIM_BREAK2_AFMODE_INPUT.
3760 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3761 * BDTR BK2F LL_TIM_ConfigBRK2\n
3762 * BDTR BK2BID LL_TIM_ConfigBRK2
3763 * @param TIMx Timer instance
3764 * @param Break2Polarity This parameter can be one of the following values:
3765 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3766 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3767 * @param Break2Filter This parameter can be one of the following values:
3768 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3769 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3770 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3771 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3772 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3773 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3774 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3775 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3776 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3777 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3778 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3779 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3780 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3781 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3782 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3783 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3784 * @param Break2AFMode This parameter can be one of the following values:
3785 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3786 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3787 * @retval None
3788 */
3789__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3790 uint32_t Break2AFMode)
3791{
3792 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3793}
3794
3795#else
3796/**
3797 * @brief Configure the break 2 input.
3798 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3799 * a timer instance provides a second break input.
3800 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3801 * BDTR BK2F LL_TIM_ConfigBRK2
3802 * @param TIMx Timer instance
3803 * @param Break2Polarity This parameter can be one of the following values:
3804 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3805 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3806 * @param Break2Filter This parameter can be one of the following values:
3807 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3808 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3809 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3810 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3811 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3812 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3813 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3814 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3815 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3816 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3817 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3818 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3819 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3820 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3821 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3822 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3823 * @retval None
3824 */
3825__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3826{
3827 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3828}
3829
3830#endif /*TIM_BDTR_BKBID */
3831#if defined(TIM_BDTR_BKBID)
3832/**
3833 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3834 * @note The break 2 input can be disarmed only when it is configured in
3835 * bidirectional mode and when when MOE is reset.
3836 * @note Purpose is to be able to have the input voltage back to high-state,
3837 * whatever the time constant on the output.
3838 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3839 * @param TIMx Timer instance
3840 * @retval None
3841 */
3842__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3843{
3844 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3845}
3846
3847#endif /*TIM_BDTR_BKBID */
3848/**
3849 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3850 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3851 * a timer instance provides a break input.
3852 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3853 * BDTR OSSR LL_TIM_SetOffStates
3854 * @param TIMx Timer instance
3855 * @param OffStateIdle This parameter can be one of the following values:
3856 * @arg @ref LL_TIM_OSSI_DISABLE
3857 * @arg @ref LL_TIM_OSSI_ENABLE
3858 * @param OffStateRun This parameter can be one of the following values:
3859 * @arg @ref LL_TIM_OSSR_DISABLE
3860 * @arg @ref LL_TIM_OSSR_ENABLE
3861 * @retval None
3862 */
3863__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3864{
3865 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3866}
3867
3868/**
3869 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3870 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3871 * a timer instance provides a break input.
3872 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3873 * @param TIMx Timer instance
3874 * @retval None
3875 */
3876__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3877{
3878 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3879}
3880
3881/**
3882 * @brief Disable automatic output (MOE can be set only by software).
3883 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3884 * a timer instance provides a break input.
3885 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3886 * @param TIMx Timer instance
3887 * @retval None
3888 */
3889__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3890{
3891 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3892}
3893
3894/**
3895 * @brief Indicate whether automatic output is enabled.
3896 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3897 * a timer instance provides a break input.
3898 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3899 * @param TIMx Timer instance
3900 * @retval State of bit (1 or 0).
3901 */
3902__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3903{
3904 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3905}
3906
3907/**
3908 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3909 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3910 * software and is reset in case of break or break2 event
3911 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3912 * a timer instance provides a break input.
3913 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3914 * @param TIMx Timer instance
3915 * @retval None
3916 */
3917__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3918{
3919 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3920}
3921
3922/**
3923 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3924 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3925 * software and is reset in case of break or break2 event.
3926 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3927 * a timer instance provides a break input.
3928 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3929 * @param TIMx Timer instance
3930 * @retval None
3931 */
3932__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3933{
3934 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3935}
3936
3937/**
3938 * @brief Indicates whether outputs are enabled.
3939 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3940 * a timer instance provides a break input.
3941 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3942 * @param TIMx Timer instance
3943 * @retval State of bit (1 or 0).
3944 */
3945__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3946{
3947 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3948}
3949
3950#if defined(TIM_BREAK_INPUT_SUPPORT)
3951/**
3952 * @brief Enable the signals connected to the designated timer break input.
3953 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3954 * or not a timer instance allows for break input selection.
3955 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3956 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3957 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3958 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3959 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3960 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3961 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3962 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3963 * @param TIMx Timer instance
3964 * @param BreakInput This parameter can be one of the following values:
3965 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3966 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3967 * @param Source This parameter can be one of the following values:
3968 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3969 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3970 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3971 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3972 * @retval None
3973 */
3974__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3975{
3976 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3977 SET_BIT(*pReg, Source);
3978}
3979
3980/**
3981 * @brief Disable the signals connected to the designated timer break input.
3982 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3983 * or not a timer instance allows for break input selection.
3984 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3985 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3986 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3987 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3988 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3989 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3990 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3991 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3992 * @param TIMx Timer instance
3993 * @param BreakInput This parameter can be one of the following values:
3994 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3995 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3996 * @param Source This parameter can be one of the following values:
3997 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3998 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3999 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4000 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
4001 * @retval None
4002 */
4003__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4004{
4005 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4006 CLEAR_BIT(*pReg, Source);
4007}
4008
4009/**
4010 * @brief Set the polarity of the break signal for the timer break input.
4011 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4012 * or not a timer instance allows for break input selection.
4013 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4014 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4015 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4016 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4017 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4018 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
4019 * @param TIMx Timer instance
4020 * @param BreakInput This parameter can be one of the following values:
4021 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4022 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4023 * @param Source This parameter can be one of the following values:
4024 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4025 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4026 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4027 * @param Polarity This parameter can be one of the following values:
4028 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4029 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4030 * @retval None
4031 */
4032__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4033 uint32_t Polarity)
4034{
4035 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4036 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4037}
4038#endif /* TIM_BREAK_INPUT_SUPPORT */
4039/**
4040 * @}
4041 */
4042
4043/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4044 * @{
4045 */
4046/**
4047 * @brief Configures the timer DMA burst feature.
4048 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4049 * not a timer instance supports the DMA burst mode.
4050 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4051 * DCR DBA LL_TIM_ConfigDMABurst
4052 * @param TIMx Timer instance
4053 * @param DMABurstBaseAddress This parameter can be one of the following values:
4054 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4055 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4056 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4057 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4058 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4059 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4060 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4061 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4062 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4063 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4064 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4065 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4066 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4067 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4068 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4069 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4070 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4071 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4072 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4073 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4074 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4075 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4076 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4077 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4078 *
4079 * @param DMABurstLength This parameter can be one of the following values:
4080 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4081 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4082 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4083 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4084 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4085 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4086 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4087 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4088 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4089 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4090 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4091 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4092 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4093 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4094 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4095 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4096 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4097 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4098 * @retval None
4099 */
4100__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
4101{
4102 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
4103}
4104
4105/**
4106 * @}
4107 */
4108
4109/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4110 * @{
4111 */
4112/**
4113 * @brief Remap TIM inputs (input channel, internal/external triggers).
4114 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4115 * a some timer inputs can be remapped.
4116 * TIM1: one of the following values:
4117 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
4118 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
4119 *
4120 * TIM2: one of the following values:
4121 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
4122 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
4123 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
4124 * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
4125 *
4126 * TIM3: one of the following values:
4127 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
4128 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
4129 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
4130 * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
4131 *
4132 * TIM5: one of the following values:
4133 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
4134 * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP
4135 * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP
4136 *
4137 * TIM8: one of the following values:
4138 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
4139 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
4140 *
4141 * TIM12: one of the following values: (*)
4142 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
4143 * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
4144 *
4145 * TIM15: one of the following values:
4146 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
4147 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1
4148 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1
4149 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1
4150 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
4151 * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI
4152 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
4153 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
4154 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2
4155 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2
4156 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2
4157 *
4158 * TIM16: one of the following values:
4159 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
4160 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
4161 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
4162 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
4163 *
4164 * TIM17: one of the following values:
4165 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
4166 * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
4167 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
4168 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
4169 *
4170 * TIM23: one of the following values: (*)
4171 * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO
4172 * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output
4173 * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output
4174 * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
4175 *
4176 * TIM24: one of the following values: (*)
4177 * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO
4178 * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP
4179 * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP
4180 * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC
4181 *
4182 * (*) Value not defined in all devices. \n
4183 * @retval None
4184 */
4185__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4186{
4187 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4188}
4189
4190/**
4191 * @}
4192 */
4193
4194/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4195 * @{
4196 */
4197/**
4198 * @brief Clear the update interrupt flag (UIF).
4199 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4200 * @param TIMx Timer instance
4201 * @retval None
4202 */
4203__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4204{
4205 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4206}
4207
4208/**
4209 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4210 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4211 * @param TIMx Timer instance
4212 * @retval State of bit (1 or 0).
4213 */
4214__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4215{
4216 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4217}
4218
4219/**
4220 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4221 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4222 * @param TIMx Timer instance
4223 * @retval None
4224 */
4225__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4226{
4227 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4228}
4229
4230/**
4231 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4232 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4233 * @param TIMx Timer instance
4234 * @retval State of bit (1 or 0).
4235 */
4236__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4237{
4238 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4239}
4240
4241/**
4242 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4243 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4244 * @param TIMx Timer instance
4245 * @retval None
4246 */
4247__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4248{
4249 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4250}
4251
4252/**
4253 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4254 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4255 * @param TIMx Timer instance
4256 * @retval State of bit (1 or 0).
4257 */
4258__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4259{
4260 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4261}
4262
4263/**
4264 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4265 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4266 * @param TIMx Timer instance
4267 * @retval None
4268 */
4269__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4270{
4271 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4272}
4273
4274/**
4275 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4276 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4277 * @param TIMx Timer instance
4278 * @retval State of bit (1 or 0).
4279 */
4280__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4281{
4282 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4283}
4284
4285/**
4286 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4287 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4288 * @param TIMx Timer instance
4289 * @retval None
4290 */
4291__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4292{
4293 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4294}
4295
4296/**
4297 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4298 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4299 * @param TIMx Timer instance
4300 * @retval State of bit (1 or 0).
4301 */
4302__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4303{
4304 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4305}
4306
4307/**
4308 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4309 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4310 * @param TIMx Timer instance
4311 * @retval None
4312 */
4313__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4314{
4315 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4316}
4317
4318/**
4319 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4320 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4321 * @param TIMx Timer instance
4322 * @retval State of bit (1 or 0).
4323 */
4324__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4325{
4326 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4327}
4328
4329/**
4330 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4331 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4332 * @param TIMx Timer instance
4333 * @retval None
4334 */
4335__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4336{
4337 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4338}
4339
4340/**
4341 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4342 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4343 * @param TIMx Timer instance
4344 * @retval State of bit (1 or 0).
4345 */
4346__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4347{
4348 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4349}
4350
4351/**
4352 * @brief Clear the commutation interrupt flag (COMIF).
4353 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4354 * @param TIMx Timer instance
4355 * @retval None
4356 */
4357__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4358{
4359 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4360}
4361
4362/**
4363 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4364 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4365 * @param TIMx Timer instance
4366 * @retval State of bit (1 or 0).
4367 */
4368__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4369{
4370 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4371}
4372
4373/**
4374 * @brief Clear the trigger interrupt flag (TIF).
4375 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4376 * @param TIMx Timer instance
4377 * @retval None
4378 */
4379__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4380{
4381 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4382}
4383
4384/**
4385 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4386 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4387 * @param TIMx Timer instance
4388 * @retval State of bit (1 or 0).
4389 */
4390__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4391{
4392 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4393}
4394
4395/**
4396 * @brief Clear the break interrupt flag (BIF).
4397 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4398 * @param TIMx Timer instance
4399 * @retval None
4400 */
4401__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4402{
4403 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4404}
4405
4406/**
4407 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4408 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4409 * @param TIMx Timer instance
4410 * @retval State of bit (1 or 0).
4411 */
4412__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4413{
4414 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4415}
4416
4417/**
4418 * @brief Clear the break 2 interrupt flag (B2IF).
4419 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4420 * @param TIMx Timer instance
4421 * @retval None
4422 */
4423__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4424{
4425 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4426}
4427
4428/**
4429 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4430 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4431 * @param TIMx Timer instance
4432 * @retval State of bit (1 or 0).
4433 */
4434__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4435{
4436 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4437}
4438
4439/**
4440 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4441 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4442 * @param TIMx Timer instance
4443 * @retval None
4444 */
4445__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4446{
4447 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4448}
4449
4450/**
4451 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4452 * (Capture/Compare 1 interrupt is pending).
4453 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4454 * @param TIMx Timer instance
4455 * @retval State of bit (1 or 0).
4456 */
4457__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4458{
4459 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4460}
4461
4462/**
4463 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4464 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4465 * @param TIMx Timer instance
4466 * @retval None
4467 */
4468__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4469{
4470 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4471}
4472
4473/**
4474 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4475 * (Capture/Compare 2 over-capture interrupt is pending).
4476 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4477 * @param TIMx Timer instance
4478 * @retval State of bit (1 or 0).
4479 */
4480__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4481{
4482 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4483}
4484
4485/**
4486 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4487 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4488 * @param TIMx Timer instance
4489 * @retval None
4490 */
4491__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4492{
4493 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4494}
4495
4496/**
4497 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4498 * (Capture/Compare 3 over-capture interrupt is pending).
4499 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4500 * @param TIMx Timer instance
4501 * @retval State of bit (1 or 0).
4502 */
4503__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4504{
4505 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4506}
4507
4508/**
4509 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4510 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4511 * @param TIMx Timer instance
4512 * @retval None
4513 */
4514__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4515{
4516 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4517}
4518
4519/**
4520 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4521 * (Capture/Compare 4 over-capture interrupt is pending).
4522 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4523 * @param TIMx Timer instance
4524 * @retval State of bit (1 or 0).
4525 */
4526__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4527{
4528 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4529}
4530
4531/**
4532 * @brief Clear the system break interrupt flag (SBIF).
4533 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4534 * @param TIMx Timer instance
4535 * @retval None
4536 */
4537__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4538{
4539 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4540}
4541
4542/**
4543 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4544 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4545 * @param TIMx Timer instance
4546 * @retval State of bit (1 or 0).
4547 */
4548__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4549{
4550 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4551}
4552
4553/**
4554 * @}
4555 */
4556
4557/** @defgroup TIM_LL_EF_IT_Management IT-Management
4558 * @{
4559 */
4560/**
4561 * @brief Enable update interrupt (UIE).
4562 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4563 * @param TIMx Timer instance
4564 * @retval None
4565 */
4566__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4567{
4568 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4569}
4570
4571/**
4572 * @brief Disable update interrupt (UIE).
4573 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4574 * @param TIMx Timer instance
4575 * @retval None
4576 */
4577__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4578{
4579 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4580}
4581
4582/**
4583 * @brief Indicates whether the update interrupt (UIE) is enabled.
4584 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4585 * @param TIMx Timer instance
4586 * @retval State of bit (1 or 0).
4587 */
4588__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4589{
4590 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4591}
4592
4593/**
4594 * @brief Enable capture/compare 1 interrupt (CC1IE).
4595 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4596 * @param TIMx Timer instance
4597 * @retval None
4598 */
4599__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4600{
4601 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4602}
4603
4604/**
4605 * @brief Disable capture/compare 1 interrupt (CC1IE).
4606 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4607 * @param TIMx Timer instance
4608 * @retval None
4609 */
4610__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4611{
4612 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4613}
4614
4615/**
4616 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4617 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4618 * @param TIMx Timer instance
4619 * @retval State of bit (1 or 0).
4620 */
4621__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4622{
4623 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4624}
4625
4626/**
4627 * @brief Enable capture/compare 2 interrupt (CC2IE).
4628 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4629 * @param TIMx Timer instance
4630 * @retval None
4631 */
4632__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4633{
4634 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4635}
4636
4637/**
4638 * @brief Disable capture/compare 2 interrupt (CC2IE).
4639 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4640 * @param TIMx Timer instance
4641 * @retval None
4642 */
4643__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4644{
4645 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4646}
4647
4648/**
4649 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4650 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4651 * @param TIMx Timer instance
4652 * @retval State of bit (1 or 0).
4653 */
4654__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4655{
4656 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4657}
4658
4659/**
4660 * @brief Enable capture/compare 3 interrupt (CC3IE).
4661 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4662 * @param TIMx Timer instance
4663 * @retval None
4664 */
4665__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4666{
4667 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4668}
4669
4670/**
4671 * @brief Disable capture/compare 3 interrupt (CC3IE).
4672 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4673 * @param TIMx Timer instance
4674 * @retval None
4675 */
4676__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4677{
4678 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4679}
4680
4681/**
4682 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4683 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4684 * @param TIMx Timer instance
4685 * @retval State of bit (1 or 0).
4686 */
4687__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4688{
4689 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4690}
4691
4692/**
4693 * @brief Enable capture/compare 4 interrupt (CC4IE).
4694 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4695 * @param TIMx Timer instance
4696 * @retval None
4697 */
4698__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4699{
4700 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4701}
4702
4703/**
4704 * @brief Disable capture/compare 4 interrupt (CC4IE).
4705 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4706 * @param TIMx Timer instance
4707 * @retval None
4708 */
4709__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4710{
4711 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4712}
4713
4714/**
4715 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4716 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4717 * @param TIMx Timer instance
4718 * @retval State of bit (1 or 0).
4719 */
4720__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4721{
4722 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4723}
4724
4725/**
4726 * @brief Enable commutation interrupt (COMIE).
4727 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4728 * @param TIMx Timer instance
4729 * @retval None
4730 */
4731__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4732{
4733 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4734}
4735
4736/**
4737 * @brief Disable commutation interrupt (COMIE).
4738 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4739 * @param TIMx Timer instance
4740 * @retval None
4741 */
4742__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4743{
4744 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4745}
4746
4747/**
4748 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4749 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4750 * @param TIMx Timer instance
4751 * @retval State of bit (1 or 0).
4752 */
4753__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4754{
4755 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4756}
4757
4758/**
4759 * @brief Enable trigger interrupt (TIE).
4760 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4761 * @param TIMx Timer instance
4762 * @retval None
4763 */
4764__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4765{
4766 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4767}
4768
4769/**
4770 * @brief Disable trigger interrupt (TIE).
4771 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4772 * @param TIMx Timer instance
4773 * @retval None
4774 */
4775__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4776{
4777 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4778}
4779
4780/**
4781 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4782 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4783 * @param TIMx Timer instance
4784 * @retval State of bit (1 or 0).
4785 */
4786__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4787{
4788 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4789}
4790
4791/**
4792 * @brief Enable break interrupt (BIE).
4793 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4794 * @param TIMx Timer instance
4795 * @retval None
4796 */
4797__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4798{
4799 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4800}
4801
4802/**
4803 * @brief Disable break interrupt (BIE).
4804 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4805 * @param TIMx Timer instance
4806 * @retval None
4807 */
4808__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4809{
4810 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4811}
4812
4813/**
4814 * @brief Indicates whether the break interrupt (BIE) is enabled.
4815 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4816 * @param TIMx Timer instance
4817 * @retval State of bit (1 or 0).
4818 */
4819__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4820{
4821 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4822}
4823
4824/**
4825 * @}
4826 */
4827
4828/** @defgroup TIM_LL_EF_DMA_Management DMA Management
4829 * @{
4830 */
4831/**
4832 * @brief Enable update DMA request (UDE).
4833 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4834 * @param TIMx Timer instance
4835 * @retval None
4836 */
4837__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4838{
4839 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4840}
4841
4842/**
4843 * @brief Disable update DMA request (UDE).
4844 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4845 * @param TIMx Timer instance
4846 * @retval None
4847 */
4848__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4849{
4850 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4851}
4852
4853/**
4854 * @brief Indicates whether the update DMA request (UDE) is enabled.
4855 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4856 * @param TIMx Timer instance
4857 * @retval State of bit (1 or 0).
4858 */
4859__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4860{
4861 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4862}
4863
4864/**
4865 * @brief Enable capture/compare 1 DMA request (CC1DE).
4866 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4867 * @param TIMx Timer instance
4868 * @retval None
4869 */
4870__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4871{
4872 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4873}
4874
4875/**
4876 * @brief Disable capture/compare 1 DMA request (CC1DE).
4877 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4878 * @param TIMx Timer instance
4879 * @retval None
4880 */
4881__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4882{
4883 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4884}
4885
4886/**
4887 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4888 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4889 * @param TIMx Timer instance
4890 * @retval State of bit (1 or 0).
4891 */
4892__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4893{
4894 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4895}
4896
4897/**
4898 * @brief Enable capture/compare 2 DMA request (CC2DE).
4899 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4900 * @param TIMx Timer instance
4901 * @retval None
4902 */
4903__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4904{
4905 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4906}
4907
4908/**
4909 * @brief Disable capture/compare 2 DMA request (CC2DE).
4910 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4911 * @param TIMx Timer instance
4912 * @retval None
4913 */
4914__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4915{
4916 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4917}
4918
4919/**
4920 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4921 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4922 * @param TIMx Timer instance
4923 * @retval State of bit (1 or 0).
4924 */
4925__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4926{
4927 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4928}
4929
4930/**
4931 * @brief Enable capture/compare 3 DMA request (CC3DE).
4932 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4933 * @param TIMx Timer instance
4934 * @retval None
4935 */
4936__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4937{
4938 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4939}
4940
4941/**
4942 * @brief Disable capture/compare 3 DMA request (CC3DE).
4943 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4944 * @param TIMx Timer instance
4945 * @retval None
4946 */
4947__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4948{
4949 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4950}
4951
4952/**
4953 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4954 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4955 * @param TIMx Timer instance
4956 * @retval State of bit (1 or 0).
4957 */
4958__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4959{
4960 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4961}
4962
4963/**
4964 * @brief Enable capture/compare 4 DMA request (CC4DE).
4965 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4966 * @param TIMx Timer instance
4967 * @retval None
4968 */
4969__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4970{
4971 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4972}
4973
4974/**
4975 * @brief Disable capture/compare 4 DMA request (CC4DE).
4976 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4977 * @param TIMx Timer instance
4978 * @retval None
4979 */
4980__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4981{
4982 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4983}
4984
4985/**
4986 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4987 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4988 * @param TIMx Timer instance
4989 * @retval State of bit (1 or 0).
4990 */
4991__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4992{
4993 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4994}
4995
4996/**
4997 * @brief Enable commutation DMA request (COMDE).
4998 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4999 * @param TIMx Timer instance
5000 * @retval None
5001 */
5002__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
5003{
5004 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
5005}
5006
5007/**
5008 * @brief Disable commutation DMA request (COMDE).
5009 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
5010 * @param TIMx Timer instance
5011 * @retval None
5012 */
5013__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
5014{
5015 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
5016}
5017
5018/**
5019 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
5020 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
5021 * @param TIMx Timer instance
5022 * @retval State of bit (1 or 0).
5023 */
5024__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
5025{
5026 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
5027}
5028
5029/**
5030 * @brief Enable trigger interrupt (TDE).
5031 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
5032 * @param TIMx Timer instance
5033 * @retval None
5034 */
5035__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
5036{
5037 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
5038}
5039
5040/**
5041 * @brief Disable trigger interrupt (TDE).
5042 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
5043 * @param TIMx Timer instance
5044 * @retval None
5045 */
5046__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
5047{
5048 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
5049}
5050
5051/**
5052 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
5053 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
5054 * @param TIMx Timer instance
5055 * @retval State of bit (1 or 0).
5056 */
5057__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
5058{
5059 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
5060}
5061
5062/**
5063 * @}
5064 */
5065
5066/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
5067 * @{
5068 */
5069/**
5070 * @brief Generate an update event.
5071 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
5072 * @param TIMx Timer instance
5073 * @retval None
5074 */
5075__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
5076{
5077 SET_BIT(TIMx->EGR, TIM_EGR_UG);
5078}
5079
5080/**
5081 * @brief Generate Capture/Compare 1 event.
5082 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
5083 * @param TIMx Timer instance
5084 * @retval None
5085 */
5086__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
5087{
5088 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
5089}
5090
5091/**
5092 * @brief Generate Capture/Compare 2 event.
5093 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
5094 * @param TIMx Timer instance
5095 * @retval None
5096 */
5097__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
5098{
5099 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
5100}
5101
5102/**
5103 * @brief Generate Capture/Compare 3 event.
5104 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
5105 * @param TIMx Timer instance
5106 * @retval None
5107 */
5108__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
5109{
5110 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
5111}
5112
5113/**
5114 * @brief Generate Capture/Compare 4 event.
5115 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
5116 * @param TIMx Timer instance
5117 * @retval None
5118 */
5119__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
5120{
5121 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
5122}
5123
5124/**
5125 * @brief Generate commutation event.
5126 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
5127 * @param TIMx Timer instance
5128 * @retval None
5129 */
5130__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
5131{
5132 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
5133}
5134
5135/**
5136 * @brief Generate trigger event.
5137 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
5138 * @param TIMx Timer instance
5139 * @retval None
5140 */
5141__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
5142{
5143 SET_BIT(TIMx->EGR, TIM_EGR_TG);
5144}
5145
5146/**
5147 * @brief Generate break event.
5148 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
5149 * @param TIMx Timer instance
5150 * @retval None
5151 */
5152__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5153{
5154 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5155}
5156
5157/**
5158 * @brief Generate break 2 event.
5159 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5160 * @param TIMx Timer instance
5161 * @retval None
5162 */
5163__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5164{
5165 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5166}
5167
5168/**
5169 * @}
5170 */
5171
5172#if defined(USE_FULL_LL_DRIVER)
5173/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5174 * @{
5175 */
5176
5177ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
5178void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5179ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5180void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5181ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5182void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5183ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5184void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5185ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5186void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5187ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5188void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5189ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5190/**
5191 * @}
5192 */
5193#endif /* USE_FULL_LL_DRIVER */
5194
5195/**
5196 * @}
5197 */
5198
5199/**
5200 * @}
5201 */
5202
5203#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */
5204
5205/**
5206 * @}
5207 */
5208
5209#ifdef __cplusplus
5210}
5211#endif
5212
5213#endif /* __STM32H7xx_LL_TIM_H */
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
__IO
#define __IO
Defines 'read / write' permissions.
Definition core_armv81mml.h:290
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
READ_REG
#define READ_REG(REG)
Definition stm32h7xx.h:217
ErrorStatus
ErrorStatus
Definition stm32h7xx.h:194
RESET
@ RESET
Definition stm32h7xx.h:182
TIM_EGR_CC3G
#define TIM_EGR_CC3G
Capture/Compare 3 Generation.
Definition stm32h723xx.h:19614
TIM_CR1_URS
#define TIM_CR1_URS
Update request source.
Definition stm32h723xx.h:19377
TIM_EGR_BG
#define TIM_EGR_BG
Break Generation.
Definition stm32h723xx.h:19626
TIM_EGR_CC1G
#define TIM_EGR_CC1G
Capture/Compare 1 Generation.
Definition stm32h723xx.h:19608
TIM_CCER_CC1P
#define TIM_CCER_CC1P
Capture/Compare 1 output Polarity.
Definition stm32h723xx.h:19800
TIM_SMCR_ETPS
#define TIM_SMCR_ETPS
ETPS[1:0] bits (External trigger prescaler).
Definition stm32h723xx.h:19494
TIM_DIER_CC3DE
#define TIM_DIER_CC3DE
Capture/Compare 3 DMA request enable.
Definition stm32h723xx.h:19541
TIM_EGR_UG
#define TIM_EGR_UG
Update Generation.
Definition stm32h723xx.h:19605
TIM_CCMR1_OC1PE
#define TIM_CCMR1_OC1PE
Output Compare 1 Preload enable.
Definition stm32h723xx.h:19644
TIM_DIER_CC1IE
#define TIM_DIER_CC1IE
Capture/Compare 1 interrupt enable.
Definition stm32h723xx.h:19511
TIM_EGR_CC4G
#define TIM_EGR_CC4G
Capture/Compare 4 Generation.
Definition stm32h723xx.h:19617
TIM_DIER_BIE
#define TIM_DIER_BIE
Break interrupt enable.
Definition stm32h723xx.h:19529
TIM_SR_CC5IF
#define TIM_SR_CC5IF
Capture/Compare 5 interrupt Flag.
Definition stm32h723xx.h:19594
TIM_SR_CC2IF
#define TIM_SR_CC2IF
Capture/Compare 2 interrupt Flag.
Definition stm32h723xx.h:19561
TIM_BDTR_MOE
#define TIM_BDTR_MOE
Main Output enable.
Definition stm32h723xx.h:19949
TIM_SMCR_ETP
#define TIM_SMCR_ETP
External trigger polarity.
Definition stm32h723xx.h:19503
TIM_EGR_TG
#define TIM_EGR_TG
Trigger Generation.
Definition stm32h723xx.h:19623
TIM_BDTR_BKDSRM
#define TIM_BDTR_BKDSRM
Break Disarm.
Definition stm32h723xx.h:19966
TIM_CR2_OIS1
#define TIM_CR2_OIS1
Output Idle state 1 (OC1 output).
Definition stm32h723xx.h:19428
TIM_BDTR_BKP
#define TIM_BDTR_BKP
Break Polarity for Break1.
Definition stm32h723xx.h:19943
TIM_SMCR_ECE
#define TIM_SMCR_ECE
External clock enable.
Definition stm32h723xx.h:19500
TIM_CR1_CMS
#define TIM_CR1_CMS
CMS[1:0] bits (Center-aligned mode selection).
Definition stm32h723xx.h:19387
TIM_SR_CC2OF
#define TIM_SR_CC2OF
Capture/Compare 2 Overcapture Flag.
Definition stm32h723xx.h:19585
TIM_CCER_CC1NP
#define TIM_CCER_CC1NP
Capture/Compare 1 Complementary output Polarity.
Definition stm32h723xx.h:19806
TIM_EGR_B2G
#define TIM_EGR_B2G
Break Generation.
Definition stm32h723xx.h:19629
TIM_SR_CC1IF
#define TIM_SR_CC1IF
Capture/Compare 1 interrupt Flag.
Definition stm32h723xx.h:19558
TIM_CR1_ARPE
#define TIM_CR1_ARPE
Auto-reload preload enable.
Definition stm32h723xx.h:19393
TIM_DIER_CC3IE
#define TIM_DIER_CC3IE
Capture/Compare 3 interrupt enable.
Definition stm32h723xx.h:19517
TIM_BDTR_BK2E
#define TIM_BDTR_BK2E
Break enable for Break2.
Definition stm32h723xx.h:19960
TIM_TISEL_TI1SEL
#define TIM_TISEL_TI1SEL
TI1SEL[3:0] bits (TIM TI1 SEL).
Definition stm32h723xx.h:20096
TIM_SMCR_MSM
#define TIM_SMCR_MSM
Master/slave mode.
Definition stm32h723xx.h:19482
TIM_EGR_CC2G
#define TIM_EGR_CC2G
Capture/Compare 2 Generation.
Definition stm32h723xx.h:19611
TIM_CCR5_CCR5
#define TIM_CCR5_CCR5
Capture/Compare 5 Value.
Definition stm32h723xx.h:19897
TIM_BDTR_BKBID
#define TIM_BDTR_BKBID
Break Bidirectional.
Definition stm32h723xx.h:19972
TIM_DIER_CC2DE
#define TIM_DIER_CC2DE
Capture/Compare 2 DMA request enable.
Definition stm32h723xx.h:19538
TIM_BDTR_AOE
#define TIM_BDTR_AOE
Automatic Output enable.
Definition stm32h723xx.h:19946
TIM_DIER_TDE
#define TIM_DIER_TDE
Trigger DMA request enable.
Definition stm32h723xx.h:19550
TIM_DIER_UIE
#define TIM_DIER_UIE
Update interrupt enable.
Definition stm32h723xx.h:19508
TIM_CCR5_GC5C2
#define TIM_CCR5_GC5C2
Group Channel 5 and Channel 2.
Definition stm32h723xx.h:19903
TIM_DIER_CC4IE
#define TIM_DIER_CC4IE
Capture/Compare 4 interrupt enable.
Definition stm32h723xx.h:19520
TIM_CR1_OPM
#define TIM_CR1_OPM
One pulse mode.
Definition stm32h723xx.h:19380
TIM_SR_BIF
#define TIM_SR_BIF
Break interrupt Flag.
Definition stm32h723xx.h:19576
TIM_CCMR1_OC1M
#define TIM_CCMR1_OC1M
OC1M[2:0] bits (Output Compare 1 Mode).
Definition stm32h723xx.h:19648
TIM_BDTR_BKE
#define TIM_BDTR_BKE
Break enable for Break1.
Definition stm32h723xx.h:19940
TIM_DIER_CC2IE
#define TIM_DIER_CC2IE
Capture/Compare 2 interrupt enable.
Definition stm32h723xx.h:19514
TIM_BDTR_BK2DSRM
#define TIM_BDTR_BK2DSRM
Break2 Disarm.
Definition stm32h723xx.h:19969
TIM_DIER_COMDE
#define TIM_DIER_COMDE
COM DMA request enable.
Definition stm32h723xx.h:19547
TIM_TISEL_TI3SEL
#define TIM_TISEL_TI3SEL
TI3SEL[3:0] bits (TIM TI3 SEL).
Definition stm32h723xx.h:20112
TIM_SR_TIF
#define TIM_SR_TIF
Trigger interrupt Flag.
Definition stm32h723xx.h:19573
TIM_BDTR_LOCK
#define TIM_BDTR_LOCK
LOCK[1:0] bits (Lock Configuration).
Definition stm32h723xx.h:19928
TIM_TISEL_TI4SEL
#define TIM_TISEL_TI4SEL
TI4SEL[3:0] bits (TIM TI4 SEL).
Definition stm32h723xx.h:20120
TIM_SR_CC1OF
#define TIM_SR_CC1OF
Capture/Compare 1 Overcapture Flag.
Definition stm32h723xx.h:19582
TIM_SR_CC4OF
#define TIM_SR_CC4OF
Capture/Compare 4 Overcapture Flag.
Definition stm32h723xx.h:19591
TIM_SMCR_TS
#define TIM_SMCR_TS
TS[4:0] bits (Trigger selection).
Definition stm32h723xx.h:19473
TIM_CCMR1_OC1CE
#define TIM_CCMR1_OC1CE
Output Compare 1Clear Enable.
Definition stm32h723xx.h:19656
TIM_CNT_UIFCPY
#define TIM_CNT_UIFCPY
Update interrupt flag copy.
Definition stm32h723xx.h:19858
TIM_SR_COMIF
#define TIM_SR_COMIF
COM interrupt Flag.
Definition stm32h723xx.h:19570
TIM_CR1_CEN
#define TIM_CR1_CEN
Counter enable.
Definition stm32h723xx.h:19371
TIM_BDTR_BK2P
#define TIM_BDTR_BK2P
Break Polarity for Break2.
Definition stm32h723xx.h:19963
TIM_CCMR1_CC1S
#define TIM_CCMR1_CC1S
CC1S[1:0] bits (Capture/Compare 1 Selection).
Definition stm32h723xx.h:19635
TIM_CR1_UDIS
#define TIM_CR1_UDIS
Update disable.
Definition stm32h723xx.h:19374
TIM_DIER_TIE
#define TIM_DIER_TIE
Trigger interrupt enable.
Definition stm32h723xx.h:19526
TIM_CR2_MMS
#define TIM_CR2_MMS
MMS[2:0] bits (Master Mode Selection).
Definition stm32h723xx.h:19418
TIM_CCR5_GC5C3
#define TIM_CCR5_GC5C3
Group Channel 5 and Channel 3.
Definition stm32h723xx.h:19906
TIM_DIER_CC4DE
#define TIM_DIER_CC4DE
Capture/Compare 4 DMA request enable.
Definition stm32h723xx.h:19544
TIM_CR2_CCPC
#define TIM_CR2_CCPC
Capture/Compare Preloaded Control.
Definition stm32h723xx.h:19408
TIM_CCMR1_IC1F
#define TIM_CCMR1_IC1F
IC1F[3:0] bits (Input Capture 1 Filter).
Definition stm32h723xx.h:19693
TIM_BDTR_OSSI
#define TIM_BDTR_OSSI
Off-State Selection for Idle mode.
Definition stm32h723xx.h:19934
TIM_BDTR_BK2BID
#define TIM_BDTR_BK2BID
Break2 Bidirectional.
Definition stm32h723xx.h:19975
TIM_CCMR1_IC1PSC
#define TIM_CCMR1_IC1PSC
IC1PSC[1:0] bits (Input Capture 1 Prescaler).
Definition stm32h723xx.h:19687
TIM_CCMR1_OC1FE
#define TIM_CCMR1_OC1FE
Output Compare 1 Fast enable.
Definition stm32h723xx.h:19641
TIM_DCR_DBL
#define TIM_DCR_DBL
DBL[4:0] bits (DMA Burst Length).
Definition stm32h723xx.h:19989
TIM_DIER_UDE
#define TIM_DIER_UDE
Update DMA request enable.
Definition stm32h723xx.h:19532
TIM_BDTR_DTG
#define TIM_BDTR_DTG
DTG[0:7] bits (Dead-Time Generator set-up).
Definition stm32h723xx.h:19916
TIM_DCR_DBA
#define TIM_DCR_DBA
DBA[4:0] bits (DMA Base Address).
Definition stm32h723xx.h:19980
TIM_SR_UIF
#define TIM_SR_UIF
Update interrupt Flag.
Definition stm32h723xx.h:19555
TIM_CR1_CKD
#define TIM_CR1_CKD
CKD[1:0] bits (clock division).
Definition stm32h723xx.h:19397
TIM_SR_CC4IF
#define TIM_SR_CC4IF
Capture/Compare 4 interrupt Flag.
Definition stm32h723xx.h:19567
TIM_BDTR_BK2F
#define TIM_BDTR_BK2F
Break Filter for Break2.
Definition stm32h723xx.h:19956
TIM_CR1_DIR
#define TIM_CR1_DIR
Direction.
Definition stm32h723xx.h:19383
TIM_CR2_TI1S
#define TIM_CR2_TI1S
TI1 Selection.
Definition stm32h723xx.h:19425
TIM_SR_CC6IF
#define TIM_SR_CC6IF
Capture/Compare 6 interrupt Flag.
Definition stm32h723xx.h:19597
TIM_SR_CC3IF
#define TIM_SR_CC3IF
Capture/Compare 3 interrupt Flag.
Definition stm32h723xx.h:19564
TIM_EGR_COMG
#define TIM_EGR_COMG
Capture/Compare Control Update Generation.
Definition stm32h723xx.h:19620
TIM_CCR5_GC5C1
#define TIM_CCR5_GC5C1
Group Channel 5 and Channel 1.
Definition stm32h723xx.h:19900
TIM_CR2_CCDS
#define TIM_CR2_CCDS
Capture/Compare DMA Selection.
Definition stm32h723xx.h:19414
TIM_DIER_COMIE
#define TIM_DIER_COMIE
COM interrupt enable.
Definition stm32h723xx.h:19523
TIM_DIER_CC1DE
#define TIM_DIER_CC1DE
Capture/Compare 1 DMA request enable.
Definition stm32h723xx.h:19535
TIM_CR2_MMS2
#define TIM_CR2_MMS2
MMS[2:0] bits (Master Mode Selection).
Definition stm32h723xx.h:19456
TIM_BDTR_BKF
#define TIM_BDTR_BKF
Break Filter for Break1.
Definition stm32h723xx.h:19953
TIM_SMCR_ETF
#define TIM_SMCR_ETF
ETF[3:0] bits (External trigger filter).
Definition stm32h723xx.h:19486
TIM_SR_SBIF
#define TIM_SR_SBIF
System Break Flag.
Definition stm32h723xx.h:19600
TIM_SMCR_SMS
#define TIM_SMCR_SMS
SMS[2:0] bits (Slave mode selection).
Definition stm32h723xx.h:19465
TIM_SR_B2IF
#define TIM_SR_B2IF
Break2 interrupt Flag.
Definition stm32h723xx.h:19579
TIM_CR2_CCUS
#define TIM_CR2_CCUS
Capture/Compare Control Update Selection.
Definition stm32h723xx.h:19411
TIM_CR1_UIFREMAP
#define TIM_CR1_UIFREMAP
Update interrupt flag remap.
Definition stm32h723xx.h:19403
TIM_SR_CC3OF
#define TIM_SR_CC3OF
Capture/Compare 3 Overcapture Flag.
Definition stm32h723xx.h:19588
TIM_BDTR_OSSR
#define TIM_BDTR_OSSR
Off-State Selection for Run mode.
Definition stm32h723xx.h:19937
TIM_TISEL_TI2SEL
#define TIM_TISEL_TI2SEL
TI2SEL[3:0] bits (TIM TI2 SEL).
Definition stm32h723xx.h:20104
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
TIM_TypeDef
TIM.
Definition stm32h723xx.h:1525
TIM_TypeDef::EGR
__IO uint32_t EGR
TIM event generation register, Address offset: 0x14.
Definition stm32h723xx.h:1531
TIM_TypeDef::CCR1
__IO uint32_t CCR1
TIM capture/compare register 1, Address offset: 0x34.
Definition stm32h723xx.h:1539
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
TIM capture/compare mode register 1, Address offset: 0x18.
Definition stm32h723xx.h:1532
TIM_TypeDef::BDTR
__IO uint32_t BDTR
TIM break and dead-time register, Address offset: 0x44.
Definition stm32h723xx.h:1543
TIM_TypeDef::DIER
__IO uint32_t DIER
TIM DMA/interrupt enable register, Address offset: 0x0C.
Definition stm32h723xx.h:1529
TIM_TypeDef::CCR6
__IO uint32_t CCR6
TIM capture/compare register6, Address offset: 0x5C.
Definition stm32h723xx.h:1549
TIM_TypeDef::TISEL
__IO uint32_t TISEL
TIM Input Selection register, Address offset: 0x68.
Definition stm32h723xx.h:1552
TIM_TypeDef::CCR2
__IO uint32_t CCR2
TIM capture/compare register 2, Address offset: 0x38.
Definition stm32h723xx.h:1540
TIM_TypeDef::CCR4
__IO uint32_t CCR4
TIM capture/compare register 4, Address offset: 0x40.
Definition stm32h723xx.h:1542
TIM_TypeDef::SMCR
__IO uint32_t SMCR
TIM slave mode control register, Address offset: 0x08.
Definition stm32h723xx.h:1528
TIM_TypeDef::ARR
__IO uint32_t ARR
TIM auto-reload register, Address offset: 0x2C.
Definition stm32h723xx.h:1537
TIM_TypeDef::CR2
__IO uint32_t CR2
TIM control register 2, Address offset: 0x04.
Definition stm32h723xx.h:1527
TIM_TypeDef::CNT
__IO uint32_t CNT
TIM counter register, Address offset: 0x24.
Definition stm32h723xx.h:1535
TIM_TypeDef::AF1
__IO uint32_t AF1
TIM alternate function option register 1, Address offset: 0x60.
Definition stm32h723xx.h:1550
TIM_TypeDef::DCR
__IO uint32_t DCR
TIM DMA control register, Address offset: 0x48.
Definition stm32h723xx.h:1544
TIM_TypeDef::CR1
__IO uint32_t CR1
TIM control register 1, Address offset: 0x00.
Definition stm32h723xx.h:1526
TIM_TypeDef::CCR3
__IO uint32_t CCR3
TIM capture/compare register 3, Address offset: 0x3C.
Definition stm32h723xx.h:1541
TIM_TypeDef::SR
__IO uint32_t SR
TIM status register, Address offset: 0x10.
Definition stm32h723xx.h:1530
TIM_TypeDef::PSC
__IO uint32_t PSC
TIM prescaler, Address offset: 0x28.
Definition stm32h723xx.h:1536
TIM_TypeDef::RCR
__IO uint32_t RCR
TIM repetition counter register, Address offset: 0x30.
Definition stm32h723xx.h:1538
TIM_TypeDef::CCER
__IO uint32_t CCER
TIM capture/compare enable register, Address offset: 0x20.
Definition stm32h723xx.h:1534
TIM_TypeDef::CCR5
__IO uint32_t CCR5
TIM capture/compare register5, Address offset: 0x58.
Definition stm32h723xx.h:1548