TIM. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR1
	TIM control register 1, Address offset: 0x00.
__IO uint32_t	CR2
	TIM control register 2, Address offset: 0x04.
__IO uint32_t	SMCR
	TIM slave mode control register, Address offset: 0x08.
__IO uint32_t	DIER
	TIM DMA/interrupt enable register, Address offset: 0x0C.
__IO uint32_t	SR
	TIM status register, Address offset: 0x10.
__IO uint32_t	EGR
	TIM event generation register, Address offset: 0x14.
__IO uint32_t	CCMR1
	TIM capture/compare mode register 1, Address offset: 0x18.
__IO uint32_t	CCMR2
	TIM capture/compare mode register 2, Address offset: 0x1C.
__IO uint32_t	CCER
	TIM capture/compare enable register, Address offset: 0x20.
__IO uint32_t	CNT
	TIM counter register, Address offset: 0x24.
__IO uint32_t	PSC
	TIM prescaler, Address offset: 0x28.
__IO uint32_t	ARR
	TIM auto-reload register, Address offset: 0x2C.
__IO uint32_t	RCR
	TIM repetition counter register, Address offset: 0x30.
__IO uint32_t	CCR1
	TIM capture/compare register 1, Address offset: 0x34.
__IO uint32_t	CCR2
	TIM capture/compare register 2, Address offset: 0x38.
__IO uint32_t	CCR3
	TIM capture/compare register 3, Address offset: 0x3C.
__IO uint32_t	CCR4
	TIM capture/compare register 4, Address offset: 0x40.
__IO uint32_t	BDTR
	TIM break and dead-time register, Address offset: 0x44.
__IO uint32_t	DCR
	TIM DMA control register, Address offset: 0x48.
__IO uint32_t	DMAR
	TIM DMA address for full transfer, Address offset: 0x4C.
uint32_t	RESERVED1
	Reserved, 0x50.
__IO uint32_t	CCMR3
	TIM capture/compare mode register 3, Address offset: 0x54.
__IO uint32_t	CCR5
	TIM capture/compare register5, Address offset: 0x58.
__IO uint32_t	CCR6
	TIM capture/compare register6, Address offset: 0x5C.
__IO uint32_t	AF1
	TIM alternate function option register 1, Address offset: 0x60.
__IO uint32_t	AF2
	TIM alternate function option register 2, Address offset: 0x64.
__IO uint32_t	TISEL
	TIM Input Selection register, Address offset: 0x68.

Detailed Description

TIM.

Definition at line 1524 of file stm32h723xx.h.

Member Data Documentation

◆ AF1

__IO uint32_t TIM_TypeDef::AF1

TIM alternate function option register 1, Address offset: 0x60.

Definition at line 1550 of file stm32h723xx.h.

◆ AF2

__IO uint32_t TIM_TypeDef::AF2

TIM alternate function option register 2, Address offset: 0x64.

Definition at line 1551 of file stm32h723xx.h.

◆ ARR

__IO uint32_t TIM_TypeDef::ARR

TIM auto-reload register, Address offset: 0x2C.

Definition at line 1537 of file stm32h723xx.h.

◆ BDTR

__IO uint32_t TIM_TypeDef::BDTR

TIM break and dead-time register, Address offset: 0x44.

Definition at line 1543 of file stm32h723xx.h.

◆ CCER

__IO uint32_t TIM_TypeDef::CCER

TIM capture/compare enable register, Address offset: 0x20.

Definition at line 1534 of file stm32h723xx.h.

◆ CCMR1

__IO uint32_t TIM_TypeDef::CCMR1

TIM capture/compare mode register 1, Address offset: 0x18.

Definition at line 1532 of file stm32h723xx.h.

◆ CCMR2

__IO uint32_t TIM_TypeDef::CCMR2

TIM capture/compare mode register 2, Address offset: 0x1C.

Definition at line 1533 of file stm32h723xx.h.

◆ CCMR3

__IO uint32_t TIM_TypeDef::CCMR3

TIM capture/compare mode register 3, Address offset: 0x54.

Definition at line 1547 of file stm32h723xx.h.

◆ CCR1

__IO uint32_t TIM_TypeDef::CCR1

TIM capture/compare register 1, Address offset: 0x34.

Definition at line 1539 of file stm32h723xx.h.

◆ CCR2

__IO uint32_t TIM_TypeDef::CCR2

TIM capture/compare register 2, Address offset: 0x38.

Definition at line 1540 of file stm32h723xx.h.

◆ CCR3

__IO uint32_t TIM_TypeDef::CCR3

TIM capture/compare register 3, Address offset: 0x3C.

Definition at line 1541 of file stm32h723xx.h.

◆ CCR4

__IO uint32_t TIM_TypeDef::CCR4

TIM capture/compare register 4, Address offset: 0x40.

Definition at line 1542 of file stm32h723xx.h.

◆ CCR5

__IO uint32_t TIM_TypeDef::CCR5

TIM capture/compare register5, Address offset: 0x58.

Definition at line 1548 of file stm32h723xx.h.

◆ CCR6

__IO uint32_t TIM_TypeDef::CCR6

TIM capture/compare register6, Address offset: 0x5C.

Definition at line 1549 of file stm32h723xx.h.

◆ CNT

__IO uint32_t TIM_TypeDef::CNT

TIM counter register, Address offset: 0x24.

Definition at line 1535 of file stm32h723xx.h.

◆ CR1

__IO uint32_t TIM_TypeDef::CR1

TIM control register 1, Address offset: 0x00.

Definition at line 1526 of file stm32h723xx.h.

◆ CR2

__IO uint32_t TIM_TypeDef::CR2

TIM control register 2, Address offset: 0x04.

Definition at line 1527 of file stm32h723xx.h.

◆ DCR

__IO uint32_t TIM_TypeDef::DCR

TIM DMA control register, Address offset: 0x48.

Definition at line 1544 of file stm32h723xx.h.

◆ DIER

__IO uint32_t TIM_TypeDef::DIER

TIM DMA/interrupt enable register, Address offset: 0x0C.

Definition at line 1529 of file stm32h723xx.h.

◆ DMAR

__IO uint32_t TIM_TypeDef::DMAR

TIM DMA address for full transfer, Address offset: 0x4C.

Definition at line 1545 of file stm32h723xx.h.

◆ EGR

__IO uint32_t TIM_TypeDef::EGR

TIM event generation register, Address offset: 0x14.

Definition at line 1531 of file stm32h723xx.h.

◆ PSC

__IO uint32_t TIM_TypeDef::PSC

TIM prescaler, Address offset: 0x28.

Definition at line 1536 of file stm32h723xx.h.

◆ RCR

__IO uint32_t TIM_TypeDef::RCR

TIM repetition counter register, Address offset: 0x30.

Definition at line 1538 of file stm32h723xx.h.

◆ RESERVED1

uint32_t TIM_TypeDef::RESERVED1

Reserved, 0x50.

Definition at line 1546 of file stm32h723xx.h.

◆ SMCR

__IO uint32_t TIM_TypeDef::SMCR

TIM slave mode control register, Address offset: 0x08.

Definition at line 1528 of file stm32h723xx.h.

◆ SR

__IO uint32_t TIM_TypeDef::SR

TIM status register, Address offset: 0x10.

Definition at line 1530 of file stm32h723xx.h.

◆ TISEL

__IO uint32_t TIM_TypeDef::TISEL

TIM Input Selection register, Address offset: 0x68.

Definition at line 1552 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes