20#ifndef STM32H7xx_LL_USART_H
21#define STM32H7xx_LL_USART_H
34#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
35 || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
47static const uint32_t USART_PRESCALER_TAB[] =
78#if defined(USE_FULL_LL_DRIVER)
88#if defined(USE_FULL_LL_DRIVER)
98 uint32_t PrescalerValue;
127 uint32_t TransferDirection;
133 uint32_t HardwareFlowControl;
139 uint32_t OverSampling;
145} LL_USART_InitTypeDef;
152 uint32_t ClockOutput;
159 uint32_t ClockPolarity;
173 uint32_t LastBitClockPulse;
181} LL_USART_ClockInitTypeDef;
197#define LL_USART_ICR_PECF USART_ICR_PECF
198#define LL_USART_ICR_FECF USART_ICR_FECF
199#define LL_USART_ICR_NECF USART_ICR_NECF
200#define LL_USART_ICR_ORECF USART_ICR_ORECF
201#define LL_USART_ICR_IDLECF USART_ICR_IDLECF
202#define LL_USART_ICR_TXFECF USART_ICR_TXFECF
203#define LL_USART_ICR_TCCF USART_ICR_TCCF
204#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
205#define LL_USART_ICR_LBDCF USART_ICR_LBDCF
206#define LL_USART_ICR_CTSCF USART_ICR_CTSCF
207#define LL_USART_ICR_RTOCF USART_ICR_RTOCF
208#define LL_USART_ICR_EOBCF USART_ICR_EOBCF
209#define LL_USART_ICR_UDRCF USART_ICR_UDRCF
210#define LL_USART_ICR_CMCF USART_ICR_CMCF
211#define LL_USART_ICR_WUCF USART_ICR_WUCF
220#define LL_USART_ISR_PE USART_ISR_PE
221#define LL_USART_ISR_FE USART_ISR_FE
222#define LL_USART_ISR_NE USART_ISR_NE
223#define LL_USART_ISR_ORE USART_ISR_ORE
224#define LL_USART_ISR_IDLE USART_ISR_IDLE
225#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
226#define LL_USART_ISR_TC USART_ISR_TC
227#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
228#define LL_USART_ISR_LBDF USART_ISR_LBDF
229#define LL_USART_ISR_CTSIF USART_ISR_CTSIF
230#define LL_USART_ISR_CTS USART_ISR_CTS
231#define LL_USART_ISR_RTOF USART_ISR_RTOF
232#define LL_USART_ISR_EOBF USART_ISR_EOBF
233#define LL_USART_ISR_UDR USART_ISR_UDR
234#define LL_USART_ISR_ABRE USART_ISR_ABRE
235#define LL_USART_ISR_ABRF USART_ISR_ABRF
236#define LL_USART_ISR_BUSY USART_ISR_BUSY
237#define LL_USART_ISR_CMF USART_ISR_CMF
238#define LL_USART_ISR_SBKF USART_ISR_SBKF
239#define LL_USART_ISR_RWU USART_ISR_RWU
240#define LL_USART_ISR_WUF USART_ISR_WUF
241#define LL_USART_ISR_TEACK USART_ISR_TEACK
242#define LL_USART_ISR_REACK USART_ISR_REACK
243#define LL_USART_ISR_TXFE USART_ISR_TXFE
244#define LL_USART_ISR_RXFF USART_ISR_RXFF
245#define LL_USART_ISR_TCBGT USART_ISR_TCBGT
246#define LL_USART_ISR_RXFT USART_ISR_RXFT
247#define LL_USART_ISR_TXFT USART_ISR_TXFT
256#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
257#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
258#define LL_USART_CR1_TCIE USART_CR1_TCIE
259#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
260#define LL_USART_CR1_PEIE USART_CR1_PEIE
261#define LL_USART_CR1_CMIE USART_CR1_CMIE
262#define LL_USART_CR1_RTOIE USART_CR1_RTOIE
263#define LL_USART_CR1_EOBIE USART_CR1_EOBIE
264#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
265#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
266#define LL_USART_CR2_LBDIE USART_CR2_LBDIE
267#define LL_USART_CR3_EIE USART_CR3_EIE
268#define LL_USART_CR3_CTSIE USART_CR3_CTSIE
269#define LL_USART_CR3_WUFIE USART_CR3_WUFIE
270#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
271#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
272#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE
280#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
281#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
282#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
283#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
284#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
285#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U
293#define LL_USART_DIRECTION_NONE 0x00000000U
294#define LL_USART_DIRECTION_RX USART_CR1_RE
295#define LL_USART_DIRECTION_TX USART_CR1_TE
296#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
304#define LL_USART_PARITY_NONE 0x00000000U
305#define LL_USART_PARITY_EVEN USART_CR1_PCE
306#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
314#define LL_USART_WAKEUP_IDLELINE 0x00000000U
315#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
323#define LL_USART_DATAWIDTH_7B USART_CR1_M1
324#define LL_USART_DATAWIDTH_8B 0x00000000U
325#define LL_USART_DATAWIDTH_9B USART_CR1_M0
333#define LL_USART_OVERSAMPLING_16 0x00000000U
334#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
339#if defined(USE_FULL_LL_DRIVER)
344#define LL_USART_CLOCK_DISABLE 0x00000000U
345#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
354#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
355#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
363#define LL_USART_PHASE_1EDGE 0x00000000U
364#define LL_USART_PHASE_2EDGE USART_CR2_CPHA
372#define LL_USART_POLARITY_LOW 0x00000000U
373#define LL_USART_POLARITY_HIGH USART_CR2_CPOL
381#define LL_USART_PRESCALER_DIV1 0x00000000U
382#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
383#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
384#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
385#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
386#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
387#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
388#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
389#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
390#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
391#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
392#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
400#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
401#define LL_USART_STOPBITS_1 0x00000000U
402#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
403#define LL_USART_STOPBITS_2 USART_CR2_STOP_1
411#define LL_USART_TXRX_STANDARD 0x00000000U
412#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
420#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
421#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
429#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
430#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
438#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
439#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
447#define LL_USART_BITORDER_LSBFIRST 0x00000000U
448#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
456#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
457#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
458#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
459#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
467#define LL_USART_ADDRESS_DETECT_4B 0x00000000U
468#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
476#define LL_USART_HWCONTROL_NONE 0x00000000U
477#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE
478#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE
479#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
487#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
488#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
489#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
497#define LL_USART_IRDA_POWER_NORMAL 0x00000000U
498#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
506#define LL_USART_LINBREAK_DETECT_10B 0x00000000U
507#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
515#define LL_USART_DE_POLARITY_HIGH 0x00000000U
516#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP
524#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
525#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U
550#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
558#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
587#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
588 (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
589 + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
611#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
612 ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
613 + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
1887 uint32_t OverSampling,
1893 if (PrescalerValue > LL_USART_PRESCALER_DIV256)
1897 else if (BaudRate == 0U)
1901 else if (OverSampling == LL_USART_OVERSAMPLING_8)
1903 usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
1904 brrtemp = usartdiv & 0xFFF0U;
1905 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
1906 USARTx->
BRR = brrtemp;
1910 USARTx->
BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
1941 uint32_t OverSampling)
1944 uint32_t brrresult = 0x0U;
1945 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
1947 usartdiv = USARTx->
BRR;
1953 else if (OverSampling == LL_USART_OVERSAMPLING_8)
1955 usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
1958 brrresult = (periphclkpresc * 2U) / usartdiv;
1963 if ((usartdiv & 0xFFFFU) != 0U)
1965 brrresult = periphclkpresc / usartdiv;
2992#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
3018#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
3473#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
3499#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
3688#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
3714#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
3905#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
3931#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
4226 uint32_t data_reg_addr;
4228 if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
4231 data_reg_addr = (uint32_t) &(USARTx->
TDR);
4236 data_reg_addr = (uint32_t) &(USARTx->
RDR);
4239 return data_reg_addr;
4281 USARTx->
TDR = Value;
4293 USARTx->
TDR = (uint16_t)(Value & 0x1FFUL);
4371#if defined(USE_FULL_LL_DRIVER)
4377void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
4379void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
#define ATOMIC_CLEAR_BIT(REG, BIT)
#define CLEAR_BIT(REG, BIT)
#define SET_BIT(REG, BIT)
#define WRITE_REG(REG, VAL)
#define ATOMIC_SET_BIT(REG, BIT)
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
#define READ_BIT(REG, BIT)
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
#define USART_ICR_WUCF
Wake Up from stop mode Clear Flag.
#define USART_ISR_NE
Noise detected Flag.
#define USART_ISR_RTOF
Receiver Time Out.
#define USART_ISR_RWU
Receive Wake Up from mute mode Flag.
#define USART_CR3_TCBGTIE
Transmission Complete before guard time, interrupt enable.
#define USART_CR2_SLVEN
Synchronous Slave mode Enable.
#define USART_RTOR_BLEN
Block Length.
#define USART_ISR_TXE_TXFNF
Transmit Data Register Empty or TX FIFO Not Full Flag.
#define USART_ISR_TXFT
TXFIFO threshold Flag.
#define USART_CR1_UESM
USART Enable in STOP Mode.
#define USART_CR3_DEP
Driver Enable Polarity Selection.
#define USART_GTPR_GT_Pos
#define USART_CR3_IRLP
IrDA Low-Power.
#define USART_PRESC_PRESCALER
PRESCALER[3:0] bits (Clock prescaler).
#define USART_CR1_PEIE
PE Interrupt Enable.
#define USART_ISR_FE
Framing Error.
#define USART_RQR_MMRQ
Mute Mode Request.
#define USART_CR2_STOP_1
0x00002000
#define USART_CR1_UE
USART Enable.
#define USART_CR2_ADD_Pos
#define USART_RQR_SBKRQ
Send Break Request.
#define USART_CR2_ADDM7
7-bit or 4-bit Address Detection
#define USART_CR1_PS
Parity Selection.
#define USART_CR3_IREN
IrDA mode Enable.
#define USART_ISR_EOBF
End Of Block Flag.
#define USART_CR3_OVRDIS
Overrun Disable.
#define USART_CR2_CPHA
Clock Phase.
#define USART_ICR_ORECF
OverRun Error Clear Flag.
#define USART_ICR_RTOCF
Receiver Time Out Clear Flag.
#define USART_CR2_ADD
Address of the USART node.
#define USART_CR3_NACK
SmartCard NACK enable.
#define USART_CR3_TXFTCFG
TXFIFO [2:0] threshold configuration.
#define USART_CR3_SCARCNT_Pos
#define USART_ICR_PECF
Parity Error Clear Flag.
#define USART_CR2_CLKEN
Clock Enable.
#define USART_ICR_EOBCF
End Of Block Clear Flag.
#define USART_ICR_TCBGTCF
Transmission complete before guard time Clear Flag.
#define USART_ICR_TXFECF
TXFIFO empty clear flag.
#define USART_CR3_RXFTIE
RXFIFO threshold interrupt enable.
#define USART_CR2_LBCL
Last Bit Clock pulse.
#define USART_CR1_MME
Mute Mode Enable.
#define USART_CR2_SWAP
SWAP TX/RX pins.
#define USART_CR1_IDLEIE
IDLE Interrupt Enable.
#define USART_ICR_CMCF
Character Match Clear Flag.
#define USART_CR3_TXFTIE
TXFIFO threshold interrupt enable.
#define USART_CR3_DMAT
DMA Enable Transmitter.
#define USART_RTOR_RTO
Receiver Time Out Value.
#define USART_CR1_PCE
Parity Control Enable.
#define USART_CR3_CTSIE
CTS Interrupt Enable.
#define USART_CR3_RXFTCFG_Pos
#define USART_CR1_DEAT
DEAT[4:0] bits (Driver Enable Assertion Time).
#define USART_CR1_RXFFIE
RXFIFO Full interrupt enable.
#define USART_CR2_MSBFIRST
Most Significant Bit First.
#define USART_ISR_SBKF
Send Break Flag.
#define USART_CR1_DEAT_Pos
#define USART_CR3_WUS
WUS[1:0] bits (Wake UP Interrupt Flag Selection).
#define USART_CR2_ABRMODE
ABRMOD[1:0] bits (Auto Baud-Rate Mode).
#define USART_RQR_RXFRQ
Receive Data flush Request.
#define USART_CR3_RTSE
RTS Enable.
#define USART_CR2_LBDL
LIN Break Detection Length.
#define USART_CR3_WUFIE
Wake Up Interrupt Enable.
#define USART_ISR_CMF
Character Match Flag.
#define USART_CR1_RXNEIE_RXFNEIE
RXNE and RX FIFO Not Empty Interrupt Enable.
#define USART_ICR_FECF
Framing Error Clear Flag.
#define USART_ISR_CTS
CTS flag.
#define USART_ICR_CTSCF
CTS Interrupt Clear Flag.
#define USART_GTPR_GT
GT[7:0] bits (Guard time value).
#define USART_CR2_DATAINV
Binary data inversion.
#define USART_CR3_SCEN
SmartCard mode enable.
#define USART_CR1_TXEIE_TXFNFIE
TXE and TX FIFO Not Full Interrupt Enable.
#define USART_CR1_M
Word length.
#define USART_CR3_ONEBIT
One sample bit method enable.
#define USART_ICR_IDLECF
IDLE line detected Clear Flag.
#define USART_ISR_ORE
OverRun Error.
#define USART_ISR_CTSIF
CTS interrupt flag.
#define USART_CR2_LBDIE
LIN Break Detection Interrupt Enable.
#define USART_GTPR_PSC
PSC[7:0] bits (Prescaler value).
#define USART_ISR_PE
Parity Error.
#define USART_CR3_CTSE
CTS Enable.
#define USART_CR1_TCIE
Transmission Complete Interrupt Enable.
#define USART_RQR_TXFRQ
Transmit data flush Request.
#define USART_ISR_TC
Transmission Complete.
#define USART_ISR_REACK
Receive Enable Acknowledge Flag.
#define USART_CR2_ABREN
Auto Baud-Rate Enable.
#define USART_ISR_RXFF
RXFIFO Full Flag.
#define USART_CR1_CMIE
Character match interrupt enable.
#define USART_ICR_LBDCF
LIN Break Detection Clear Flag.
#define USART_CR3_EIE
Error Interrupt Enable.
#define USART_CR3_TXFTCFG_Pos
#define USART_CR1_DEDT
DEDT[4:0] bits (Driver Enable Deassertion Time).
#define USART_CR1_TXFEIE
TXFIFO empty interrupt enable.
#define USART_CR2_RTOEN
Receiver Time-Out enable.
#define USART_CR3_RXFTCFG
RXFTCFG [2:0]Receive FIFO threshold configuration.
#define USART_ISR_RXNE_RXFNE
Read Data Register or RX FIFO Not Empty.
#define USART_CR1_RTOIE
Receive Time Out interrupt enable.
#define USART_ICR_UDRCF
SPI slave underrun clear flag.
#define USART_CR3_SCARCNT
SCARCNT[2:0] bits (SmartCard Auto-Retry Count).
#define USART_CR3_HDSEL
Half-Duplex Selection.
#define USART_CR2_LINEN
LIN mode enable.
#define USART_ICR_NECF
Noise detected Clear Flag.
#define USART_CR3_DEM
Driver Enable Mode.
#define USART_ISR_IDLE
IDLE line detected.
#define USART_ICR_TCCF
Transmission Complete Clear Flag.
#define USART_RQR_ABRRQ
Auto-Baud Rate Request.
#define USART_CR2_DIS_NSS
Negative Slave Select (NSS) pin management.
#define USART_CR1_WAKE
Receiver Wakeup method.
#define USART_ISR_WUF
Wake Up from stop mode Flag.
#define USART_CR1_RE
Receiver Enable.
#define USART_RTOR_BLEN_Pos
#define USART_CR2_TXINV
TX pin active level inversion.
#define USART_CR1_TE
Transmitter Enable.
#define USART_CR1_DEDT_Pos
#define USART_CR3_DDRE
DMA Disable on Reception Error.
#define USART_CR1_EOBIE
End of Block interrupt enable.
#define USART_ISR_ABRE
Auto-Baud Rate Error.
#define USART_ISR_RXFT
RXFIFO threshold Flag.
#define USART_ISR_TCBGT
Transmission complete before guard time Flag.
#define USART_RDR_RDR
RDR[8:0] bits (Receive Data value).
#define USART_CR1_OVER8
Oversampling by 8-bit or 16-bit mode.
#define USART_CR2_STOP_0
0x00001000
#define USART_ISR_UDR
SPI slave underrun error flag.
#define USART_ISR_LBDF
LIN Break Detection Flag.
#define USART_ISR_TEACK
Transmit Enable Acknowledge Flag.
#define USART_ISR_TXFE
TXFIFO Empty.
#define USART_CR2_STOP
STOP[1:0] bits (STOP bits).
#define USART_CR1_FIFOEN
FIFO mode enable.
#define USART_ISR_BUSY
Busy Flag.
#define USART_CR2_CPOL
Clock Polarity.
#define USART_ISR_ABRF
Auto-Baud Rate Flag.
#define USART_CR3_DMAR
DMA Enable Receiver.
#define USART_CR2_RXINV
RX pin active level inversion.
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
Universal Synchronous Asynchronous Receiver Transmitter.
__IO uint32_t TDR
USART Transmit Data register, Address offset: 0x28.
__IO uint32_t RTOR
USART Receiver Time Out register, Address offset: 0x14.
__IO uint32_t CR1
USART Control register 1, Address offset: 0x00.
__IO uint32_t BRR
USART Baud rate register, Address offset: 0x0C.
__IO uint32_t ISR
USART Interrupt and status register, Address offset: 0x1C.
__IO uint32_t RDR
USART Receive Data register, Address offset: 0x24.
__IO uint32_t CR2
USART Control register 2, Address offset: 0x04.
__IO uint32_t ICR
USART Interrupt flag Clear register, Address offset: 0x20.
__IO uint32_t PRESC
USART clock Prescaler register, Address offset: 0x2C.
__IO uint32_t RQR
USART Request register, Address offset: 0x18.
__IO uint32_t GTPR
USART Guard time and prescaler register, Address offset: 0x10.
__IO uint32_t CR3
USART Control register 3, Address offset: 0x08.