Digital to Analog Converter. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR
	DAC control register, Address offset: 0x00.
__IO uint32_t	SWTRIGR
	DAC software trigger register, Address offset: 0x04.
__IO uint32_t	DHR12R1
	DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08.
__IO uint32_t	DHR12L1
	DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C.
__IO uint32_t	DHR8R1
	DAC channel1 8-bit right aligned data holding register, Address offset: 0x10.
__IO uint32_t	DHR12R2
	DAC channel2 12-bit right aligned data holding register, Address offset: 0x14.
__IO uint32_t	DHR12L2
	DAC channel2 12-bit left aligned data holding register, Address offset: 0x18.
__IO uint32_t	DHR8R2
	DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C.
__IO uint32_t	DHR12RD
	Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20.
__IO uint32_t	DHR12LD
	DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24.
__IO uint32_t	DHR8RD
	DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28.
__IO uint32_t	DOR1
	DAC channel1 data output register, Address offset: 0x2C.
__IO uint32_t	DOR2
	DAC channel2 data output register, Address offset: 0x30.
__IO uint32_t	SR
	DAC status register, Address offset: 0x34.
__IO uint32_t	CCR
	DAC calibration control register, Address offset: 0x38.
__IO uint32_t	MCR
	DAC mode control register, Address offset: 0x3C.
__IO uint32_t	SHSR1
	DAC Sample and Hold sample time register 1, Address offset: 0x40.
__IO uint32_t	SHSR2
	DAC Sample and Hold sample time register 2, Address offset: 0x44.
__IO uint32_t	SHHR
	DAC Sample and Hold hold time register, Address offset: 0x48.
__IO uint32_t	SHRR
	DAC Sample and Hold refresh time register, Address offset: 0x4C.

Detailed Description

Digital to Analog Converter.

Definition at line 468 of file stm32h723xx.h.

Member Data Documentation

◆ CCR

__IO uint32_t DAC_TypeDef::CCR

DAC calibration control register, Address offset: 0x38.

Definition at line 484 of file stm32h723xx.h.

◆ CR

__IO uint32_t DAC_TypeDef::CR

DAC control register, Address offset: 0x00.

Definition at line 470 of file stm32h723xx.h.

◆ DHR12L1

__IO uint32_t DAC_TypeDef::DHR12L1

DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C.

Definition at line 473 of file stm32h723xx.h.

◆ DHR12L2

__IO uint32_t DAC_TypeDef::DHR12L2

DAC channel2 12-bit left aligned data holding register, Address offset: 0x18.

Definition at line 476 of file stm32h723xx.h.

◆ DHR12LD

__IO uint32_t DAC_TypeDef::DHR12LD

DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24.

Definition at line 479 of file stm32h723xx.h.

◆ DHR12R1

__IO uint32_t DAC_TypeDef::DHR12R1

DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08.

Definition at line 472 of file stm32h723xx.h.

◆ DHR12R2

__IO uint32_t DAC_TypeDef::DHR12R2

DAC channel2 12-bit right aligned data holding register, Address offset: 0x14.

Definition at line 475 of file stm32h723xx.h.

◆ DHR12RD

__IO uint32_t DAC_TypeDef::DHR12RD

Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20.

Definition at line 478 of file stm32h723xx.h.

◆ DHR8R1

__IO uint32_t DAC_TypeDef::DHR8R1

DAC channel1 8-bit right aligned data holding register, Address offset: 0x10.

Definition at line 474 of file stm32h723xx.h.

◆ DHR8R2

__IO uint32_t DAC_TypeDef::DHR8R2

DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C.

Definition at line 477 of file stm32h723xx.h.

◆ DHR8RD

__IO uint32_t DAC_TypeDef::DHR8RD

DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28.

Definition at line 480 of file stm32h723xx.h.

◆ DOR1

__IO uint32_t DAC_TypeDef::DOR1

DAC channel1 data output register, Address offset: 0x2C.

Definition at line 481 of file stm32h723xx.h.

◆ DOR2

__IO uint32_t DAC_TypeDef::DOR2

DAC channel2 data output register, Address offset: 0x30.

Definition at line 482 of file stm32h723xx.h.

◆ MCR

__IO uint32_t DAC_TypeDef::MCR

DAC mode control register, Address offset: 0x3C.

Definition at line 485 of file stm32h723xx.h.

◆ SHHR

__IO uint32_t DAC_TypeDef::SHHR

DAC Sample and Hold hold time register, Address offset: 0x48.

Definition at line 488 of file stm32h723xx.h.

◆ SHRR

__IO uint32_t DAC_TypeDef::SHRR

DAC Sample and Hold refresh time register, Address offset: 0x4C.

Definition at line 489 of file stm32h723xx.h.

◆ SHSR1

__IO uint32_t DAC_TypeDef::SHSR1

DAC Sample and Hold sample time register 1, Address offset: 0x40.

Definition at line 486 of file stm32h723xx.h.

◆ SHSR2

__IO uint32_t DAC_TypeDef::SHSR2

DAC Sample and Hold sample time register 2, Address offset: 0x44.

Definition at line 487 of file stm32h723xx.h.

◆ SR

__IO uint32_t DAC_TypeDef::SR

DAC status register, Address offset: 0x34.

Definition at line 483 of file stm32h723xx.h.

◆ SWTRIGR

__IO uint32_t DAC_TypeDef::SWTRIGR

DAC software trigger register, Address offset: 0x04.

Definition at line 471 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes