DCMI. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR
	DCMI control register 1, Address offset: 0x00.
__IO uint32_t	SR
	DCMI status register, Address offset: 0x04.
__IO uint32_t	RISR
	DCMI raw interrupt status register, Address offset: 0x08.
__IO uint32_t	IER
	DCMI interrupt enable register, Address offset: 0x0C.
__IO uint32_t	MISR
	DCMI masked interrupt status register, Address offset: 0x10.
__IO uint32_t	ICR
	DCMI interrupt clear register, Address offset: 0x14.
__IO uint32_t	ESCR
	DCMI embedded synchronization code register, Address offset: 0x18.
__IO uint32_t	ESUR
	DCMI embedded synchronization unmask register, Address offset: 0x1C.
__IO uint32_t	CWSTRTR
	DCMI crop window start, Address offset: 0x20.
__IO uint32_t	CWSIZER
	DCMI crop window size, Address offset: 0x24.
__IO uint32_t	DR
	DCMI data register, Address offset: 0x28.

Detailed Description

DCMI.

Definition at line 560 of file stm32h723xx.h.

Member Data Documentation

◆ CR

__IO uint32_t DCMI_TypeDef::CR

DCMI control register 1, Address offset: 0x00.

Definition at line 562 of file stm32h723xx.h.

◆ CWSIZER

__IO uint32_t DCMI_TypeDef::CWSIZER

DCMI crop window size, Address offset: 0x24.

Definition at line 571 of file stm32h723xx.h.

◆ CWSTRTR

__IO uint32_t DCMI_TypeDef::CWSTRTR

DCMI crop window start, Address offset: 0x20.

Definition at line 570 of file stm32h723xx.h.

◆ DR

__IO uint32_t DCMI_TypeDef::DR

DCMI data register, Address offset: 0x28.

Definition at line 572 of file stm32h723xx.h.

◆ ESCR

__IO uint32_t DCMI_TypeDef::ESCR

DCMI embedded synchronization code register, Address offset: 0x18.

Definition at line 568 of file stm32h723xx.h.

◆ ESUR

__IO uint32_t DCMI_TypeDef::ESUR

DCMI embedded synchronization unmask register, Address offset: 0x1C.

Definition at line 569 of file stm32h723xx.h.

◆ ICR

__IO uint32_t DCMI_TypeDef::ICR

DCMI interrupt clear register, Address offset: 0x14.

Definition at line 567 of file stm32h723xx.h.

◆ IER

__IO uint32_t DCMI_TypeDef::IER

DCMI interrupt enable register, Address offset: 0x0C.

Definition at line 565 of file stm32h723xx.h.

◆ MISR

__IO uint32_t DCMI_TypeDef::MISR

DCMI masked interrupt status register, Address offset: 0x10.

Definition at line 566 of file stm32h723xx.h.

◆ RISR

__IO uint32_t DCMI_TypeDef::RISR

DCMI raw interrupt status register, Address offset: 0x08.

Definition at line 564 of file stm32h723xx.h.

◆ SR

__IO uint32_t DCMI_TypeDef::SR

DCMI status register, Address offset: 0x04.

Definition at line 563 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes