DMA2D Controller. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR
	DMA2D Control Register, Address offset: 0x00.
__IO uint32_t	ISR
	DMA2D Interrupt Status Register, Address offset: 0x04.
__IO uint32_t	IFCR
	DMA2D Interrupt Flag Clear Register, Address offset: 0x08.
__IO uint32_t	FGMAR
	DMA2D Foreground Memory Address Register, Address offset: 0x0C.
__IO uint32_t	FGOR
	DMA2D Foreground Offset Register, Address offset: 0x10.
__IO uint32_t	BGMAR
	DMA2D Background Memory Address Register, Address offset: 0x14.
__IO uint32_t	BGOR
	DMA2D Background Offset Register, Address offset: 0x18.
__IO uint32_t	FGPFCCR
	DMA2D Foreground PFC Control Register, Address offset: 0x1C.
__IO uint32_t	FGCOLR
	DMA2D Foreground Color Register, Address offset: 0x20.
__IO uint32_t	BGPFCCR
	DMA2D Background PFC Control Register, Address offset: 0x24.
__IO uint32_t	BGCOLR
	DMA2D Background Color Register, Address offset: 0x28.
__IO uint32_t	FGCMAR
	DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C.
__IO uint32_t	BGCMAR
	DMA2D Background CLUT Memory Address Register, Address offset: 0x30.
__IO uint32_t	OPFCCR
	DMA2D Output PFC Control Register, Address offset: 0x34.
__IO uint32_t	OCOLR
	DMA2D Output Color Register, Address offset: 0x38.
__IO uint32_t	OMAR
	DMA2D Output Memory Address Register, Address offset: 0x3C.
__IO uint32_t	OOR
	DMA2D Output Offset Register, Address offset: 0x40.
__IO uint32_t	NLR
	DMA2D Number of Line Register, Address offset: 0x44.
__IO uint32_t	LWR
	DMA2D Line Watermark Register, Address offset: 0x48.
__IO uint32_t	AMTCR
	DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C.
uint32_t	RESERVED [236]
	Reserved, 0x50-0x3FF.
__IO uint32_t	FGCLUT [256]
	DMA2D Foreground CLUT, Address offset:400-7FF.
__IO uint32_t	BGCLUT [256]
	DMA2D Background CLUT, Address offset:800-BFF.

Detailed Description

DMA2D Controller.

Definition at line 685 of file stm32h723xx.h.

Member Data Documentation

◆ AMTCR

__IO uint32_t DMA2D_TypeDef::AMTCR

DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C.

Definition at line 706 of file stm32h723xx.h.

◆ BGCLUT

__IO uint32_t DMA2D_TypeDef::BGCLUT[256]

DMA2D Background CLUT, Address offset:800-BFF.

Definition at line 709 of file stm32h723xx.h.

◆ BGCMAR

__IO uint32_t DMA2D_TypeDef::BGCMAR

DMA2D Background CLUT Memory Address Register, Address offset: 0x30.

Definition at line 699 of file stm32h723xx.h.

◆ BGCOLR

__IO uint32_t DMA2D_TypeDef::BGCOLR

DMA2D Background Color Register, Address offset: 0x28.

Definition at line 697 of file stm32h723xx.h.

◆ BGMAR

__IO uint32_t DMA2D_TypeDef::BGMAR

DMA2D Background Memory Address Register, Address offset: 0x14.

Definition at line 692 of file stm32h723xx.h.

◆ BGOR

__IO uint32_t DMA2D_TypeDef::BGOR

DMA2D Background Offset Register, Address offset: 0x18.

Definition at line 693 of file stm32h723xx.h.

◆ BGPFCCR

__IO uint32_t DMA2D_TypeDef::BGPFCCR

DMA2D Background PFC Control Register, Address offset: 0x24.

Definition at line 696 of file stm32h723xx.h.

◆ CR

__IO uint32_t DMA2D_TypeDef::CR

DMA2D Control Register, Address offset: 0x00.

Definition at line 687 of file stm32h723xx.h.

◆ FGCLUT

__IO uint32_t DMA2D_TypeDef::FGCLUT[256]

DMA2D Foreground CLUT, Address offset:400-7FF.

Definition at line 708 of file stm32h723xx.h.

◆ FGCMAR

__IO uint32_t DMA2D_TypeDef::FGCMAR

DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C.

Definition at line 698 of file stm32h723xx.h.

◆ FGCOLR

__IO uint32_t DMA2D_TypeDef::FGCOLR

DMA2D Foreground Color Register, Address offset: 0x20.

Definition at line 695 of file stm32h723xx.h.

◆ FGMAR

__IO uint32_t DMA2D_TypeDef::FGMAR

DMA2D Foreground Memory Address Register, Address offset: 0x0C.

Definition at line 690 of file stm32h723xx.h.

◆ FGOR

__IO uint32_t DMA2D_TypeDef::FGOR

DMA2D Foreground Offset Register, Address offset: 0x10.

Definition at line 691 of file stm32h723xx.h.

◆ FGPFCCR

__IO uint32_t DMA2D_TypeDef::FGPFCCR

DMA2D Foreground PFC Control Register, Address offset: 0x1C.

Definition at line 694 of file stm32h723xx.h.

◆ IFCR

__IO uint32_t DMA2D_TypeDef::IFCR

DMA2D Interrupt Flag Clear Register, Address offset: 0x08.

Definition at line 689 of file stm32h723xx.h.

◆ ISR

__IO uint32_t DMA2D_TypeDef::ISR

DMA2D Interrupt Status Register, Address offset: 0x04.

Definition at line 688 of file stm32h723xx.h.

◆ LWR

__IO uint32_t DMA2D_TypeDef::LWR

DMA2D Line Watermark Register, Address offset: 0x48.

Definition at line 705 of file stm32h723xx.h.

◆ NLR

__IO uint32_t DMA2D_TypeDef::NLR

DMA2D Number of Line Register, Address offset: 0x44.

Definition at line 704 of file stm32h723xx.h.

◆ OCOLR

__IO uint32_t DMA2D_TypeDef::OCOLR

DMA2D Output Color Register, Address offset: 0x38.

Definition at line 701 of file stm32h723xx.h.

◆ OMAR

__IO uint32_t DMA2D_TypeDef::OMAR

DMA2D Output Memory Address Register, Address offset: 0x3C.

Definition at line 702 of file stm32h723xx.h.

◆ OOR

__IO uint32_t DMA2D_TypeDef::OOR

DMA2D Output Offset Register, Address offset: 0x40.

Definition at line 703 of file stm32h723xx.h.

◆ OPFCCR

__IO uint32_t DMA2D_TypeDef::OPFCCR

DMA2D Output PFC Control Register, Address offset: 0x34.

Definition at line 700 of file stm32h723xx.h.

◆ RESERVED

uint32_t DMA2D_TypeDef::RESERVED[236]

Reserved, 0x50-0x3FF.

Definition at line 707 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes