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FDCAN_GlobalTypeDef Struct Reference
CMSIS_Device » Stm32h723xx » Peripheral_registers_structures

FD Controller Area Network. More...

#include <stm32h723xx.h>

Public Attributes

__IO uint32_t CREL
 FDCAN Core Release register, Address offset: 0x000.
__IO uint32_t ENDN
 FDCAN Endian register, Address offset: 0x004.
__IO uint32_t RESERVED1
 Reserved, 0x008.
__IO uint32_t DBTP
 FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C.
__IO uint32_t TEST
 FDCAN Test register, Address offset: 0x010.
__IO uint32_t RWD
 FDCAN RAM Watchdog register, Address offset: 0x014.
__IO uint32_t CCCR
 FDCAN CC Control register, Address offset: 0x018.
__IO uint32_t NBTP
 FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C.
__IO uint32_t TSCC
 FDCAN Timestamp Counter Configuration register, Address offset: 0x020.
__IO uint32_t TSCV
 FDCAN Timestamp Counter Value register, Address offset: 0x024.
__IO uint32_t TOCC
 FDCAN Timeout Counter Configuration register, Address offset: 0x028.
__IO uint32_t TOCV
 FDCAN Timeout Counter Value register, Address offset: 0x02C.
__IO uint32_t RESERVED2 [4]
 Reserved, 0x030 - 0x03C.
__IO uint32_t ECR
 FDCAN Error Counter register, Address offset: 0x040.
__IO uint32_t PSR
 FDCAN Protocol Status register, Address offset: 0x044.
__IO uint32_t TDCR
 FDCAN Transmitter Delay Compensation register, Address offset: 0x048.
__IO uint32_t RESERVED3
 Reserved, 0x04C.
__IO uint32_t IR
 FDCAN Interrupt register, Address offset: 0x050.
__IO uint32_t IE
 FDCAN Interrupt Enable register, Address offset: 0x054.
__IO uint32_t ILS
 FDCAN Interrupt Line Select register, Address offset: 0x058.
__IO uint32_t ILE
 FDCAN Interrupt Line Enable register, Address offset: 0x05C.
__IO uint32_t RESERVED4 [8]
 Reserved, 0x060 - 0x07C.
__IO uint32_t GFC
 FDCAN Global Filter Configuration register, Address offset: 0x080.
__IO uint32_t SIDFC
 FDCAN Standard ID Filter Configuration register, Address offset: 0x084.
__IO uint32_t XIDFC
 FDCAN Extended ID Filter Configuration register, Address offset: 0x088.
__IO uint32_t RESERVED5
 Reserved, 0x08C.
__IO uint32_t XIDAM
 FDCAN Extended ID AND Mask register, Address offset: 0x090.
__IO uint32_t HPMS
 FDCAN High Priority Message Status register, Address offset: 0x094.
__IO uint32_t NDAT1
 FDCAN New Data 1 register, Address offset: 0x098.
__IO uint32_t NDAT2
 FDCAN New Data 2 register, Address offset: 0x09C.
__IO uint32_t RXF0C
 FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0.
__IO uint32_t RXF0S
 FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4.
__IO uint32_t RXF0A
 FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8.
__IO uint32_t RXBC
 FDCAN Rx Buffer Configuration register, Address offset: 0x0AC.
__IO uint32_t RXF1C
 FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0.
__IO uint32_t RXF1S
 FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4.
__IO uint32_t RXF1A
 FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8.
__IO uint32_t RXESC
 FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC.
__IO uint32_t TXBC
 FDCAN Tx Buffer Configuration register, Address offset: 0x0C0.
__IO uint32_t TXFQS
 FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4.
__IO uint32_t TXESC
 FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8.
__IO uint32_t TXBRP
 FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC.
__IO uint32_t TXBAR
 FDCAN Tx Buffer Add Request register, Address offset: 0x0D0.
__IO uint32_t TXBCR
 FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4.
__IO uint32_t TXBTO
 FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8.
__IO uint32_t TXBCF
 FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC.
__IO uint32_t TXBTIE
 FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0.
__IO uint32_t TXBCIE
 FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4.
__IO uint32_t RESERVED6 [2]
 Reserved, 0x0E8 - 0x0EC.
__IO uint32_t TXEFC
 FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0.
__IO uint32_t TXEFS
 FDCAN Tx Event FIFO Status register, Address offset: 0x0F4.
__IO uint32_t TXEFA
 FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8.
__IO uint32_t RESERVED7
 Reserved, 0x0FC.

Detailed Description

FD Controller Area Network.

Definition at line 314 of file stm32h723xx.h.

Member Data Documentation

◆ CCCR

__IO uint32_t FDCAN_GlobalTypeDef::CCCR

FDCAN CC Control register, Address offset: 0x018.

Definition at line 322 of file stm32h723xx.h.

◆ CREL

__IO uint32_t FDCAN_GlobalTypeDef::CREL

FDCAN Core Release register, Address offset: 0x000.

Definition at line 316 of file stm32h723xx.h.

◆ DBTP

__IO uint32_t FDCAN_GlobalTypeDef::DBTP

FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C.

Definition at line 319 of file stm32h723xx.h.

◆ ECR

__IO uint32_t FDCAN_GlobalTypeDef::ECR

FDCAN Error Counter register, Address offset: 0x040.

Definition at line 329 of file stm32h723xx.h.

◆ ENDN

__IO uint32_t FDCAN_GlobalTypeDef::ENDN

FDCAN Endian register, Address offset: 0x004.

Definition at line 317 of file stm32h723xx.h.

◆ GFC

__IO uint32_t FDCAN_GlobalTypeDef::GFC

FDCAN Global Filter Configuration register, Address offset: 0x080.

Definition at line 338 of file stm32h723xx.h.

◆ HPMS

__IO uint32_t FDCAN_GlobalTypeDef::HPMS

FDCAN High Priority Message Status register, Address offset: 0x094.

Definition at line 343 of file stm32h723xx.h.

◆ IE

__IO uint32_t FDCAN_GlobalTypeDef::IE

FDCAN Interrupt Enable register, Address offset: 0x054.

Definition at line 334 of file stm32h723xx.h.

◆ ILE

__IO uint32_t FDCAN_GlobalTypeDef::ILE

FDCAN Interrupt Line Enable register, Address offset: 0x05C.

Definition at line 336 of file stm32h723xx.h.

◆ ILS

__IO uint32_t FDCAN_GlobalTypeDef::ILS

FDCAN Interrupt Line Select register, Address offset: 0x058.

Definition at line 335 of file stm32h723xx.h.

◆ IR

__IO uint32_t FDCAN_GlobalTypeDef::IR

FDCAN Interrupt register, Address offset: 0x050.

Definition at line 333 of file stm32h723xx.h.

◆ NBTP

__IO uint32_t FDCAN_GlobalTypeDef::NBTP

FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C.

Definition at line 323 of file stm32h723xx.h.

◆ NDAT1

__IO uint32_t FDCAN_GlobalTypeDef::NDAT1

FDCAN New Data 1 register, Address offset: 0x098.

Definition at line 344 of file stm32h723xx.h.

◆ NDAT2

__IO uint32_t FDCAN_GlobalTypeDef::NDAT2

FDCAN New Data 2 register, Address offset: 0x09C.

Definition at line 345 of file stm32h723xx.h.

◆ PSR

__IO uint32_t FDCAN_GlobalTypeDef::PSR

FDCAN Protocol Status register, Address offset: 0x044.

Definition at line 330 of file stm32h723xx.h.

◆ RESERVED1

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED1

Reserved, 0x008.

Definition at line 318 of file stm32h723xx.h.

◆ RESERVED2

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED2[4]

Reserved, 0x030 - 0x03C.

Definition at line 328 of file stm32h723xx.h.

◆ RESERVED3

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED3

Reserved, 0x04C.

Definition at line 332 of file stm32h723xx.h.

◆ RESERVED4

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED4[8]

Reserved, 0x060 - 0x07C.

Definition at line 337 of file stm32h723xx.h.

◆ RESERVED5

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED5

Reserved, 0x08C.

Definition at line 341 of file stm32h723xx.h.

◆ RESERVED6

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED6[2]

Reserved, 0x0E8 - 0x0EC.

Definition at line 364 of file stm32h723xx.h.

◆ RESERVED7

__IO uint32_t FDCAN_GlobalTypeDef::RESERVED7

Reserved, 0x0FC.

Definition at line 368 of file stm32h723xx.h.

◆ RWD

__IO uint32_t FDCAN_GlobalTypeDef::RWD

FDCAN RAM Watchdog register, Address offset: 0x014.

Definition at line 321 of file stm32h723xx.h.

◆ RXBC

__IO uint32_t FDCAN_GlobalTypeDef::RXBC

FDCAN Rx Buffer Configuration register, Address offset: 0x0AC.

Definition at line 349 of file stm32h723xx.h.

◆ RXESC

__IO uint32_t FDCAN_GlobalTypeDef::RXESC

FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC.

Definition at line 353 of file stm32h723xx.h.

◆ RXF0A

__IO uint32_t FDCAN_GlobalTypeDef::RXF0A

FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8.

Definition at line 348 of file stm32h723xx.h.

◆ RXF0C

__IO uint32_t FDCAN_GlobalTypeDef::RXF0C

FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0.

Definition at line 346 of file stm32h723xx.h.

◆ RXF0S

__IO uint32_t FDCAN_GlobalTypeDef::RXF0S

FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4.

Definition at line 347 of file stm32h723xx.h.

◆ RXF1A

__IO uint32_t FDCAN_GlobalTypeDef::RXF1A

FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8.

Definition at line 352 of file stm32h723xx.h.

◆ RXF1C

__IO uint32_t FDCAN_GlobalTypeDef::RXF1C

FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0.

Definition at line 350 of file stm32h723xx.h.

◆ RXF1S

__IO uint32_t FDCAN_GlobalTypeDef::RXF1S

FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4.

Definition at line 351 of file stm32h723xx.h.

◆ SIDFC

__IO uint32_t FDCAN_GlobalTypeDef::SIDFC

FDCAN Standard ID Filter Configuration register, Address offset: 0x084.

Definition at line 339 of file stm32h723xx.h.

◆ TDCR

__IO uint32_t FDCAN_GlobalTypeDef::TDCR

FDCAN Transmitter Delay Compensation register, Address offset: 0x048.

Definition at line 331 of file stm32h723xx.h.

◆ TEST

__IO uint32_t FDCAN_GlobalTypeDef::TEST

FDCAN Test register, Address offset: 0x010.

Definition at line 320 of file stm32h723xx.h.

◆ TOCC

__IO uint32_t FDCAN_GlobalTypeDef::TOCC

FDCAN Timeout Counter Configuration register, Address offset: 0x028.

Definition at line 326 of file stm32h723xx.h.

◆ TOCV

__IO uint32_t FDCAN_GlobalTypeDef::TOCV

FDCAN Timeout Counter Value register, Address offset: 0x02C.

Definition at line 327 of file stm32h723xx.h.

◆ TSCC

__IO uint32_t FDCAN_GlobalTypeDef::TSCC

FDCAN Timestamp Counter Configuration register, Address offset: 0x020.

Definition at line 324 of file stm32h723xx.h.

◆ TSCV

__IO uint32_t FDCAN_GlobalTypeDef::TSCV

FDCAN Timestamp Counter Value register, Address offset: 0x024.

Definition at line 325 of file stm32h723xx.h.

◆ TXBAR

__IO uint32_t FDCAN_GlobalTypeDef::TXBAR

FDCAN Tx Buffer Add Request register, Address offset: 0x0D0.

Definition at line 358 of file stm32h723xx.h.

◆ TXBC

__IO uint32_t FDCAN_GlobalTypeDef::TXBC

FDCAN Tx Buffer Configuration register, Address offset: 0x0C0.

Definition at line 354 of file stm32h723xx.h.

◆ TXBCF

__IO uint32_t FDCAN_GlobalTypeDef::TXBCF

FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC.

Definition at line 361 of file stm32h723xx.h.

◆ TXBCIE

__IO uint32_t FDCAN_GlobalTypeDef::TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4.

Definition at line 363 of file stm32h723xx.h.

◆ TXBCR

__IO uint32_t FDCAN_GlobalTypeDef::TXBCR

FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4.

Definition at line 359 of file stm32h723xx.h.

◆ TXBRP

__IO uint32_t FDCAN_GlobalTypeDef::TXBRP

FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC.

Definition at line 357 of file stm32h723xx.h.

◆ TXBTIE

__IO uint32_t FDCAN_GlobalTypeDef::TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0.

Definition at line 362 of file stm32h723xx.h.

◆ TXBTO

__IO uint32_t FDCAN_GlobalTypeDef::TXBTO

FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8.

Definition at line 360 of file stm32h723xx.h.

◆ TXEFA

__IO uint32_t FDCAN_GlobalTypeDef::TXEFA

FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8.

Definition at line 367 of file stm32h723xx.h.

◆ TXEFC

__IO uint32_t FDCAN_GlobalTypeDef::TXEFC

FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0.

Definition at line 365 of file stm32h723xx.h.

◆ TXEFS

__IO uint32_t FDCAN_GlobalTypeDef::TXEFS

FDCAN Tx Event FIFO Status register, Address offset: 0x0F4.

Definition at line 366 of file stm32h723xx.h.

◆ TXESC

__IO uint32_t FDCAN_GlobalTypeDef::TXESC

FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8.

Definition at line 356 of file stm32h723xx.h.

◆ TXFQS

__IO uint32_t FDCAN_GlobalTypeDef::TXFQS

FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4.

Definition at line 355 of file stm32h723xx.h.

◆ XIDAM

__IO uint32_t FDCAN_GlobalTypeDef::XIDAM

FDCAN Extended ID AND Mask register, Address offset: 0x090.

Definition at line 342 of file stm32h723xx.h.

◆ XIDFC

__IO uint32_t FDCAN_GlobalTypeDef::XIDFC

FDCAN Extended ID Filter Configuration register, Address offset: 0x088.

Definition at line 340 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:
  • firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h