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FLASH_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx » Peripheral_registers_structures

FLASH Registers. More...

#include <stm32h723xx.h>

Public Attributes

__IO uint32_t ACR
 FLASH access control register, Address offset: 0x00.
__IO uint32_t KEYR1
 Flash Key Register for bank1, Address offset: 0x04.
__IO uint32_t OPTKEYR
 Flash Option Key Register, Address offset: 0x08.
__IO uint32_t CR1
 Flash Control Register for bank1, Address offset: 0x0C.
__IO uint32_t SR1
 Flash Status Register for bank1, Address offset: 0x10.
__IO uint32_t CCR1
 Flash Control Register for bank1, Address offset: 0x14.
__IO uint32_t OPTCR
 Flash Option Control Register, Address offset: 0x18.
__IO uint32_t OPTSR_CUR
 Flash Option Status Current Register, Address offset: 0x1C.
__IO uint32_t OPTSR_PRG
 Flash Option Status to Program Register, Address offset: 0x20.
__IO uint32_t OPTCCR
 Flash Option Clear Control Register, Address offset: 0x24.
__IO uint32_t PRAR_CUR1
 Flash Current Protection Address Register for bank1, Address offset: 0x28.
__IO uint32_t PRAR_PRG1
 Flash Protection Address to Program Register for bank1, Address offset: 0x2C.
__IO uint32_t SCAR_CUR1
 Flash Current Secure Address Register for bank1, Address offset: 0x30.
__IO uint32_t SCAR_PRG1
 Flash Secure Address to Program Register for bank1, Address offset: 0x34.
__IO uint32_t WPSN_CUR1
 Flash Current Write Protection Register on bank1, Address offset: 0x38.
__IO uint32_t WPSN_PRG1
 Flash Write Protection to Program Register on bank1, Address offset: 0x3C.
__IO uint32_t BOOT_CUR
 Flash Current Boot Address for Pelican Core Register, Address offset: 0x40.
__IO uint32_t BOOT_PRG
 Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44.
uint32_t RESERVED0 [2]
 Reserved, 0x48 to 0x4C.
__IO uint32_t CRCCR1
 Flash CRC Control register For Bank1 Register , Address offset: 0x50.
__IO uint32_t CRCSADD1
 Flash CRC Start Address Register for Bank1 , Address offset: 0x54.
__IO uint32_t CRCEADD1
 Flash CRC End Address Register for Bank1 , Address offset: 0x58.
__IO uint32_t CRCDATA
 Flash CRC Data Register for Bank1 , Address offset: 0x5C.
__IO uint32_t ECC_FA1
 Flash ECC Fail Address For Bank1 Register , Address offset: 0x60.
uint32_t RESERVED [3]
 Reserved, 0x64 to 0x6C.
__IO uint32_t OPTSR2_CUR
 Flash Option Status Current Register 2, Address offset: 0x70.
__IO uint32_t OPTSR2_PRG
 Flash Option Status to Program Register 2, Address offset: 0x74.

Detailed Description

FLASH Registers.

Definition at line 955 of file stm32h723xx.h.

Member Data Documentation

◆ ACR

__IO uint32_t FLASH_TypeDef::ACR

FLASH access control register, Address offset: 0x00.

Definition at line 957 of file stm32h723xx.h.

◆ BOOT_CUR

__IO uint32_t FLASH_TypeDef::BOOT_CUR

Flash Current Boot Address for Pelican Core Register, Address offset: 0x40.

Definition at line 973 of file stm32h723xx.h.

◆ BOOT_PRG

__IO uint32_t FLASH_TypeDef::BOOT_PRG

Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44.

Definition at line 974 of file stm32h723xx.h.

◆ CCR1

__IO uint32_t FLASH_TypeDef::CCR1

Flash Control Register for bank1, Address offset: 0x14.

Definition at line 962 of file stm32h723xx.h.

◆ CR1

__IO uint32_t FLASH_TypeDef::CR1

Flash Control Register for bank1, Address offset: 0x0C.

Definition at line 960 of file stm32h723xx.h.

◆ CRCCR1

__IO uint32_t FLASH_TypeDef::CRCCR1

Flash CRC Control register For Bank1 Register , Address offset: 0x50.

Definition at line 976 of file stm32h723xx.h.

◆ CRCDATA

__IO uint32_t FLASH_TypeDef::CRCDATA

Flash CRC Data Register for Bank1 , Address offset: 0x5C.

Definition at line 979 of file stm32h723xx.h.

◆ CRCEADD1

__IO uint32_t FLASH_TypeDef::CRCEADD1

Flash CRC End Address Register for Bank1 , Address offset: 0x58.

Definition at line 978 of file stm32h723xx.h.

◆ CRCSADD1

__IO uint32_t FLASH_TypeDef::CRCSADD1

Flash CRC Start Address Register for Bank1 , Address offset: 0x54.

Definition at line 977 of file stm32h723xx.h.

◆ ECC_FA1

__IO uint32_t FLASH_TypeDef::ECC_FA1

Flash ECC Fail Address For Bank1 Register , Address offset: 0x60.

Definition at line 980 of file stm32h723xx.h.

◆ KEYR1

__IO uint32_t FLASH_TypeDef::KEYR1

Flash Key Register for bank1, Address offset: 0x04.

Definition at line 958 of file stm32h723xx.h.

◆ OPTCCR

__IO uint32_t FLASH_TypeDef::OPTCCR

Flash Option Clear Control Register, Address offset: 0x24.

Definition at line 966 of file stm32h723xx.h.

◆ OPTCR

__IO uint32_t FLASH_TypeDef::OPTCR

Flash Option Control Register, Address offset: 0x18.

Definition at line 963 of file stm32h723xx.h.

◆ OPTKEYR

__IO uint32_t FLASH_TypeDef::OPTKEYR

Flash Option Key Register, Address offset: 0x08.

Definition at line 959 of file stm32h723xx.h.

◆ OPTSR2_CUR

__IO uint32_t FLASH_TypeDef::OPTSR2_CUR

Flash Option Status Current Register 2, Address offset: 0x70.

Definition at line 982 of file stm32h723xx.h.

◆ OPTSR2_PRG

__IO uint32_t FLASH_TypeDef::OPTSR2_PRG

Flash Option Status to Program Register 2, Address offset: 0x74.

Definition at line 983 of file stm32h723xx.h.

◆ OPTSR_CUR

__IO uint32_t FLASH_TypeDef::OPTSR_CUR

Flash Option Status Current Register, Address offset: 0x1C.

Definition at line 964 of file stm32h723xx.h.

◆ OPTSR_PRG

__IO uint32_t FLASH_TypeDef::OPTSR_PRG

Flash Option Status to Program Register, Address offset: 0x20.

Definition at line 965 of file stm32h723xx.h.

◆ PRAR_CUR1

__IO uint32_t FLASH_TypeDef::PRAR_CUR1

Flash Current Protection Address Register for bank1, Address offset: 0x28.

Definition at line 967 of file stm32h723xx.h.

◆ PRAR_PRG1

__IO uint32_t FLASH_TypeDef::PRAR_PRG1

Flash Protection Address to Program Register for bank1, Address offset: 0x2C.

Definition at line 968 of file stm32h723xx.h.

◆ RESERVED

uint32_t FLASH_TypeDef::RESERVED[3]

Reserved, 0x64 to 0x6C.

Definition at line 981 of file stm32h723xx.h.

◆ RESERVED0

uint32_t FLASH_TypeDef::RESERVED0[2]

Reserved, 0x48 to 0x4C.

Definition at line 975 of file stm32h723xx.h.

◆ SCAR_CUR1

__IO uint32_t FLASH_TypeDef::SCAR_CUR1

Flash Current Secure Address Register for bank1, Address offset: 0x30.

Definition at line 969 of file stm32h723xx.h.

◆ SCAR_PRG1

__IO uint32_t FLASH_TypeDef::SCAR_PRG1

Flash Secure Address to Program Register for bank1, Address offset: 0x34.

Definition at line 970 of file stm32h723xx.h.

◆ SR1

__IO uint32_t FLASH_TypeDef::SR1

Flash Status Register for bank1, Address offset: 0x10.

Definition at line 961 of file stm32h723xx.h.

◆ WPSN_CUR1

__IO uint32_t FLASH_TypeDef::WPSN_CUR1

Flash Current Write Protection Register on bank1, Address offset: 0x38.

Definition at line 971 of file stm32h723xx.h.

◆ WPSN_PRG1

__IO uint32_t FLASH_TypeDef::WPSN_PRG1

Flash Write Protection to Program Register on bank1, Address offset: 0x3C.

Definition at line 972 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:
  • firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h