FMC_Bank2_TypeDef Struct Reference

Flexible Memory Controller Bank2. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	PCR2
	NAND Flash control register 2, Address offset: 0x60.
__IO uint32_t	SR2
	NAND Flash FIFO status and interrupt register 2, Address offset: 0x64.
__IO uint32_t	PMEM2
	NAND Flash Common memory space timing register 2, Address offset: 0x68.
__IO uint32_t	PATT2
	NAND Flash Attribute memory space timing register 2, Address offset: 0x6C.
uint32_t	RESERVED0
	Reserved, 0x70.
__IO uint32_t	ECCR2
	NAND Flash ECC result registers 2, Address offset: 0x74.

Detailed Description

Flexible Memory Controller Bank2.

Definition at line 1023 of file stm32h723xx.h.

Member Data Documentation

ECCR2

__IO uint32_t FMC_Bank2_TypeDef::ECCR2

NAND Flash ECC result registers 2, Address offset: 0x74.

Definition at line 1030 of file stm32h723xx.h.

PATT2

__IO uint32_t FMC_Bank2_TypeDef::PATT2

NAND Flash Attribute memory space timing register 2, Address offset: 0x6C.

Definition at line 1028 of file stm32h723xx.h.

PCR2

__IO uint32_t FMC_Bank2_TypeDef::PCR2

NAND Flash control register 2, Address offset: 0x60.

Definition at line 1025 of file stm32h723xx.h.

PMEM2

__IO uint32_t FMC_Bank2_TypeDef::PMEM2

NAND Flash Common memory space timing register 2, Address offset: 0x68.

Definition at line 1027 of file stm32h723xx.h.

RESERVED0

uint32_t FMC_Bank2_TypeDef::RESERVED0

Reserved, 0x70.

Definition at line 1029 of file stm32h723xx.h.

SR2

__IO uint32_t FMC_Bank2_TypeDef::SR2

NAND Flash FIFO status and interrupt register 2, Address offset: 0x64.

Definition at line 1026 of file stm32h723xx.h.

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The documentation for this struct was generated from the following file:

• firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h