FMC_Bank3_TypeDef Struct Reference

Flexible Memory Controller Bank3. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	PCR
	NAND Flash control register 3, Address offset: 0x80.
__IO uint32_t	SR
	NAND Flash FIFO status and interrupt register 3, Address offset: 0x84.
__IO uint32_t	PMEM
	NAND Flash Common memory space timing register 3, Address offset: 0x88.
__IO uint32_t	PATT
	NAND Flash Attribute memory space timing register 3, Address offset: 0x8C.
uint32_t	RESERVED
	Reserved, 0x90.
__IO uint32_t	ECCR
	NAND Flash ECC result registers 3, Address offset: 0x94.

Detailed Description

Flexible Memory Controller Bank3.

Definition at line 1037 of file stm32h723xx.h.

Member Data Documentation

ECCR

__IO uint32_t FMC_Bank3_TypeDef::ECCR

NAND Flash ECC result registers 3, Address offset: 0x94.

Definition at line 1044 of file stm32h723xx.h.

PATT

__IO uint32_t FMC_Bank3_TypeDef::PATT

NAND Flash Attribute memory space timing register 3, Address offset: 0x8C.

Definition at line 1042 of file stm32h723xx.h.

PCR

__IO uint32_t FMC_Bank3_TypeDef::PCR

NAND Flash control register 3, Address offset: 0x80.

Definition at line 1039 of file stm32h723xx.h.

PMEM

__IO uint32_t FMC_Bank3_TypeDef::PMEM

NAND Flash Common memory space timing register 3, Address offset: 0x88.

Definition at line 1041 of file stm32h723xx.h.

RESERVED

uint32_t FMC_Bank3_TypeDef::RESERVED

Reserved, 0x90.

Definition at line 1043 of file stm32h723xx.h.

SR

__IO uint32_t FMC_Bank3_TypeDef::SR

NAND Flash FIFO status and interrupt register 3, Address offset: 0x84.

Definition at line 1040 of file stm32h723xx.h.

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The documentation for this struct was generated from the following file:

• firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h