FMC_Bank5_6_TypeDef Struct Reference

Flexible Memory Controller Bank5 and 6. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	SDCR [2]
	SDRAM Control registers , Address offset: 0x140-0x144.
__IO uint32_t	SDTR [2]
	SDRAM Timing registers , Address offset: 0x148-0x14C.
__IO uint32_t	SDCMR
	SDRAM Command Mode register, Address offset: 0x150.
__IO uint32_t	SDRTR
	SDRAM Refresh Timer register, Address offset: 0x154.
__IO uint32_t	SDSR
	SDRAM Status register, Address offset: 0x158.

Detailed Description

Flexible Memory Controller Bank5 and 6.

Definition at line 1052 of file stm32h723xx.h.

Member Data Documentation

SDCMR

__IO uint32_t FMC_Bank5_6_TypeDef::SDCMR

SDRAM Command Mode register, Address offset: 0x150.

Definition at line 1056 of file stm32h723xx.h.

SDCR

__IO uint32_t FMC_Bank5_6_TypeDef::SDCR[2]

SDRAM Control registers , Address offset: 0x140-0x144.

Definition at line 1054 of file stm32h723xx.h.

SDRTR

__IO uint32_t FMC_Bank5_6_TypeDef::SDRTR

SDRAM Refresh Timer register, Address offset: 0x154.

Definition at line 1057 of file stm32h723xx.h.

SDSR

__IO uint32_t FMC_Bank5_6_TypeDef::SDSR

SDRAM Status register, Address offset: 0x158.

Definition at line 1058 of file stm32h723xx.h.

SDTR

__IO uint32_t FMC_Bank5_6_TypeDef::SDTR[2]

SDRAM Timing registers , Address offset: 0x148-0x14C.

Definition at line 1055 of file stm32h723xx.h.

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The documentation for this struct was generated from the following file:

• firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h