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#include <stm32h723xx.h>

Public Attributes
uint32_t	RESERVED0 [2036]
	Reserved, Address offset: 0x00-0x1FCC.
__IO uint32_t	AXI_PERIPH_ID_4
	AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0.
uint32_t	AXI_PERIPH_ID_5
	Reserved, Address offset: 0x1FD4.
uint32_t	AXI_PERIPH_ID_6
	Reserved, Address offset: 0x1FD8.
uint32_t	AXI_PERIPH_ID_7
	Reserved, Address offset: 0x1FDC.
__IO uint32_t	AXI_PERIPH_ID_0
	AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0.
__IO uint32_t	AXI_PERIPH_ID_1
	AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4.
__IO uint32_t	AXI_PERIPH_ID_2
	AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8.
__IO uint32_t	AXI_PERIPH_ID_3
	AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC.
__IO uint32_t	AXI_COMP_ID_0
	AXI interconnect - component ID0 register, Address offset: 0x1FF0.
__IO uint32_t	AXI_COMP_ID_1
	AXI interconnect - component ID1 register, Address offset: 0x1FF4.
__IO uint32_t	AXI_COMP_ID_2
	AXI interconnect - component ID2 register, Address offset: 0x1FF8.
__IO uint32_t	AXI_COMP_ID_3
	AXI interconnect - component ID3 register, Address offset: 0x1FFC.
uint32_t	RESERVED1 [2]
	Reserved, Address offset: 0x2000-0x2004.
__IO uint32_t	AXI_TARG1_FN_MOD_ISS_BM
	AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008.
uint32_t	RESERVED2 [6]
	Reserved, Address offset: 0x200C-0x2020.
__IO uint32_t	AXI_TARG1_FN_MOD2
	AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024.
uint32_t	RESERVED3
	Reserved, Address offset: 0x2028.
__IO uint32_t	AXI_TARG1_FN_MOD_LB
	AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C.
uint32_t	RESERVED4 [54]
	Reserved, Address offset: 0x2030-0x2104.
__IO uint32_t	AXI_TARG1_FN_MOD
	AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108.
uint32_t	RESERVED5 [959]
	Reserved, Address offset: 0x210C-0x3004.
__IO uint32_t	AXI_TARG2_FN_MOD_ISS_BM
	AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008.
uint32_t	RESERVED6 [6]
	Reserved, Address offset: 0x300C-0x3020.
__IO uint32_t	AXI_TARG2_FN_MOD2
	AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024.
uint32_t	RESERVED7
	Reserved, Address offset: 0x3028.
__IO uint32_t	AXI_TARG2_FN_MOD_LB
	AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C.
uint32_t	RESERVED8 [54]
	Reserved, Address offset: 0x3030-0x3104.
__IO uint32_t	AXI_TARG2_FN_MOD
	AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108.
uint32_t	RESERVED9 [959]
	Reserved, Address offset: 0x310C-0x4004.
__IO uint32_t	AXI_TARG3_FN_MOD_ISS_BM
	AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008.
uint32_t	RESERVED10 [1023]
	Reserved, Address offset: 0x400C-0x5004.
__IO uint32_t	AXI_TARG4_FN_MOD_ISS_BM
	AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008.
uint32_t	RESERVED11 [1023]
	Reserved, Address offset: 0x500C-0x6004.
__IO uint32_t	AXI_TARG5_FN_MOD_ISS_BM
	AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008.
uint32_t	RESERVED12 [1023]
	Reserved, Address offset: 0x600C-0x7004.
__IO uint32_t	AXI_TARG6_FN_MOD_ISS_BM
	AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008.
uint32_t	RESERVED13 [1023]
	Reserved, Address offset: 0x700C-0x8004.
__IO uint32_t	AXI_TARG7_FN_MOD_ISS_BM
	AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008.
uint32_t	RESERVED14 [6]
	Reserved, Address offset: 0x800C-0x8020.
__IO uint32_t	AXI_TARG7_FN_MOD2
	AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024.
uint32_t	RESERVED15
	Reserved, Address offset: 0x8028.
__IO uint32_t	AXI_TARG7_FN_MOD_LB
	AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C.
uint32_t	RESERVED16 [54]
	Reserved, Address offset: 0x8030-0x8104.
__IO uint32_t	AXI_TARG7_FN_MOD
	AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108.
uint32_t	RESERVED17 [959]
	Reserved, Address offset: 0x810C-0x9004.
__IO uint32_t	AXI_TARG8_FN_MOD_ISS_BM
	AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008.
uint32_t	RESERVED117 [6]
	Reserved, Address offset: 0x900C-0x9020.
__IO uint32_t	AXI_TARG8_FN_MOD2
	AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024.
uint32_t	RESERVED118 [56]
	Reserved, Address offset: 0x9028-0x9104.
__IO uint32_t	AXI_TARG8_FN_MOD
	AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108.
uint32_t	RESERVED119 [58310]
	Reserved, Address offset: 0x910C-0x42020.
__IO uint32_t	AXI_INI1_FN_MOD2
	AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024.
__IO uint32_t	AXI_INI1_FN_MOD_AHB
	AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028.
uint32_t	RESERVED18 [53]
	Reserved, Address offset: 0x4202C-0x420FC.
__IO uint32_t	AXI_INI1_READ_QOS
	AXI interconnect - INI 1 read QoS register, Address offset: 0x42100.
__IO uint32_t	AXI_INI1_WRITE_QOS
	AXI interconnect - INI 1 write QoS register, Address offset: 0x42104.
__IO uint32_t	AXI_INI1_FN_MOD
	AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108.
uint32_t	RESERVED19 [1021]
	Reserved, Address offset: 0x4210C-0x430FC.
__IO uint32_t	AXI_INI2_READ_QOS
	AXI interconnect - INI 2 read QoS register, Address offset: 0x43100.
__IO uint32_t	AXI_INI2_WRITE_QOS
	AXI interconnect - INI 2 write QoS register, Address offset: 0x43104.
__IO uint32_t	AXI_INI2_FN_MOD
	AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108.
uint32_t	RESERVED20 [966]
	Reserved, Address offset: 0x4310C-0x44020.
__IO uint32_t	AXI_INI3_FN_MOD2
	AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024.
__IO uint32_t	AXI_INI3_FN_MOD_AHB
	AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028.
uint32_t	RESERVED21 [53]
	Reserved, Address offset: 0x4402C-0x440FC.
__IO uint32_t	AXI_INI3_READ_QOS
	AXI interconnect - INI 3 read QoS register, Address offset: 0x44100.
__IO uint32_t	AXI_INI3_WRITE_QOS
	AXI interconnect - INI 3 write QoS register, Address offset: 0x44104.
__IO uint32_t	AXI_INI3_FN_MOD
	AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108.
uint32_t	RESERVED22 [1021]
	Reserved, Address offset: 0x4410C-0x450FC.
__IO uint32_t	AXI_INI4_READ_QOS
	AXI interconnect - INI 4 read QoS register, Address offset: 0x45100.
__IO uint32_t	AXI_INI4_WRITE_QOS
	AXI interconnect - INI 4 write QoS register, Address offset: 0x45104.
__IO uint32_t	AXI_INI4_FN_MOD
	AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108.
uint32_t	RESERVED23 [1021]
	Reserved, Address offset: 0x4510C-0x460FC.
__IO uint32_t	AXI_INI5_READ_QOS
	AXI interconnect - INI 5 read QoS register, Address offset: 0x46100.
__IO uint32_t	AXI_INI5_WRITE_QOS
	AXI interconnect - INI 5 write QoS register, Address offset: 0x46104.
__IO uint32_t	AXI_INI5_FN_MOD
	AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108.
uint32_t	RESERVED24 [1021]
	Reserved, Address offset: 0x4610C-0x470FC.
__IO uint32_t	AXI_INI6_READ_QOS
	AXI interconnect - INI 6 read QoS register, Address offset: 0x47100.
__IO uint32_t	AXI_INI6_WRITE_QOS
	AXI interconnect - INI 6 write QoS register, Address offset: 0x47104.
__IO uint32_t	AXI_INI6_FN_MOD
	AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108.

Detailed Description

Global Programmer View.

Definition at line 1965 of file stm32h723xx.h.

Member Data Documentation

◆ AXI_COMP_ID_0

__IO uint32_t GPV_TypeDef::AXI_COMP_ID_0

AXI interconnect - component ID0 register, Address offset: 0x1FF0.

Definition at line 1976 of file stm32h723xx.h.

◆ AXI_COMP_ID_1

__IO uint32_t GPV_TypeDef::AXI_COMP_ID_1

AXI interconnect - component ID1 register, Address offset: 0x1FF4.

Definition at line 1977 of file stm32h723xx.h.

◆ AXI_COMP_ID_2

__IO uint32_t GPV_TypeDef::AXI_COMP_ID_2

AXI interconnect - component ID2 register, Address offset: 0x1FF8.

Definition at line 1978 of file stm32h723xx.h.

◆ AXI_COMP_ID_3

__IO uint32_t GPV_TypeDef::AXI_COMP_ID_3

AXI interconnect - component ID3 register, Address offset: 0x1FFC.

Definition at line 1979 of file stm32h723xx.h.

◆ AXI_INI1_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_INI1_FN_MOD

AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108.

Definition at line 2024 of file stm32h723xx.h.

◆ AXI_INI1_FN_MOD2

__IO uint32_t GPV_TypeDef::AXI_INI1_FN_MOD2

AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024.

Definition at line 2019 of file stm32h723xx.h.

◆ AXI_INI1_FN_MOD_AHB

__IO uint32_t GPV_TypeDef::AXI_INI1_FN_MOD_AHB

AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028.

Definition at line 2020 of file stm32h723xx.h.

◆ AXI_INI1_READ_QOS

__IO uint32_t GPV_TypeDef::AXI_INI1_READ_QOS

AXI interconnect - INI 1 read QoS register, Address offset: 0x42100.

Definition at line 2022 of file stm32h723xx.h.

◆ AXI_INI1_WRITE_QOS

__IO uint32_t GPV_TypeDef::AXI_INI1_WRITE_QOS

AXI interconnect - INI 1 write QoS register, Address offset: 0x42104.

Definition at line 2023 of file stm32h723xx.h.

◆ AXI_INI2_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_INI2_FN_MOD

AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108.

Definition at line 2028 of file stm32h723xx.h.

◆ AXI_INI2_READ_QOS

__IO uint32_t GPV_TypeDef::AXI_INI2_READ_QOS

AXI interconnect - INI 2 read QoS register, Address offset: 0x43100.

Definition at line 2026 of file stm32h723xx.h.

◆ AXI_INI2_WRITE_QOS

__IO uint32_t GPV_TypeDef::AXI_INI2_WRITE_QOS

AXI interconnect - INI 2 write QoS register, Address offset: 0x43104.

Definition at line 2027 of file stm32h723xx.h.

◆ AXI_INI3_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_INI3_FN_MOD

AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108.

Definition at line 2035 of file stm32h723xx.h.

◆ AXI_INI3_FN_MOD2

__IO uint32_t GPV_TypeDef::AXI_INI3_FN_MOD2

AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024.

Definition at line 2030 of file stm32h723xx.h.

◆ AXI_INI3_FN_MOD_AHB

__IO uint32_t GPV_TypeDef::AXI_INI3_FN_MOD_AHB

AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028.

Definition at line 2031 of file stm32h723xx.h.

◆ AXI_INI3_READ_QOS

__IO uint32_t GPV_TypeDef::AXI_INI3_READ_QOS

AXI interconnect - INI 3 read QoS register, Address offset: 0x44100.

Definition at line 2033 of file stm32h723xx.h.

◆ AXI_INI3_WRITE_QOS

__IO uint32_t GPV_TypeDef::AXI_INI3_WRITE_QOS

AXI interconnect - INI 3 write QoS register, Address offset: 0x44104.

Definition at line 2034 of file stm32h723xx.h.

◆ AXI_INI4_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_INI4_FN_MOD

AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108.

Definition at line 2039 of file stm32h723xx.h.

◆ AXI_INI4_READ_QOS

__IO uint32_t GPV_TypeDef::AXI_INI4_READ_QOS

AXI interconnect - INI 4 read QoS register, Address offset: 0x45100.

Definition at line 2037 of file stm32h723xx.h.

◆ AXI_INI4_WRITE_QOS

__IO uint32_t GPV_TypeDef::AXI_INI4_WRITE_QOS

AXI interconnect - INI 4 write QoS register, Address offset: 0x45104.

Definition at line 2038 of file stm32h723xx.h.

◆ AXI_INI5_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_INI5_FN_MOD

AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108.

Definition at line 2043 of file stm32h723xx.h.

◆ AXI_INI5_READ_QOS

__IO uint32_t GPV_TypeDef::AXI_INI5_READ_QOS

AXI interconnect - INI 5 read QoS register, Address offset: 0x46100.

Definition at line 2041 of file stm32h723xx.h.

◆ AXI_INI5_WRITE_QOS

__IO uint32_t GPV_TypeDef::AXI_INI5_WRITE_QOS

AXI interconnect - INI 5 write QoS register, Address offset: 0x46104.

Definition at line 2042 of file stm32h723xx.h.

◆ AXI_INI6_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_INI6_FN_MOD

AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108.

Definition at line 2047 of file stm32h723xx.h.

◆ AXI_INI6_READ_QOS

__IO uint32_t GPV_TypeDef::AXI_INI6_READ_QOS

AXI interconnect - INI 6 read QoS register, Address offset: 0x47100.

Definition at line 2045 of file stm32h723xx.h.

◆ AXI_INI6_WRITE_QOS

__IO uint32_t GPV_TypeDef::AXI_INI6_WRITE_QOS

AXI interconnect - INI 6 write QoS register, Address offset: 0x47104.

Definition at line 2046 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_0

__IO uint32_t GPV_TypeDef::AXI_PERIPH_ID_0

AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0.

Definition at line 1972 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_1

__IO uint32_t GPV_TypeDef::AXI_PERIPH_ID_1

AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4.

Definition at line 1973 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_2

__IO uint32_t GPV_TypeDef::AXI_PERIPH_ID_2

AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8.

Definition at line 1974 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_3

__IO uint32_t GPV_TypeDef::AXI_PERIPH_ID_3

AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC.

Definition at line 1975 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_4

__IO uint32_t GPV_TypeDef::AXI_PERIPH_ID_4

AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0.

Definition at line 1968 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_5

uint32_t GPV_TypeDef::AXI_PERIPH_ID_5

Reserved, Address offset: 0x1FD4.

Definition at line 1969 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_6

uint32_t GPV_TypeDef::AXI_PERIPH_ID_6

Reserved, Address offset: 0x1FD8.

Definition at line 1970 of file stm32h723xx.h.

◆ AXI_PERIPH_ID_7

uint32_t GPV_TypeDef::AXI_PERIPH_ID_7

Reserved, Address offset: 0x1FDC.

Definition at line 1971 of file stm32h723xx.h.

◆ AXI_TARG1_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_TARG1_FN_MOD

AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108.

Definition at line 1987 of file stm32h723xx.h.

◆ AXI_TARG1_FN_MOD2

__IO uint32_t GPV_TypeDef::AXI_TARG1_FN_MOD2

AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024.

Definition at line 1983 of file stm32h723xx.h.

◆ AXI_TARG1_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG1_FN_MOD_ISS_BM

AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008.

Definition at line 1981 of file stm32h723xx.h.

◆ AXI_TARG1_FN_MOD_LB

__IO uint32_t GPV_TypeDef::AXI_TARG1_FN_MOD_LB

AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C.

Definition at line 1985 of file stm32h723xx.h.

◆ AXI_TARG2_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_TARG2_FN_MOD

AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108.

Definition at line 1995 of file stm32h723xx.h.

◆ AXI_TARG2_FN_MOD2

__IO uint32_t GPV_TypeDef::AXI_TARG2_FN_MOD2

AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024.

Definition at line 1991 of file stm32h723xx.h.

◆ AXI_TARG2_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG2_FN_MOD_ISS_BM

AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008.

Definition at line 1989 of file stm32h723xx.h.

◆ AXI_TARG2_FN_MOD_LB

__IO uint32_t GPV_TypeDef::AXI_TARG2_FN_MOD_LB

AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C.

Definition at line 1993 of file stm32h723xx.h.

◆ AXI_TARG3_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG3_FN_MOD_ISS_BM

AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008.

Definition at line 1997 of file stm32h723xx.h.

◆ AXI_TARG4_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG4_FN_MOD_ISS_BM

AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008.

Definition at line 1999 of file stm32h723xx.h.

◆ AXI_TARG5_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG5_FN_MOD_ISS_BM

AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008.

Definition at line 2001 of file stm32h723xx.h.

◆ AXI_TARG6_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG6_FN_MOD_ISS_BM

AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008.

Definition at line 2003 of file stm32h723xx.h.

◆ AXI_TARG7_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_TARG7_FN_MOD

AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108.

Definition at line 2011 of file stm32h723xx.h.

◆ AXI_TARG7_FN_MOD2

__IO uint32_t GPV_TypeDef::AXI_TARG7_FN_MOD2

AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024.

Definition at line 2007 of file stm32h723xx.h.

◆ AXI_TARG7_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG7_FN_MOD_ISS_BM

AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008.

Definition at line 2005 of file stm32h723xx.h.

◆ AXI_TARG7_FN_MOD_LB

__IO uint32_t GPV_TypeDef::AXI_TARG7_FN_MOD_LB

AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C.

Definition at line 2009 of file stm32h723xx.h.

◆ AXI_TARG8_FN_MOD

__IO uint32_t GPV_TypeDef::AXI_TARG8_FN_MOD

AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108.

Definition at line 2017 of file stm32h723xx.h.

◆ AXI_TARG8_FN_MOD2

__IO uint32_t GPV_TypeDef::AXI_TARG8_FN_MOD2

AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024.

Definition at line 2015 of file stm32h723xx.h.

◆ AXI_TARG8_FN_MOD_ISS_BM

__IO uint32_t GPV_TypeDef::AXI_TARG8_FN_MOD_ISS_BM

AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008.

Definition at line 2013 of file stm32h723xx.h.

◆ RESERVED0

uint32_t GPV_TypeDef::RESERVED0[2036]

Reserved, Address offset: 0x00-0x1FCC.

Definition at line 1967 of file stm32h723xx.h.

◆ RESERVED1

uint32_t GPV_TypeDef::RESERVED1[2]

Reserved, Address offset: 0x2000-0x2004.

Definition at line 1980 of file stm32h723xx.h.

◆ RESERVED10

uint32_t GPV_TypeDef::RESERVED10[1023]

Reserved, Address offset: 0x400C-0x5004.

Definition at line 1998 of file stm32h723xx.h.

◆ RESERVED11

uint32_t GPV_TypeDef::RESERVED11[1023]

Reserved, Address offset: 0x500C-0x6004.

Definition at line 2000 of file stm32h723xx.h.

◆ RESERVED117

uint32_t GPV_TypeDef::RESERVED117[6]

Reserved, Address offset: 0x900C-0x9020.

Definition at line 2014 of file stm32h723xx.h.

◆ RESERVED118

uint32_t GPV_TypeDef::RESERVED118[56]

Reserved, Address offset: 0x9028-0x9104.

Definition at line 2016 of file stm32h723xx.h.

◆ RESERVED119

uint32_t GPV_TypeDef::RESERVED119[58310]

Reserved, Address offset: 0x910C-0x42020.

Definition at line 2018 of file stm32h723xx.h.

◆ RESERVED12

uint32_t GPV_TypeDef::RESERVED12[1023]

Reserved, Address offset: 0x600C-0x7004.

Definition at line 2002 of file stm32h723xx.h.

◆ RESERVED13

uint32_t GPV_TypeDef::RESERVED13[1023]

Reserved, Address offset: 0x700C-0x8004.

Definition at line 2004 of file stm32h723xx.h.

◆ RESERVED14

uint32_t GPV_TypeDef::RESERVED14[6]

Reserved, Address offset: 0x800C-0x8020.

Definition at line 2006 of file stm32h723xx.h.

◆ RESERVED15

uint32_t GPV_TypeDef::RESERVED15

Reserved, Address offset: 0x8028.

Definition at line 2008 of file stm32h723xx.h.

◆ RESERVED16

uint32_t GPV_TypeDef::RESERVED16[54]

Reserved, Address offset: 0x8030-0x8104.

Definition at line 2010 of file stm32h723xx.h.

◆ RESERVED17

uint32_t GPV_TypeDef::RESERVED17[959]

Reserved, Address offset: 0x810C-0x9004.

Definition at line 2012 of file stm32h723xx.h.

◆ RESERVED18

uint32_t GPV_TypeDef::RESERVED18[53]

Reserved, Address offset: 0x4202C-0x420FC.

Definition at line 2021 of file stm32h723xx.h.

◆ RESERVED19

uint32_t GPV_TypeDef::RESERVED19[1021]

Reserved, Address offset: 0x4210C-0x430FC.

Definition at line 2025 of file stm32h723xx.h.

◆ RESERVED2

uint32_t GPV_TypeDef::RESERVED2[6]

Reserved, Address offset: 0x200C-0x2020.

Definition at line 1982 of file stm32h723xx.h.

◆ RESERVED20

uint32_t GPV_TypeDef::RESERVED20[966]

Reserved, Address offset: 0x4310C-0x44020.

Definition at line 2029 of file stm32h723xx.h.

◆ RESERVED21

uint32_t GPV_TypeDef::RESERVED21[53]

Reserved, Address offset: 0x4402C-0x440FC.

Definition at line 2032 of file stm32h723xx.h.

◆ RESERVED22

uint32_t GPV_TypeDef::RESERVED22[1021]

Reserved, Address offset: 0x4410C-0x450FC.

Definition at line 2036 of file stm32h723xx.h.

◆ RESERVED23

uint32_t GPV_TypeDef::RESERVED23[1021]

Reserved, Address offset: 0x4510C-0x460FC.

Definition at line 2040 of file stm32h723xx.h.

◆ RESERVED24

uint32_t GPV_TypeDef::RESERVED24[1021]

Reserved, Address offset: 0x4610C-0x470FC.

Definition at line 2044 of file stm32h723xx.h.

◆ RESERVED3

uint32_t GPV_TypeDef::RESERVED3

Reserved, Address offset: 0x2028.

Definition at line 1984 of file stm32h723xx.h.

◆ RESERVED4

uint32_t GPV_TypeDef::RESERVED4[54]

Reserved, Address offset: 0x2030-0x2104.

Definition at line 1986 of file stm32h723xx.h.

◆ RESERVED5

uint32_t GPV_TypeDef::RESERVED5[959]

Reserved, Address offset: 0x210C-0x3004.

Definition at line 1988 of file stm32h723xx.h.

◆ RESERVED6

uint32_t GPV_TypeDef::RESERVED6[6]

Reserved, Address offset: 0x300C-0x3020.

Definition at line 1990 of file stm32h723xx.h.

◆ RESERVED7

uint32_t GPV_TypeDef::RESERVED7

Reserved, Address offset: 0x3028.

Definition at line 1992 of file stm32h723xx.h.

◆ RESERVED8

uint32_t GPV_TypeDef::RESERVED8[54]

Reserved, Address offset: 0x3030-0x3104.

Definition at line 1994 of file stm32h723xx.h.

◆ RESERVED9

uint32_t GPV_TypeDef::RESERVED9[959]

Reserved, Address offset: 0x310C-0x4004.

Definition at line 1996 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes