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LPTIM_TypeDef Struct Reference

LPTIMIMER. More...

#include <stm32h723xx.h>

Public Attributes

__IO uint32_t ISR
 LPTIM Interrupt and Status register, Address offset: 0x00.
__IO uint32_t ICR
 LPTIM Interrupt Clear register, Address offset: 0x04.
__IO uint32_t IER
 LPTIM Interrupt Enable register, Address offset: 0x08.
__IO uint32_t CFGR
 LPTIM Configuration register, Address offset: 0x0C.
__IO uint32_t CR
 LPTIM Control register, Address offset: 0x10.
__IO uint32_t CMP
 LPTIM Compare register, Address offset: 0x14.
__IO uint32_t ARR
 LPTIM Autoreload register, Address offset: 0x18.
__IO uint32_t CNT
 LPTIM Counter register, Address offset: 0x1C.
uint32_t RESERVED1
 Reserved, 0x20.
__IO uint32_t CFGR2
 LPTIM Configuration register, Address offset: 0x24.

Detailed Description

LPTIMIMER.

Definition at line 1558 of file stm32h723xx.h.

Member Data Documentation

◆ ARR

__IO uint32_t LPTIM_TypeDef::ARR

LPTIM Autoreload register, Address offset: 0x18.

Definition at line 1566 of file stm32h723xx.h.

◆ CFGR

__IO uint32_t LPTIM_TypeDef::CFGR

LPTIM Configuration register, Address offset: 0x0C.

Definition at line 1563 of file stm32h723xx.h.

◆ CFGR2

__IO uint32_t LPTIM_TypeDef::CFGR2

LPTIM Configuration register, Address offset: 0x24.

Definition at line 1569 of file stm32h723xx.h.

◆ CMP

__IO uint32_t LPTIM_TypeDef::CMP

LPTIM Compare register, Address offset: 0x14.

Definition at line 1565 of file stm32h723xx.h.

◆ CNT

__IO uint32_t LPTIM_TypeDef::CNT

LPTIM Counter register, Address offset: 0x1C.

Definition at line 1567 of file stm32h723xx.h.

◆ CR

__IO uint32_t LPTIM_TypeDef::CR

LPTIM Control register, Address offset: 0x10.

Definition at line 1564 of file stm32h723xx.h.

◆ ICR

__IO uint32_t LPTIM_TypeDef::ICR

LPTIM Interrupt Clear register, Address offset: 0x04.

Definition at line 1561 of file stm32h723xx.h.

◆ IER

__IO uint32_t LPTIM_TypeDef::IER

LPTIM Interrupt Enable register, Address offset: 0x08.

Definition at line 1562 of file stm32h723xx.h.

◆ ISR

__IO uint32_t LPTIM_TypeDef::ISR

LPTIM Interrupt and Status register, Address offset: 0x00.

Definition at line 1560 of file stm32h723xx.h.

◆ RESERVED1

uint32_t LPTIM_TypeDef::RESERVED1

Reserved, 0x20.

Definition at line 1568 of file stm32h723xx.h.


The documentation for this struct was generated from the following file:
  • firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h