Power Control. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR1
	PWR power control register 1, Address offset: 0x00.
__IO uint32_t	CSR1
	PWR power control status register 1, Address offset: 0x04.
__IO uint32_t	CR2
	PWR power control register 2, Address offset: 0x08.
__IO uint32_t	CR3
	PWR power control register 3, Address offset: 0x0C.
__IO uint32_t	CPUCR
	PWR CPU control register, Address offset: 0x10.
uint32_t	RESERVED0
	Reserved, Address offset: 0x14.
__IO uint32_t	D3CR
	PWR D3 domain control register, Address offset: 0x18.
uint32_t	RESERVED1
	Reserved, Address offset: 0x1C.
__IO uint32_t	WKUPCR
	PWR wakeup clear register, Address offset: 0x20.
__IO uint32_t	WKUPFR
	PWR wakeup flag register, Address offset: 0x24.
__IO uint32_t	WKUPEPR
	PWR wakeup enable and polarity register, Address offset: 0x28.

Detailed Description

Power Control.

Definition at line 1213 of file stm32h723xx.h.

Member Data Documentation

◆ CPUCR

__IO uint32_t PWR_TypeDef::CPUCR

PWR CPU control register, Address offset: 0x10.

Definition at line 1219 of file stm32h723xx.h.

◆ CR1

__IO uint32_t PWR_TypeDef::CR1

PWR power control register 1, Address offset: 0x00.

Definition at line 1215 of file stm32h723xx.h.

◆ CR2

__IO uint32_t PWR_TypeDef::CR2

PWR power control register 2, Address offset: 0x08.

Definition at line 1217 of file stm32h723xx.h.

◆ CR3

__IO uint32_t PWR_TypeDef::CR3

PWR power control register 3, Address offset: 0x0C.

Definition at line 1218 of file stm32h723xx.h.

◆ CSR1

__IO uint32_t PWR_TypeDef::CSR1

PWR power control status register 1, Address offset: 0x04.

Definition at line 1216 of file stm32h723xx.h.

◆ D3CR

__IO uint32_t PWR_TypeDef::D3CR

PWR D3 domain control register, Address offset: 0x18.

Definition at line 1221 of file stm32h723xx.h.

◆ RESERVED0

uint32_t PWR_TypeDef::RESERVED0

Reserved, Address offset: 0x14.

Definition at line 1220 of file stm32h723xx.h.

◆ RESERVED1

uint32_t PWR_TypeDef::RESERVED1

Reserved, Address offset: 0x1C.

Definition at line 1222 of file stm32h723xx.h.

◆ WKUPCR

__IO uint32_t PWR_TypeDef::WKUPCR

PWR wakeup clear register, Address offset: 0x20.

Definition at line 1223 of file stm32h723xx.h.

◆ WKUPEPR

__IO uint32_t PWR_TypeDef::WKUPEPR

PWR wakeup enable and polarity register, Address offset: 0x28.

Definition at line 1225 of file stm32h723xx.h.

◆ WKUPFR

__IO uint32_t PWR_TypeDef::WKUPFR

PWR wakeup flag register, Address offset: 0x24.

Definition at line 1224 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes