Reset and Clock Control. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	CR
	RCC clock control register, Address offset: 0x00.
__IO uint32_t	HSICFGR
	HSI Clock Calibration Register, Address offset: 0x04.
__IO uint32_t	CRRCR
	Clock Recovery RC Register, Address offset: 0x08.
__IO uint32_t	CSICFGR
	CSI Clock Calibration Register, Address offset: 0x0C.
__IO uint32_t	CFGR
	RCC clock configuration register, Address offset: 0x10.
uint32_t	RESERVED1
	Reserved, Address offset: 0x14.
__IO uint32_t	D1CFGR
	RCC Domain 1 configuration register, Address offset: 0x18.
__IO uint32_t	D2CFGR
	RCC Domain 2 configuration register, Address offset: 0x1C.
__IO uint32_t	D3CFGR
	RCC Domain 3 configuration register, Address offset: 0x20.
uint32_t	RESERVED2
	Reserved, Address offset: 0x24.
__IO uint32_t	PLLCKSELR
	RCC PLLs Clock Source Selection Register, Address offset: 0x28.
__IO uint32_t	PLLCFGR
	RCC PLLs Configuration Register, Address offset: 0x2C.
__IO uint32_t	PLL1DIVR
	RCC PLL1 Dividers Configuration Register, Address offset: 0x30.
__IO uint32_t	PLL1FRACR
	RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34.
__IO uint32_t	PLL2DIVR
	RCC PLL2 Dividers Configuration Register, Address offset: 0x38.
__IO uint32_t	PLL2FRACR
	RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C.
__IO uint32_t	PLL3DIVR
	RCC PLL3 Dividers Configuration Register, Address offset: 0x40.
__IO uint32_t	PLL3FRACR
	RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44.
uint32_t	RESERVED3
	Reserved, Address offset: 0x48.
__IO uint32_t	D1CCIPR
	RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C.
__IO uint32_t	D2CCIP1R
	RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50.
__IO uint32_t	D2CCIP2R
	RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54.
__IO uint32_t	D3CCIPR
	RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58.
uint32_t	RESERVED4
	Reserved, Address offset: 0x5C.
__IO uint32_t	CIER
	RCC Clock Source Interrupt Enable Register Address offset: 0x60.
__IO uint32_t	CIFR
	RCC Clock Source Interrupt Flag Register Address offset: 0x64.
__IO uint32_t	CICR
	RCC Clock Source Interrupt Clear Register Address offset: 0x68.
uint32_t	RESERVED5
	Reserved, Address offset: 0x6C.
__IO uint32_t	BDCR
	RCC Vswitch Backup Domain Control Register, Address offset: 0x70.
__IO uint32_t	CSR
	RCC clock control & status register, Address offset: 0x74.
uint32_t	RESERVED6
	Reserved, Address offset: 0x78.
__IO uint32_t	AHB3RSTR
	RCC AHB3 peripheral reset register, Address offset: 0x7C.
__IO uint32_t	AHB1RSTR
	RCC AHB1 peripheral reset register, Address offset: 0x80.
__IO uint32_t	AHB2RSTR
	RCC AHB2 peripheral reset register, Address offset: 0x84.
__IO uint32_t	AHB4RSTR
	RCC AHB4 peripheral reset register, Address offset: 0x88.
__IO uint32_t	APB3RSTR
	RCC APB3 peripheral reset register, Address offset: 0x8C.
__IO uint32_t	APB1LRSTR
	RCC APB1 peripheral reset Low Word register, Address offset: 0x90.
__IO uint32_t	APB1HRSTR
	RCC APB1 peripheral reset High Word register, Address offset: 0x94.
__IO uint32_t	APB2RSTR
	RCC APB2 peripheral reset register, Address offset: 0x98.
__IO uint32_t	APB4RSTR
	RCC APB4 peripheral reset register, Address offset: 0x9C.
__IO uint32_t	GCR
	RCC RCC Global Control Register, Address offset: 0xA0.
uint32_t	RESERVED8
	Reserved, Address offset: 0xA4.
__IO uint32_t	D3AMR
	RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8.
uint32_t	RESERVED11 [9]
	Reserved, 0xAC-0xCC Address offset: 0xAC.
__IO uint32_t	RSR
	RCC Reset status register, Address offset: 0xD0.
__IO uint32_t	AHB3ENR
	RCC AHB3 peripheral clock register, Address offset: 0xD4.
__IO uint32_t	AHB1ENR
	RCC AHB1 peripheral clock register, Address offset: 0xD8.
__IO uint32_t	AHB2ENR
	RCC AHB2 peripheral clock register, Address offset: 0xDC.
__IO uint32_t	AHB4ENR
	RCC AHB4 peripheral clock register, Address offset: 0xE0.
__IO uint32_t	APB3ENR
	RCC APB3 peripheral clock register, Address offset: 0xE4.
__IO uint32_t	APB1LENR
	RCC APB1 peripheral clock Low Word register, Address offset: 0xE8.
__IO uint32_t	APB1HENR
	RCC APB1 peripheral clock High Word register, Address offset: 0xEC.
__IO uint32_t	APB2ENR
	RCC APB2 peripheral clock register, Address offset: 0xF0.
__IO uint32_t	APB4ENR
	RCC APB4 peripheral clock register, Address offset: 0xF4.
uint32_t	RESERVED12
	Reserved, Address offset: 0xF8.
__IO uint32_t	AHB3LPENR
	RCC AHB3 peripheral sleep clock register, Address offset: 0xFC.
__IO uint32_t	AHB1LPENR
	RCC AHB1 peripheral sleep clock register, Address offset: 0x100.
__IO uint32_t	AHB2LPENR
	RCC AHB2 peripheral sleep clock register, Address offset: 0x104.
__IO uint32_t	AHB4LPENR
	RCC AHB4 peripheral sleep clock register, Address offset: 0x108.
__IO uint32_t	APB3LPENR
	RCC APB3 peripheral sleep clock register, Address offset: 0x10C.
__IO uint32_t	APB1LLPENR
	RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110.
__IO uint32_t	APB1HLPENR
	RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114.
__IO uint32_t	APB2LPENR
	RCC APB2 peripheral sleep clock register, Address offset: 0x118.
__IO uint32_t	APB4LPENR
	RCC APB4 peripheral sleep clock register, Address offset: 0x11C.
uint32_t	RESERVED13 [4]
	Reserved, 0x120-0x12C Address offset: 0x120.

Detailed Description

Reset and Clock Control.

Definition at line 1232 of file stm32h723xx.h.

Member Data Documentation

◆ AHB1ENR

__IO uint32_t RCC_TypeDef::AHB1ENR

RCC AHB1 peripheral clock register, Address offset: 0xD8.

Definition at line 1280 of file stm32h723xx.h.

◆ AHB1LPENR

__IO uint32_t RCC_TypeDef::AHB1LPENR

RCC AHB1 peripheral sleep clock register, Address offset: 0x100.

Definition at line 1290 of file stm32h723xx.h.

◆ AHB1RSTR

__IO uint32_t RCC_TypeDef::AHB1RSTR

RCC AHB1 peripheral reset register, Address offset: 0x80.

Definition at line 1266 of file stm32h723xx.h.

◆ AHB2ENR

__IO uint32_t RCC_TypeDef::AHB2ENR

RCC AHB2 peripheral clock register, Address offset: 0xDC.

Definition at line 1281 of file stm32h723xx.h.

◆ AHB2LPENR

__IO uint32_t RCC_TypeDef::AHB2LPENR

RCC AHB2 peripheral sleep clock register, Address offset: 0x104.

Definition at line 1291 of file stm32h723xx.h.

◆ AHB2RSTR

__IO uint32_t RCC_TypeDef::AHB2RSTR

RCC AHB2 peripheral reset register, Address offset: 0x84.

Definition at line 1267 of file stm32h723xx.h.

◆ AHB3ENR

__IO uint32_t RCC_TypeDef::AHB3ENR

RCC AHB3 peripheral clock register, Address offset: 0xD4.

Definition at line 1279 of file stm32h723xx.h.

◆ AHB3LPENR

__IO uint32_t RCC_TypeDef::AHB3LPENR

RCC AHB3 peripheral sleep clock register, Address offset: 0xFC.

Definition at line 1289 of file stm32h723xx.h.

◆ AHB3RSTR

__IO uint32_t RCC_TypeDef::AHB3RSTR

RCC AHB3 peripheral reset register, Address offset: 0x7C.

Definition at line 1265 of file stm32h723xx.h.

◆ AHB4ENR

__IO uint32_t RCC_TypeDef::AHB4ENR

RCC AHB4 peripheral clock register, Address offset: 0xE0.

Definition at line 1282 of file stm32h723xx.h.

◆ AHB4LPENR

__IO uint32_t RCC_TypeDef::AHB4LPENR

RCC AHB4 peripheral sleep clock register, Address offset: 0x108.

Definition at line 1292 of file stm32h723xx.h.

◆ AHB4RSTR

__IO uint32_t RCC_TypeDef::AHB4RSTR

RCC AHB4 peripheral reset register, Address offset: 0x88.

Definition at line 1268 of file stm32h723xx.h.

◆ APB1HENR

__IO uint32_t RCC_TypeDef::APB1HENR

RCC APB1 peripheral clock High Word register, Address offset: 0xEC.

Definition at line 1285 of file stm32h723xx.h.

◆ APB1HLPENR

__IO uint32_t RCC_TypeDef::APB1HLPENR

RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114.

Definition at line 1295 of file stm32h723xx.h.

◆ APB1HRSTR

__IO uint32_t RCC_TypeDef::APB1HRSTR

RCC APB1 peripheral reset High Word register, Address offset: 0x94.

Definition at line 1271 of file stm32h723xx.h.

◆ APB1LENR

__IO uint32_t RCC_TypeDef::APB1LENR

RCC APB1 peripheral clock Low Word register, Address offset: 0xE8.

Definition at line 1284 of file stm32h723xx.h.

◆ APB1LLPENR

__IO uint32_t RCC_TypeDef::APB1LLPENR

RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110.

Definition at line 1294 of file stm32h723xx.h.

◆ APB1LRSTR

__IO uint32_t RCC_TypeDef::APB1LRSTR

RCC APB1 peripheral reset Low Word register, Address offset: 0x90.

Definition at line 1270 of file stm32h723xx.h.

◆ APB2ENR

__IO uint32_t RCC_TypeDef::APB2ENR

RCC APB2 peripheral clock register, Address offset: 0xF0.

Definition at line 1286 of file stm32h723xx.h.

◆ APB2LPENR

__IO uint32_t RCC_TypeDef::APB2LPENR

RCC APB2 peripheral sleep clock register, Address offset: 0x118.

Definition at line 1296 of file stm32h723xx.h.

◆ APB2RSTR

__IO uint32_t RCC_TypeDef::APB2RSTR

RCC APB2 peripheral reset register, Address offset: 0x98.

Definition at line 1272 of file stm32h723xx.h.

◆ APB3ENR

__IO uint32_t RCC_TypeDef::APB3ENR

RCC APB3 peripheral clock register, Address offset: 0xE4.

Definition at line 1283 of file stm32h723xx.h.

◆ APB3LPENR

__IO uint32_t RCC_TypeDef::APB3LPENR

RCC APB3 peripheral sleep clock register, Address offset: 0x10C.

Definition at line 1293 of file stm32h723xx.h.

◆ APB3RSTR

__IO uint32_t RCC_TypeDef::APB3RSTR

RCC APB3 peripheral reset register, Address offset: 0x8C.

Definition at line 1269 of file stm32h723xx.h.

◆ APB4ENR

__IO uint32_t RCC_TypeDef::APB4ENR

RCC APB4 peripheral clock register, Address offset: 0xF4.

Definition at line 1287 of file stm32h723xx.h.

◆ APB4LPENR

__IO uint32_t RCC_TypeDef::APB4LPENR

RCC APB4 peripheral sleep clock register, Address offset: 0x11C.

Definition at line 1297 of file stm32h723xx.h.

◆ APB4RSTR

__IO uint32_t RCC_TypeDef::APB4RSTR

RCC APB4 peripheral reset register, Address offset: 0x9C.

Definition at line 1273 of file stm32h723xx.h.

◆ BDCR

__IO uint32_t RCC_TypeDef::BDCR

RCC Vswitch Backup Domain Control Register, Address offset: 0x70.

Definition at line 1262 of file stm32h723xx.h.

◆ CFGR

__IO uint32_t RCC_TypeDef::CFGR

RCC clock configuration register, Address offset: 0x10.

Definition at line 1238 of file stm32h723xx.h.

◆ CICR

__IO uint32_t RCC_TypeDef::CICR

RCC Clock Source Interrupt Clear Register Address offset: 0x68.

Definition at line 1260 of file stm32h723xx.h.

◆ CIER

__IO uint32_t RCC_TypeDef::CIER

RCC Clock Source Interrupt Enable Register Address offset: 0x60.

Definition at line 1258 of file stm32h723xx.h.

◆ CIFR

__IO uint32_t RCC_TypeDef::CIFR

RCC Clock Source Interrupt Flag Register Address offset: 0x64.

Definition at line 1259 of file stm32h723xx.h.

◆ CR

__IO uint32_t RCC_TypeDef::CR

RCC clock control register, Address offset: 0x00.

Definition at line 1234 of file stm32h723xx.h.

◆ CRRCR

__IO uint32_t RCC_TypeDef::CRRCR

Clock Recovery RC Register, Address offset: 0x08.

Definition at line 1236 of file stm32h723xx.h.

◆ CSICFGR

__IO uint32_t RCC_TypeDef::CSICFGR

CSI Clock Calibration Register, Address offset: 0x0C.

Definition at line 1237 of file stm32h723xx.h.

◆ CSR

__IO uint32_t RCC_TypeDef::CSR

RCC clock control & status register, Address offset: 0x74.

Definition at line 1263 of file stm32h723xx.h.

◆ D1CCIPR

__IO uint32_t RCC_TypeDef::D1CCIPR

RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C.

Definition at line 1253 of file stm32h723xx.h.

◆ D1CFGR

__IO uint32_t RCC_TypeDef::D1CFGR

RCC Domain 1 configuration register, Address offset: 0x18.

Definition at line 1240 of file stm32h723xx.h.

◆ D2CCIP1R

__IO uint32_t RCC_TypeDef::D2CCIP1R

RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50.

Definition at line 1254 of file stm32h723xx.h.

◆ D2CCIP2R

__IO uint32_t RCC_TypeDef::D2CCIP2R

RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54.

Definition at line 1255 of file stm32h723xx.h.

◆ D2CFGR

__IO uint32_t RCC_TypeDef::D2CFGR

RCC Domain 2 configuration register, Address offset: 0x1C.

Definition at line 1241 of file stm32h723xx.h.

◆ D3AMR

__IO uint32_t RCC_TypeDef::D3AMR

RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8.

Definition at line 1276 of file stm32h723xx.h.

◆ D3CCIPR

__IO uint32_t RCC_TypeDef::D3CCIPR

RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58.

Definition at line 1256 of file stm32h723xx.h.

◆ D3CFGR

__IO uint32_t RCC_TypeDef::D3CFGR

RCC Domain 3 configuration register, Address offset: 0x20.

Definition at line 1242 of file stm32h723xx.h.

◆ GCR

__IO uint32_t RCC_TypeDef::GCR

RCC RCC Global Control Register, Address offset: 0xA0.

Definition at line 1274 of file stm32h723xx.h.

◆ HSICFGR

__IO uint32_t RCC_TypeDef::HSICFGR

HSI Clock Calibration Register, Address offset: 0x04.

Definition at line 1235 of file stm32h723xx.h.

◆ PLL1DIVR

__IO uint32_t RCC_TypeDef::PLL1DIVR

RCC PLL1 Dividers Configuration Register, Address offset: 0x30.

Definition at line 1246 of file stm32h723xx.h.

◆ PLL1FRACR

__IO uint32_t RCC_TypeDef::PLL1FRACR

RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34.

Definition at line 1247 of file stm32h723xx.h.

◆ PLL2DIVR

__IO uint32_t RCC_TypeDef::PLL2DIVR

RCC PLL2 Dividers Configuration Register, Address offset: 0x38.

Definition at line 1248 of file stm32h723xx.h.

◆ PLL2FRACR

__IO uint32_t RCC_TypeDef::PLL2FRACR

RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C.

Definition at line 1249 of file stm32h723xx.h.

◆ PLL3DIVR

__IO uint32_t RCC_TypeDef::PLL3DIVR

RCC PLL3 Dividers Configuration Register, Address offset: 0x40.

Definition at line 1250 of file stm32h723xx.h.

◆ PLL3FRACR

__IO uint32_t RCC_TypeDef::PLL3FRACR

RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44.

Definition at line 1251 of file stm32h723xx.h.

◆ PLLCFGR

__IO uint32_t RCC_TypeDef::PLLCFGR

RCC PLLs Configuration Register, Address offset: 0x2C.

Definition at line 1245 of file stm32h723xx.h.

◆ PLLCKSELR

__IO uint32_t RCC_TypeDef::PLLCKSELR

RCC PLLs Clock Source Selection Register, Address offset: 0x28.

Definition at line 1244 of file stm32h723xx.h.

◆ RESERVED1

uint32_t RCC_TypeDef::RESERVED1

Reserved, Address offset: 0x14.

Definition at line 1239 of file stm32h723xx.h.

◆ RESERVED11

uint32_t RCC_TypeDef::RESERVED11[9]

Reserved, 0xAC-0xCC Address offset: 0xAC.

Definition at line 1277 of file stm32h723xx.h.

◆ RESERVED12

uint32_t RCC_TypeDef::RESERVED12

Reserved, Address offset: 0xF8.

Definition at line 1288 of file stm32h723xx.h.

◆ RESERVED13

uint32_t RCC_TypeDef::RESERVED13[4]

Reserved, 0x120-0x12C Address offset: 0x120.

Definition at line 1298 of file stm32h723xx.h.

◆ RESERVED2

uint32_t RCC_TypeDef::RESERVED2

Reserved, Address offset: 0x24.

Definition at line 1243 of file stm32h723xx.h.

◆ RESERVED3

uint32_t RCC_TypeDef::RESERVED3

Reserved, Address offset: 0x48.

Definition at line 1252 of file stm32h723xx.h.

◆ RESERVED4

uint32_t RCC_TypeDef::RESERVED4

Reserved, Address offset: 0x5C.

Definition at line 1257 of file stm32h723xx.h.

◆ RESERVED5

uint32_t RCC_TypeDef::RESERVED5

Reserved, Address offset: 0x6C.

Definition at line 1261 of file stm32h723xx.h.

◆ RESERVED6

uint32_t RCC_TypeDef::RESERVED6

Reserved, Address offset: 0x78.

Definition at line 1264 of file stm32h723xx.h.

◆ RESERVED8

uint32_t RCC_TypeDef::RESERVED8

Reserved, Address offset: 0xA4.

Definition at line 1275 of file stm32h723xx.h.

◆ RSR

__IO uint32_t RCC_TypeDef::RSR

RCC Reset status register, Address offset: 0xD0.

Definition at line 1278 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes