Secure digital input/output Interface. More...

#include <stm32h723xx.h>

Public Attributes
__IO uint32_t	POWER
	SDMMC power control register, Address offset: 0x00.
__IO uint32_t	CLKCR
	SDMMC clock control register, Address offset: 0x04.
__IO uint32_t	ARG
	SDMMC argument register, Address offset: 0x08.
__IO uint32_t	CMD
	SDMMC command register, Address offset: 0x0C.
__I uint32_t	RESPCMD
	SDMMC command response register, Address offset: 0x10.
__I uint32_t	RESP1
	SDMMC response 1 register, Address offset: 0x14.
__I uint32_t	RESP2
	SDMMC response 2 register, Address offset: 0x18.
__I uint32_t	RESP3
	SDMMC response 3 register, Address offset: 0x1C.
__I uint32_t	RESP4
	SDMMC response 4 register, Address offset: 0x20.
__IO uint32_t	DTIMER
	SDMMC data timer register, Address offset: 0x24.
__IO uint32_t	DLEN
	SDMMC data length register, Address offset: 0x28.
__IO uint32_t	DCTRL
	SDMMC data control register, Address offset: 0x2C.
__I uint32_t	DCOUNT
	SDMMC data counter register, Address offset: 0x30.
__I uint32_t	STA
	SDMMC status register, Address offset: 0x34.
__IO uint32_t	ICR
	SDMMC interrupt clear register, Address offset: 0x38.
__IO uint32_t	MASK
	SDMMC mask register, Address offset: 0x3C.
__IO uint32_t	ACKTIME
	SDMMC Acknowledgement timer register, Address offset: 0x40.
uint32_t	RESERVED0 [3]
	Reserved, 0x44 - 0x4C - 0x4C.
__IO uint32_t	IDMACTRL
	SDMMC DMA control register, Address offset: 0x50.
__IO uint32_t	IDMABSIZE
	SDMMC DMA buffer size register, Address offset: 0x54.
__IO uint32_t	IDMABASE0
	SDMMC DMA buffer 0 base address register, Address offset: 0x58.
__IO uint32_t	IDMABASE1
	SDMMC DMA buffer 1 base address register, Address offset: 0x5C.
uint32_t	RESERVED1 [8]
	Reserved, 0x60-0x7C.
__IO uint32_t	FIFO
	SDMMC data FIFO register, Address offset: 0x80.
uint32_t	RESERVED2 [222]
	Reserved, 0x84-0x3F8.
__IO uint32_t	IPVR
	SDMMC data FIFO register, Address offset: 0x3FC.

Detailed Description

Secure digital input/output Interface.

Definition at line 1407 of file stm32h723xx.h.

Member Data Documentation

◆ ACKTIME

__IO uint32_t SDMMC_TypeDef::ACKTIME

SDMMC Acknowledgement timer register, Address offset: 0x40.

Definition at line 1425 of file stm32h723xx.h.

◆ ARG

__IO uint32_t SDMMC_TypeDef::ARG

SDMMC argument register, Address offset: 0x08.

Definition at line 1411 of file stm32h723xx.h.

◆ CLKCR

__IO uint32_t SDMMC_TypeDef::CLKCR

SDMMC clock control register, Address offset: 0x04.

Definition at line 1410 of file stm32h723xx.h.

◆ CMD

__IO uint32_t SDMMC_TypeDef::CMD

SDMMC command register, Address offset: 0x0C.

Definition at line 1412 of file stm32h723xx.h.

◆ DCOUNT

__I uint32_t SDMMC_TypeDef::DCOUNT

SDMMC data counter register, Address offset: 0x30.

Definition at line 1421 of file stm32h723xx.h.

◆ DCTRL

__IO uint32_t SDMMC_TypeDef::DCTRL

SDMMC data control register, Address offset: 0x2C.

Definition at line 1420 of file stm32h723xx.h.

◆ DLEN

__IO uint32_t SDMMC_TypeDef::DLEN

SDMMC data length register, Address offset: 0x28.

Definition at line 1419 of file stm32h723xx.h.

◆ DTIMER

__IO uint32_t SDMMC_TypeDef::DTIMER

SDMMC data timer register, Address offset: 0x24.

Definition at line 1418 of file stm32h723xx.h.

◆ FIFO

__IO uint32_t SDMMC_TypeDef::FIFO

SDMMC data FIFO register, Address offset: 0x80.

Definition at line 1432 of file stm32h723xx.h.

◆ ICR

__IO uint32_t SDMMC_TypeDef::ICR

SDMMC interrupt clear register, Address offset: 0x38.

Definition at line 1423 of file stm32h723xx.h.

◆ IDMABASE0

__IO uint32_t SDMMC_TypeDef::IDMABASE0

SDMMC DMA buffer 0 base address register, Address offset: 0x58.

Definition at line 1429 of file stm32h723xx.h.

◆ IDMABASE1

__IO uint32_t SDMMC_TypeDef::IDMABASE1

SDMMC DMA buffer 1 base address register, Address offset: 0x5C.

Definition at line 1430 of file stm32h723xx.h.

◆ IDMABSIZE

__IO uint32_t SDMMC_TypeDef::IDMABSIZE

SDMMC DMA buffer size register, Address offset: 0x54.

Definition at line 1428 of file stm32h723xx.h.

◆ IDMACTRL

__IO uint32_t SDMMC_TypeDef::IDMACTRL

SDMMC DMA control register, Address offset: 0x50.

Definition at line 1427 of file stm32h723xx.h.

◆ IPVR

__IO uint32_t SDMMC_TypeDef::IPVR

SDMMC data FIFO register, Address offset: 0x3FC.

Definition at line 1434 of file stm32h723xx.h.

◆ MASK

__IO uint32_t SDMMC_TypeDef::MASK

SDMMC mask register, Address offset: 0x3C.

Definition at line 1424 of file stm32h723xx.h.

◆ POWER

__IO uint32_t SDMMC_TypeDef::POWER

SDMMC power control register, Address offset: 0x00.

Definition at line 1409 of file stm32h723xx.h.

◆ RESERVED0

uint32_t SDMMC_TypeDef::RESERVED0[3]

Reserved, 0x44 - 0x4C - 0x4C.

Definition at line 1426 of file stm32h723xx.h.

◆ RESERVED1

uint32_t SDMMC_TypeDef::RESERVED1[8]

Reserved, 0x60-0x7C.

Definition at line 1431 of file stm32h723xx.h.

◆ RESERVED2

uint32_t SDMMC_TypeDef::RESERVED2[222]

Reserved, 0x84-0x3F8.

Definition at line 1433 of file stm32h723xx.h.

◆ RESP1

__I uint32_t SDMMC_TypeDef::RESP1

SDMMC response 1 register, Address offset: 0x14.

Definition at line 1414 of file stm32h723xx.h.

◆ RESP2

__I uint32_t SDMMC_TypeDef::RESP2

SDMMC response 2 register, Address offset: 0x18.

Definition at line 1415 of file stm32h723xx.h.

◆ RESP3

__I uint32_t SDMMC_TypeDef::RESP3

SDMMC response 3 register, Address offset: 0x1C.

Definition at line 1416 of file stm32h723xx.h.

◆ RESP4

__I uint32_t SDMMC_TypeDef::RESP4

SDMMC response 4 register, Address offset: 0x20.

Definition at line 1417 of file stm32h723xx.h.

◆ RESPCMD

__I uint32_t SDMMC_TypeDef::RESPCMD

SDMMC command response register, Address offset: 0x10.

Definition at line 1413 of file stm32h723xx.h.

◆ STA

__I uint32_t SDMMC_TypeDef::STA

SDMMC status register, Address offset: 0x34.

Definition at line 1422 of file stm32h723xx.h.

The documentation for this struct was generated from the following file:

firmware/Flight_Computer/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

Public Attributes