Header file of FLASH HAL module. More...

#include "stm32h7xx_hal_def.h"

Include dependency graph for stm32h7xx_hal_flash_ex.h:

This graph shows which files directly or indirectly include this file:

Classes
struct	FLASH_EraseInitTypeDef
	FLASH Erase structure definition. More...
struct	FLASH_OBProgramInitTypeDef
	FLASH Option Bytes Program structure definition. More...
struct	FLASH_CRCInitTypeDef
	FLASH Erase structure definition. More...

Macros
#define	FLASH_TYPEERASE_SECTORS 0x00U
	Sectors erase only.
#define	FLASH_TYPEERASE_MASSERASE 0x01U
	Flash Mass erase activation.
#define	OB_WRPSTATE_DISABLE 0x00000000U
	Disable the write protection of the desired bank 1 sectors.
#define	OB_WRPSTATE_ENABLE 0x00000001U
	Enable the write protection of the desired bank 1 sectors.
#define	OPTIONBYTE_WRP 0x01U
	WRP option byte configuration.
#define	OPTIONBYTE_RDP 0x02U
	RDP option byte configuration.
#define	OPTIONBYTE_USER 0x04U
	USER option byte configuration.
#define	OPTIONBYTE_PCROP 0x08U
	PCROP option byte configuration.
#define	OPTIONBYTE_BOR 0x10U
	BOR option byte configuration.
#define	OPTIONBYTE_SECURE_AREA 0x20U
	secure area option byte configuration
#define	OPTIONBYTE_BOOTADD 0x40U
	BOOT ADD option byte configuration.
#define	OPTIONBYTE_ALL
	All option byte configuration.
#define	OB_RDP_LEVEL_0 0xAA00U
#define	OB_RDP_LEVEL_1 0x5500U
#define	OB_RDP_LEVEL_2 0xCC00U
	Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0.
#define	OB_IWDG_SW OB_IWDG1_SW
	Software IWDG selected.
#define	OB_IWDG_HW OB_IWDG1_HW
	Hardware IWDG selected.
#define	OB_STOP_NO_RST 0x40U
	No reset generated when entering in STOP.
#define	OB_STOP_RST 0x00U
	Reset generated when entering in STOP.
#define	OB_STDBY_NO_RST 0x80U
	No reset generated when entering in STANDBY.
#define	OB_STDBY_RST 0x00U
	Reset generated when entering in STANDBY.
#define	OB_IWDG_STOP_FREEZE 0x00000000U
	Freeze IWDG counter in STOP mode.
#define	OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP
	IWDG counter active in STOP mode.
#define	OB_IWDG_STDBY_FREEZE 0x00000000U
	Freeze IWDG counter in STANDBY mode.
#define	OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY
	IWDG counter active in STANDBY mode.
#define	OB_BOR_LEVEL0 0x00000000U
	Reset level threshold is set to 1.6V.
#define	OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
	Reset level threshold is set to 2.1V.
#define	OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
	Reset level threshold is set to 2.4V.
#define	OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 \| FLASH_OPTSR_BOR_LEV_0)
	Reset level threshold is set to 2.7V.
#define	OB_BOOTADDR_ITCM_RAM 0x0000U
	Boot from ITCM RAM (0x00000000).
#define	OB_BOOTADDR_SYSTEM 0x0040U
	Boot from System memory bootloader (0x00100000).
#define	OB_BOOTADDR_ITCM_FLASH 0x0080U
	Boot from Flash on ITCM interface (0x00200000).
#define	OB_BOOTADDR_AXIM_FLASH 0x2000U
	Boot from Flash on AXIM interface (0x08000000).
#define	OB_BOOTADDR_DTCM_RAM 0x8000U
	Boot from DTCM RAM (0x20000000).
#define	OB_BOOTADDR_SRAM1 0x8004U
	Boot from SRAM1 (0x20010000).
#define	OB_BOOTADDR_SRAM2 0x8013U
	Boot from SRAM2 (0x2004C000).
#define	FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
	FLASH Zero Latency cycle.
#define	FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
	FLASH One Latency cycle.
#define	FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
	FLASH Two Latency cycles.
#define	FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
	FLASH Three Latency cycles.
#define	FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
	FLASH Four Latency cycles.
#define	FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
	FLASH Five Latency cycles.
#define	FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
	FLASH Six Latency cycles.
#define	FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
	FLASH Seven Latency cycles.
#define	FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
	FLASH Eight Latency cycle.
#define	FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
	FLASH Nine Latency cycle.
#define	FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
	FLASH Ten Latency cycles.
#define	FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
	FLASH Eleven Latency cycles.
#define	FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
	FLASH Twelve Latency cycles.
#define	FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
	FLASH Thirteen Latency cycles.
#define	FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
	FLASH Fourteen Latency cycles.
#define	FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
	FLASH Fifteen Latency cycles.
#define	FLASH_BANK_1 0x01U
	Bank 1.
#define	OB_PCROP_RDP_NOT_ERASE 0x00000000U
	PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0 or during a mass erase.
#define	OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP
	PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase).
#define	OB_WRP_SECTOR_0 0x00000001U
	Write protection of Sector0.
#define	OB_WRP_SECTOR_1 0x00000002U
	Write protection of Sector1.
#define	OB_WRP_SECTOR_2 0x00000004U
	Write protection of Sector2.
#define	OB_WRP_SECTOR_3 0x00000008U
	Write protection of Sector3.
#define	OB_WRP_SECTOR_4 0x00000010U
	Write protection of Sector4.
#define	OB_WRP_SECTOR_5 0x00000020U
	Write protection of Sector5.
#define	OB_WRP_SECTOR_6 0x00000040U
	Write protection of Sector6.
#define	OB_WRP_SECTOR_7 0x00000080U
	Write protection of Sector7.
#define	OB_WRP_SECTOR_ALL 0x000000FFU
	Write protection of all Sectors.
#define	OB_SECURITY_DISABLE 0x00000000U
	security enabled
#define	OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY
	security disabled
#define	OB_ST_RAM_SIZE_2KB 0x00000000U
	2 Kbytes reserved to ST code
#define	OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
	4 Kbytes reserved to ST code
#define	OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
	8 Kbytes reserved to ST code
#define	OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE
	16 Kbytes reserved to ST code
#define	OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
	Hardware independent watchdog 1.
#define	OB_IWDG1_HW 0x00000000U
	Software independent watchdog 1.
#define	OB_STOP_RST_D1 0x00000000U
	Reset generated when entering the D1 to stop mode.
#define	OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1
	No reset generated when entering the D1 to stop mode.
#define	OB_STDBY_RST_D1 0x00000000U
	Reset generated when entering the D1 to standby mode.
#define	OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1
	No reset generated when entering the D1 to standby mode.
#define	OB_IOHSLV_DISABLE 0x00000000U
	IOHSLV disabled.
#define	OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV
	IOHSLV enabled.
#define	OB_USER_IWDG1_SW 0x0001U
	Independent watchdog selection.
#define	OB_USER_NRST_STOP_D1 0x0002U
	Reset when entering Stop mode selection.
#define	OB_USER_NRST_STDBY_D1 0x0004U
	Reset when entering standby mode selection.
#define	OB_USER_IWDG_STOP 0x0008U
	Independent watchdog counter freeze in stop mode.
#define	OB_USER_IWDG_STDBY 0x0010U
	Independent watchdog counter freeze in standby mode.
#define	OB_USER_ST_RAM_SIZE 0x0020U
	dedicated DTCM Ram size selection
#define	OB_USER_SECURITY 0x0040U
	security selection
#define	OB_USER_IOHSLV 0x0080U
	IO HSLV selection.
#define	OB_USER_ALL
#define	OB_BOOT_ADD0 0x01U
	Select Boot Address 0.
#define	OB_BOOT_ADD1 0x02U
	Select Boot Address 1.
#define	OB_BOOT_ADD_BOTH 0x03U
	Select Boot Address 0 and 1.
#define	OB_SECURE_RDP_NOT_ERASE 0x00000000U
	Secure area is not erased when the RDP level is decreased from Level 1 to Level 0 or during a mass erase.
#define	OB_SECURE_RDP_ERASE FLASH_SCAR_DMES
	Secure area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase).
#define	FLASH_CRC_ADDR 0x00000000U
	CRC selection type by address.
#define	FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
	CRC selection type by sectors.
#define	FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK \| FLASH_CRCCR_CRC_BY_SECT)
	CRC selection type by bank.
#define	FLASH_CRC_BURST_SIZE_4 0x00000000U
	Every burst has a size of 4 Flash words (256-bit).
#define	FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
	Every burst has a size of 16 Flash words (256-bit).
#define	FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
	Every burst has a size of 64 Flash words (256-bit).
#define	FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST
	Every burst has a size of 256 Flash words (256-bit).
#define	FLASH_PROGRAMMING_DELAY_0 0x00000000U
	programming delay set for Flash running at 70 MHz or below
#define	FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
	programming delay set for Flash running between 70 MHz and 185 MHz
#define	FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
	programming delay set for Flash running between 185 MHz and 225 MHz
#define	FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ
	programming delay set for Flash at startup
#define	__HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__)
	Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1).
#define	__HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)
	Set the FLASH Programming Delay.
#define	__HAL_FLASH_GET_PROGRAM_DELAY()
	Get the FLASH Programming Delay.
#define	IS_FLASH_TYPEERASE(VALUE)
#define	IS_WRPSTATE(VALUE)
#define	IS_OPTIONBYTE(VALUE)
#define	IS_OB_BOOT_ADDRESS(ADDRESS)
#define	IS_OB_RDP_LEVEL(LEVEL)
#define	IS_OB_IWDG_SOURCE(SOURCE)
#define	IS_OB_STOP_SOURCE(SOURCE)
#define	IS_OB_STDBY_SOURCE(SOURCE)
#define	IS_OB_IWDG_STOP_FREEZE(FREEZE)
#define	IS_OB_IWDG_STDBY_FREEZE(FREEZE)
#define	IS_OB_BOR_LEVEL(LEVEL)
#define	IS_FLASH_LATENCY(LATENCY)
#define	IS_FLASH_SECTOR(SECTOR)
#define	IS_OB_WRP_SECTOR(SECTOR)
#define	IS_OB_PCROP_RDP(CONFIG)
#define	IS_OB_SECURE_RDP(CONFIG)
#define	IS_OB_USER_IOHSLV(VALUE)
#define	IS_OB_IWDG1_SOURCE(SOURCE)
#define	IS_OB_STOP_D1_RESET(VALUE)
#define	IS_OB_STDBY_D1_RESET(VALUE)
#define	IS_OB_USER_IWDG_STOP(VALUE)
#define	IS_OB_USER_IWDG_STDBY(VALUE)
#define	IS_OB_USER_ST_RAM_SIZE(VALUE)
#define	IS_OB_USER_SECURITY(VALUE)
#define	IS_OB_USER_TYPE(TYPE)
#define	IS_OB_BOOT_ADD_OPTION(VALUE)
#define	IS_FLASH_TYPECRC(VALUE)

Functions
HAL_StatusTypeDef	HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef pEraseInit, uint32_t SectorError)
HAL_StatusTypeDef	HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
HAL_StatusTypeDef	HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
void	HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
HAL_StatusTypeDef	HAL_FLASHEx_Unlock_Bank1 (void)
HAL_StatusTypeDef	HAL_FLASHEx_Lock_Bank1 (void)
HAL_StatusTypeDef	HAL_FLASHEx_ComputeCRC (FLASH_CRCInitTypeDef pCRCInit, uint32_t CRC_Result)
void	FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)

Detailed Description

Header file of FLASH HAL module.

Author: MCD Application Team

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h7xx_hal_flash_ex.h.

Classes

Macros

Functions

Detailed Description