118#ifdef HAL_GPIO_MODULE_ENABLED
126#if defined(DUAL_CORE)
127#define EXTI_CPU1 (0x01000000U)
128#define EXTI_CPU2 (0x02000000U)
130#define GPIO_NUMBER (16U)
167 uint32_t position = 0x00U;
172#if defined(DUAL_CORE) && defined(CORE_CM4)
184 while (((GPIO_Init->
Pin) >> position) != 0x00U)
187 iocurrent = (GPIO_Init->
Pin) & (1UL << position);
189 if (iocurrent != 0x00U)
201 temp |= (GPIO_Init->
Speed << (position * 2U));
220 temp |= ((GPIO_Init->
Pull) << (position * 2U));
232 temp = GPIOx->
AFR[position >> 3U];
233 temp &= ~(0xFUL << ((position & 0x07U) * 4U));
234 temp |= ((GPIO_Init->
Alternate) << ((position & 0x07U) * 4U));
235 GPIOx->
AFR[position >> 3U] =
temp;
252 temp &= ~(0x0FUL << (4U * (position & 0x03U)));
258 temp &= ~(iocurrent);
266 temp &= ~(iocurrent);
274 temp &= ~(iocurrent);
283 temp &= ~(iocurrent);
305 uint32_t position = 0x00U;
310#if defined(DUAL_CORE) && defined(CORE_CM4)
321 while ((GPIO_Pin >> position) != 0x00U)
324 iocurrent = GPIO_Pin & (1UL << position) ;
326 if (iocurrent != 0x00U)
330 tmp =
SYSCFG->EXTICR[position >> 2U];
331 tmp &= (0x0FUL << (4U * (position & 0x03U)));
335 EXTI_CurrentCPU->
IMR1 &= ~(iocurrent);
336 EXTI_CurrentCPU->
EMR1 &= ~(iocurrent);
339 EXTI->FTSR1 &= ~(iocurrent);
340 EXTI->RTSR1 &= ~(iocurrent);
342 tmp = 0x0FUL << (4U * (position & 0x03U));
343 SYSCFG->EXTICR[position >> 2U] &= ~tmp;
351 GPIOx->
AFR[position >> 3U] &= ~(0xFUL << ((position & 0x07U) * 4U)) ;
397 if ((GPIOx->
IDR & GPIO_Pin) != 0x00U)
432 GPIOx->
BSRR = GPIO_Pin;
436 GPIOx->
BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
457 GPIOx->
BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
484 GPIOx->
LCKR = GPIO_Pin;
508#if defined(DUAL_CORE) && defined(CORE_CM4)
509 if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
511 __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
#define __IO
Defines 'read / write' permissions.
#define IS_GPIO_ALL_INSTANCE(INSTANCE)
#define IS_GPIO_AF_INSTANCE(INSTANCE)
#define IS_GPIO_LOCK_INSTANCE(INSTANCE)
#define GPIO_GET_INDEX(__GPIOx__)
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
Checks whether the specified EXTI line is asserted or not.
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
Clears the EXTI's line pending bits.
GPIO_PinState
GPIO Bit SET and Bit RESET enumeration.
#define IS_GPIO_PULL(PULL)
#define IS_GPIO_PIN(__PIN__)
#define IS_GPIO_PIN_ACTION(ACTION)
#define IS_GPIO_SPEED(SPEED)
#define IS_GPIO_MODE(MODE)
#define GPIO_PULLUP
Pull-up activation.
#define GPIO_OSPEEDR_OSPEED0
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
Enable or disable the APB4 peripheral clock.
This file contains all the functions prototypes for the HAL module driver.
#define assert_param(expr)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
HAL_StatusTypeDef
HAL Status structures definition.
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
__IO uint32_t EMR1
EXTI Event mask register, Address offset: 0x04.
__IO uint32_t IMR1
EXTI Interrupt mask register, Address offset: 0x00.
GPIO Init structure definition.
uint32_t Mode
Specifies the operating mode for the selected pins.
uint32_t Alternate
Peripheral to be connected to the selected pins.
uint32_t Pull
Specifies the Pull-up or Pull-Down activation for the selected pins.
uint32_t Pin
Specifies the GPIO pins to be configured.
uint32_t Speed
Specifies the speed for the selected pins.
__IO uint32_t OSPEEDR
GPIO port output speed register, Address offset: 0x08.
__IO uint32_t AFR[2]
GPIO alternate function registers, Address offset: 0x20-0x24.
__IO uint32_t PUPDR
GPIO port pull-up/pull-down register, Address offset: 0x0C.
__IO uint32_t ODR
GPIO port output data register, Address offset: 0x14.
__IO uint32_t OTYPER
GPIO port output type register, Address offset: 0x04.
__IO uint32_t LCKR
GPIO port configuration lock register, Address offset: 0x1C.
__IO uint32_t MODER
GPIO port mode register, Address offset: 0x00.
__IO uint32_t BSRR
GPIO port bit set/reset, Address offset: 0x18.
__IO uint32_t IDR
GPIO port input data register, Address offset: 0x10.