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Header file of ADC HAL extended module. More...
#include "stm32h7xx_hal_def.h"Go to the source code of this file.
Classes | |
| struct | ADC_InjOversamplingTypeDef |
| ADC Injected Conversion Oversampling structure definition. More... | |
| struct | ADC_InjectionConfTypeDef |
| Structure definition of ADC group injected and ADC channel affected to ADC group injected. More... | |
| struct | ADC_MultiModeTypeDef |
| Structure definition of ADC multimode. More... | |
Macros | |
| #define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) |
| Software triggers injected group conversion start. | |
| #define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) |
| ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). | |
| #define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) |
| ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). | |
| #define | ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) |
| ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). | |
| #define | ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) |
| ADC group injected conversion trigger from external peripheral: external interrupt line 15. | |
| #define | ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) |
| ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). | |
| #define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) |
| ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. | |
| #define | ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) |
| ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. | |
| #define | ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) |
| ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). | |
| #define | ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) |
| ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). | |
| #define | ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) |
| ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. | |
| #define | ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) |
| ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. | |
| #define | ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) |
| ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. | |
| #define | ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) |
| ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. | |
| #define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) |
| Injected conversions hardware trigger detection disabled. | |
| #define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) |
| Injected conversions hardware trigger detection on the rising edge. | |
| #define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) |
| Injected conversions hardware trigger detection on the falling edge. | |
| #define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) |
| Injected conversions hardware trigger detection on both the rising and falling edges. | |
| #define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) |
| ADC channel ending set to single ended (literal also used to set calibration mode). | |
| #define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) |
| ADC channel ending set to differential (literal also used to set calibration mode). | |
| #define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) |
| ADC offset disabled: no offset correction for the selected ADC channel. | |
| #define | ADC_OFFSET_1 (LL_ADC_OFFSET_1) |
| ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected). | |
| #define | ADC_OFFSET_2 (LL_ADC_OFFSET_2) |
| ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected). | |
| #define | ADC_OFFSET_3 (LL_ADC_OFFSET_3) |
| ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected). | |
| #define | ADC_OFFSET_4 (LL_ADC_OFFSET_4) |
| ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected). | |
| #define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) |
| ADC group injected sequencer rank 1. | |
| #define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) |
| ADC group injected sequencer rank 2. | |
| #define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) |
| ADC group injected sequencer rank 3. | |
| #define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) |
| ADC group injected sequencer rank 4. | |
| #define | ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) |
| ADC dual mode disabled (ADC independent mode). | |
| #define | ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) |
| ADC dual mode enabled: group regular simultaneous. | |
| #define | ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) |
| ADC dual mode enabled: Combined group regular interleaved. | |
| #define | ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) |
| ADC dual mode enabled: group injected simultaneous. | |
| #define | ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) |
| ADC dual mode enabled: group injected alternate trigger. | |
| #define | ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) |
| ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous. | |
| #define | ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) |
| ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger. | |
| #define | ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) |
| ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous. | |
| #define | ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) |
| Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used. | |
| #define | ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) |
| Data formatting mode for 32 down to 10-bit resolution. | |
| #define | ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) |
| Data formatting mode for 8-bit resolution. | |
| #define | ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) |
| ADC multimode delay between two sampling phases: 1 ADC clock cycle. | |
| #define | ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) |
| ADC multimode delay between two sampling phases: 2 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) |
| ADC multimode delay between two sampling phases: 3 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) |
| ADC multimode delay between two sampling phases: 4 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) |
| ADC multimode delay between two sampling phases: 5 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) |
| ADC multimode delay between two sampling phases: 6 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) |
| ADC multimode delay between two sampling phases: 7 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) |
| ADC multimode delay between two sampling phases: 8 ADC clock cycles. | |
| #define | ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) |
| ADC multimode delay between two sampling phases: 9 ADC clock cycles. | |
| #define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) |
| ADC group regular (available on all STM32 devices). | |
| #define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) |
| ADC group injected (not available on all STM32 devices). | |
| #define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) |
| ADC both groups regular and injected. | |
| #define | ADC_CFGR_FIELDS |
| #define | ADC_SMPR1_FIELDS |
| #define | ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) |
| #define | ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) |
| Force ADC instance in multimode mode independent (multimode disable). | |
| #define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) |
| Test if conversion trigger of injected group is software start or external trigger. | |
| #define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) |
| Check if conversion is on going on regular or injected groups. | |
| #define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) |
| Check if conversion is on going on injected group. | |
| #define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) |
| Set the selected injected Channel rank. | |
| #define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) |
| Configure ADC injected context queue. | |
| #define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) |
| Configure ADC discontinuous conversion mode for injected group. | |
| #define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) |
| Configure ADC discontinuous conversion mode for regular group. | |
| #define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) |
| Configure the number of discontinuous conversions for regular group. | |
| #define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) |
| Configure the ADC auto delay mode. | |
| #define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) |
| Configure ADC continuous conversion mode. | |
| #define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) |
| Enable the ADC DMA continuous request. | |
| #define | ADC_OFR_CHANNEL(__CHANNEL__) |
| Configure the channel number into offset OFRx register. | |
| #define | ADC_DIFSEL_CHANNEL(__CHANNEL__) |
| Configure the channel number into differential mode selection register. | |
| #define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) |
| Configure calibration factor in differential mode to be set into calibration register. | |
| #define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) |
| Calibration factor in differential mode to be retrieved from calibration register. | |
| #define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) |
| Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. | |
| #define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) |
| Configure the ADC DMA continuous request for ADC multimode. | |
| #define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) |
| Shift the offset in function of the selected ADC resolution. | |
| #define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) |
| Shift the AWD1 threshold in function of the selected ADC resolution. | |
| #define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) |
| Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. | |
| #define | ADC12_COMMON_REGISTER(__HANDLE__) |
| Clear Common Control Register. | |
| #define | ADC_MASTER_REGISTER(__HANDLE__) |
| Report Master Instance. | |
| #define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) |
| Check whether or not dual regular conversions are enabled. | |
| #define | ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) |
| Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master. | |
| #define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) |
| Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. | |
| #define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) |
| Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. | |
| #define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) |
| #define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) |
| Set handle instance of the ADC slave associated to the ADC master. | |
| #define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) |
| Verify the ADC instance connected to the temperature sensor. | |
| #define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) |
| Verify the ADC instance connected to the battery voltage VBAT. | |
| #define | ADC_VREFINT_INSTANCE(__HANDLE__) |
| Verify the ADC instance connected to the internal voltage reference VREFINT. | |
| #define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) |
| Verify the length of scheduled injected conversions group. | |
| #define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) |
| Calibration factor size verification (11 bits maximum). | |
| #define | IS_ADC_CHANNEL(__CHANNEL__) |
| Verify the ADC channel setting. | |
| #define | IS_ADC1_DIFF_CHANNEL(__CHANNEL__) |
| Verify the ADC channel setting in differential mode for ADC1. | |
| #define | IS_ADC2_DIFF_CHANNEL(__CHANNEL__) |
| Verify the ADC channel setting in differential mode for ADC2. | |
| #define | IS_ADC3_DIFF_CHANNEL(__CHANNEL__) |
| Verify the ADC channel setting in differential mode for ADC3. | |
| #define | ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) |
| Helper macro to determine the selected channel corresponding negative input for ADC1. | |
| #define | ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) |
| Helper macro to determine the selected channel corresponding negative input for ADC2. | |
| #define | ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) |
| Helper macro to determine the selected channel corresponding negative input on the ADC instance selected. | |
| #define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) |
| Verify the ADC single-ended input or differential mode setting. | |
| #define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) |
| Verify the ADC offset management setting. | |
| #define | IS_ADC_INJECTED_RANK(__CHANNEL__) |
| Verify the ADC injected channel setting. | |
| #define | IS_ADC_EXTTRIGINJEC(__INJTRIG__) |
| Verify the ADC injected conversions external trigger. | |
| #define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) |
| Verify the ADC edge trigger setting for injected group. | |
| #define | IS_ADC_MULTIMODE(__MODE__) |
| Verify the ADC multimode setting. | |
| #define | IS_ADC_DUAL_DATA_MODE(MODE) |
| Verify the ADC dual data mode setting. | |
| #define | IS_ADC_SAMPLING_DELAY(__DELAY__) |
| Verify the ADC multimode delay setting. | |
| #define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) |
| Verify the ADC analog watchdog setting. | |
| #define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) |
| Verify the ADC analog watchdog mode setting. | |
| #define | IS_ADC_CONVERSION_GROUP(__CONVERSION__) |
| Verify the ADC conversion (regular or injected or both). | |
| #define | IS_ADC_EVENT_TYPE(__EVENT__) |
| Verify the ADC event type. | |
| #define | IS_ADC_OVERSAMPLING_RATIO(RATIO) |
| Verify the ADC oversampling ratio. | |
| #define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) |
| Verify the ADC oversampling shift. | |
| #define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) |
| Verify the ADC oversampling triggered mode. | |
| #define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__) |
| Verify the ADC oversampling regular conversion resumed or continued mode. | |
| #define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) |
| Verify the DFSDM mode configuration. | |
| #define | ADC_CFGR_DFSDM(__HANDLE__) |
| Return the DFSDM configuration mode. | |
Header file of ADC HAL extended module.
Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
Definition in file stm32h7xx_hal_adc_ex.h.