Header file of ADC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_ll_adc.h"
#include "stm32h7xx_hal_adc_ex.h"

Include dependency graph for stm32h7xx_hal_adc.h:

This graph shows which files directly or indirectly include this file:

Classes
struct	ADC_OversamplingTypeDef
	ADC group regular oversampling structure definition. More...
struct	ADC_InitTypeDef
	Structure definition of ADC instance and ADC group regular. More...
struct	ADC_ChannelConfTypeDef
	Structure definition of ADC channel for regular group. More...
struct	ADC_AnalogWDGConfTypeDef
	Structure definition of ADC analog watchdog. More...
struct	ADC_InjectionConfigTypeDef
	ADC group injected contexts queue configuration. More...
struct	ADC_HandleTypeDef
	ADC handle Structure definition. More...

Macros
#define	HAL_ADC_STATE_RESET (0x00000000UL)
	HAL ADC state machine: ADC states definition (bitfields).
#define	HAL_ADC_STATE_READY (0x00000001UL)
	ADC peripheral ready for use.
#define	HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
	ADC is busy due to an internal process (initialization, calibration).
#define	HAL_ADC_STATE_TIMEOUT (0x00000004UL)
	TimeOut occurrence.
#define	HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
	Internal error occurrence.
#define	HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
	Configuration error occurrence.
#define	HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
	DMA error occurrence.
#define	HAL_ADC_STATE_REG_BUSY (0x00000100UL)
	A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)).
#define	HAL_ADC_STATE_REG_EOC (0x00000200UL)
	Conversion data available on group regular.
#define	HAL_ADC_STATE_REG_OVR (0x00000400UL)
	Overrun occurrence.
#define	HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
	Not available on this STM32 series: End Of Sampling flag raised.
#define	HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
	A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)).
#define	HAL_ADC_STATE_INJ_EOC (0x00002000UL)
	Conversion data available on group injected.
#define	HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
	Injected queue overflow occurrence.
#define	HAL_ADC_STATE_AWD1 (0x00010000UL)
	Out-of-window occurrence of ADC analog watchdog 1.
#define	HAL_ADC_STATE_AWD2 (0x00020000UL)
	Out-of-window occurrence of ADC analog watchdog 2.
#define	HAL_ADC_STATE_AWD3 (0x00040000UL)
	Out-of-window occurrence of ADC analog watchdog 3.
#define	HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)
	ADC in multimode slave state, controlled by another ADC master (when feature available).
#define	HAL_ADC_ERROR_NONE (0x00U)
	No error.
#define	HAL_ADC_ERROR_INTERNAL (0x01U)
	ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...).
#define	HAL_ADC_ERROR_OVR (0x02U)
	Overrun error.
#define	HAL_ADC_ERROR_DMA (0x04U)
	DMA transfer error.
#define	HAL_ADC_ERROR_JQOVF (0x08U)
	Injected context queue overflow error.
#define	ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
	ADC synchronous clock derived from AHB clock without prescaler.
#define	ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
	ADC synchronous clock derived from AHB clock with prescaler division by 2.
#define	ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
	ADC synchronous clock derived from AHB clock with prescaler division by 4.
#define	ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
	ADC asynchronous clock without prescaler.
#define	ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
	ADC asynchronous clock with prescaler division by 2.
#define	ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
	ADC asynchronous clock with prescaler division by 4.
#define	ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
	ADC asynchronous clock with prescaler division by 6.
#define	ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
	ADC asynchronous clock with prescaler division by 8.
#define	ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
	ADC asynchronous clock with prescaler division by 10.
#define	ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
	ADC asynchronous clock with prescaler division by 12.
#define	ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
	ADC asynchronous clock with prescaler division by 16.
#define	ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
	ADC asynchronous clock with prescaler division by 32.
#define	ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
	ADC asynchronous clock with prescaler division by 64.
#define	ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
	ADC asynchronous clock with prescaler division by 128.
#define	ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)
	ADC asynchronous clock with prescaler division by 256.
#define	ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B)
	ADC resolution 16 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B)
	ADC resolution 14 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
	ADC resolution 12 bits.
#define	ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
	ADC resolution 10 bits.
#define	ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
	ADC resolution 8 bits.
#define	ADC_SCAN_DISABLE (0x00000000UL)
	Scan mode disabled.
#define	ADC_SCAN_ENABLE (0x00000001UL)
	Scan mode enabled.
#define	ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
	ADC group regular conversion trigger internal: SW start.
#define	ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
	ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture).
#define	ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
	ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture).
#define	ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
	ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture).
#define	ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
	ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture).
#define	ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM3 TRGO event.
#define	ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
	ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture).
#define	ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
	ADC group regular conversion trigger from external peripheral: external interrupt line 11 event.
#define	ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM8 TRGO event.
#define	ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
	ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event.
#define	ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM1 TRGO event.
#define	ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
	ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event.
#define	ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM2 TRGO event.
#define	ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM4 TRGO event.
#define	ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM6 TRGO event.
#define	ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
	ADC group regular conversion trigger from external peripheral: TIM15 TRGO event.
#define	ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
	ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture).
#define	ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)
	ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event.
#define	ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)
	ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event.
#define	ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)
	ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event.
#define	ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)
	ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event.
#define	ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)
	ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT.
#define	ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
	Regular conversions hardware trigger detection disabled.
#define	ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
	ADC group regular conversion trigger polarity set to rising edge.
#define	ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
	ADC group regular conversion trigger polarity set to falling edge.
#define	ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)
	ADC group regular conversion trigger polarity set to both rising and falling edges.
#define	ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
	End of unitary conversion flag.
#define	ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
	End of sequence conversions flag.
#define	ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
	ADC group regular behavior in case of overrun: data preserved.
#define	ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)
	ADC group regular behavior in case of overrun: data overwritten.
#define	ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
	ADC group regular sequencer rank 1.
#define	ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
	ADC group regular sequencer rank 2.
#define	ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
	ADC group regular sequencer rank 3.
#define	ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
	ADC group regular sequencer rank 4.
#define	ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
	ADC group regular sequencer rank 5.
#define	ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
	ADC group regular sequencer rank 6.
#define	ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
	ADC group regular sequencer rank 7.
#define	ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
	ADC group regular sequencer rank 8.
#define	ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
	ADC group regular sequencer rank 9.
#define	ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
	ADC group regular sequencer rank 10.
#define	ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
	ADC group regular sequencer rank 11.
#define	ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
	ADC group regular sequencer rank 12.
#define	ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
	ADC group regular sequencer rank 13.
#define	ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
	ADC group regular sequencer rank 14.
#define	ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
	ADC group regular sequencer rank 15.
#define	ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)
	ADC group regular sequencer rank 16.
#define	ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)
	Sampling time 1.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
	Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5)
	Sampling time 8.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5)
	Sampling time 16.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5)
	Sampling time 32.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5)
	Sampling time 64.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5)
	Sampling time 387.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5)
	Sampling time 810.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2.
#define	ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
#define	ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)
#define	ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
	ADC external channel (channel connected to GPIO pin) ADCx_IN0.
#define	ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
	ADC external channel (channel connected to GPIO pin) ADCx_IN1.
#define	ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
	ADC external channel (channel connected to GPIO pin) ADCx_IN2.
#define	ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
	ADC external channel (channel connected to GPIO pin) ADCx_IN3.
#define	ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
	ADC external channel (channel connected to GPIO pin) ADCx_IN4.
#define	ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
	ADC external channel (channel connected to GPIO pin) ADCx_IN5.
#define	ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
	ADC external channel (channel connected to GPIO pin) ADCx_IN6.
#define	ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
	ADC external channel (channel connected to GPIO pin) ADCx_IN7.
#define	ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
	ADC external channel (channel connected to GPIO pin) ADCx_IN8.
#define	ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
	ADC external channel (channel connected to GPIO pin) ADCx_IN9.
#define	ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
	ADC external channel (channel connected to GPIO pin) ADCx_IN10.
#define	ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
	ADC external channel (channel connected to GPIO pin) ADCx_IN11.
#define	ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
	ADC external channel (channel connected to GPIO pin) ADCx_IN12.
#define	ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
	ADC external channel (channel connected to GPIO pin) ADCx_IN13.
#define	ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
	ADC external channel (channel connected to GPIO pin) ADCx_IN14.
#define	ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
	ADC external channel (channel connected to GPIO pin) ADCx_IN15.
#define	ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
	ADC external channel (channel connected to GPIO pin) ADCx_IN16.
#define	ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
	ADC external channel (channel connected to GPIO pin) ADCx_IN17.
#define	ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
	ADC external channel (channel connected to GPIO pin) ADCx_IN18.
#define	ADC_CHANNEL_19 (LL_ADC_CHANNEL_19)
	ADC external channel (channel connected to GPIO pin) ADCx_IN19.
#define	ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
	ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3.
#define	ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
	ADC internal channel connected to Temperature sensor, channel specific to ADC3.
#define	ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
	ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3.
#define	ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2)
	ADC internal channel connected to DAC1 channel 1, channel specific to ADC2.
#define	ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2)
	ADC internal channel connected to DAC1 channel 2, channel specific to ADC2.
#define	ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000)
	Regular Conversion data stored in DR register only.
#define	ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1)
	DFSDM mode selected.
#define	ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0)
	DMA one shot mode selected.
#define	ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 \| ADC_CFGR_DMNGT_1))
	DMA circular mode selected.
#define	ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
	ADC analog watchdog number 1.
#define	ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
	ADC analog watchdog number 2.
#define	ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)
	ADC analog watchdog number 3.
#define	ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
	No analog watchdog selected.
#define	ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN)
	Analog watchdog applied to a regular group single channel.
#define	ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN)
	Analog watchdog applied to an injected group single channel.
#define	ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN)
	Analog watchdog applied to a regular and injected groups single channel.
#define	ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
	Analog watchdog applied to regular group all channels.
#define	ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
	Analog watchdog applied to injected group all channels.
#define	ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN)
	Analog watchdog applied to regular and injected groups all channels.
#define	ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
	ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
	ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
	ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
	ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
	ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
	ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
	ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
	ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
	ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9)
	ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10
	ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data).
#define	ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11
	ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data).
#define	ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE)
	ADC No bit shift.
#define	ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1)
	ADC 1 bit shift.
#define	ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2)
	ADC 2 bits shift.
#define	ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3)
	ADC 3 bits shift.
#define	ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4)
	ADC 4 bits shift.
#define	ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5)
	ADC 5 bits shift.
#define	ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6)
	ADC 6 bits shift.
#define	ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7)
	ADC 7 bits shift.
#define	ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8)
	ADC 8 bits shift.
#define	ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9)
	ADC 9 bits shift.
#define	ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10)
	ADC 10 bits shift.
#define	ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11)
	ADC 11 bits shift.
#define	ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12)
	ADC 12 bits shift.
#define	ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13)
	ADC 13 bits shift.
#define	ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14)
	ADC 14 bits shift.
#define	ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15)
	ADC 15 bits shift.
#define	ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
	ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger).
#define	ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)
	ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger).
#define	ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
	Oversampling buffer maintained during injection sequence.
#define	ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)
	Oversampling buffer zeroed during injection sequence.
#define	ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
	ADC End of Sampling event.
#define	ADC_AWD1_EVENT (ADC_FLAG_AWD1)
	ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series).
#define	ADC_AWD2_EVENT (ADC_FLAG_AWD2)
	ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series).
#define	ADC_AWD3_EVENT (ADC_FLAG_AWD3)
	ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series).
#define	ADC_OVR_EVENT (ADC_FLAG_OVR)
	ADC overrun event.
#define	ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)
	ADC Injected Context Queue Overflow event.
#define	ADC_AWD_EVENT ADC_AWD1_EVENT
	ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog.
#define	ADC_IT_RDY ADC_IER_ADRDYIE
	ADC Ready interrupt source.
#define	ADC_IT_EOSMP ADC_IER_EOSMPIE
	ADC End of sampling interrupt source.
#define	ADC_IT_EOC ADC_IER_EOCIE
	ADC End of regular conversion interrupt source.
#define	ADC_IT_EOS ADC_IER_EOSIE
	ADC End of regular sequence of conversions interrupt source.
#define	ADC_IT_OVR ADC_IER_OVRIE
	ADC overrun interrupt source.
#define	ADC_IT_JEOC ADC_IER_JEOCIE
	ADC End of injected conversion interrupt source.
#define	ADC_IT_JEOS ADC_IER_JEOSIE
	ADC End of injected sequence of conversions interrupt source.
#define	ADC_IT_AWD1 ADC_IER_AWD1IE
	ADC Analog watchdog 1 interrupt source (main analog watchdog).
#define	ADC_IT_AWD2 ADC_IER_AWD2IE
	ADC Analog watchdog 2 interrupt source (additional analog watchdog).
#define	ADC_IT_AWD3 ADC_IER_AWD3IE
	ADC Analog watchdog 3 interrupt source (additional analog watchdog).
#define	ADC_IT_JQOVF ADC_IER_JQOVFIE
	ADC Injected Context Queue Overflow interrupt source.
#define	ADC_IT_AWD ADC_IT_AWD1
	ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog.
#define	ADC_FLAG_RDY ADC_ISR_ADRDY
	ADC Ready flag.
#define	ADC_FLAG_EOSMP ADC_ISR_EOSMP
	ADC End of Sampling flag.
#define	ADC_FLAG_EOC ADC_ISR_EOC
	ADC End of Regular Conversion flag.
#define	ADC_FLAG_EOS ADC_ISR_EOS
	ADC End of Regular sequence of Conversions flag.
#define	ADC_FLAG_OVR ADC_ISR_OVR
	ADC overrun flag.
#define	ADC_FLAG_JEOC ADC_ISR_JEOC
	ADC End of Injected Conversion flag.
#define	ADC_FLAG_JEOS ADC_ISR_JEOS
	ADC End of Injected sequence of Conversions flag.
#define	ADC_FLAG_AWD1 ADC_ISR_AWD1
	ADC Analog watchdog 1 flag (main analog watchdog).
#define	ADC_FLAG_AWD2 ADC_ISR_AWD2
	ADC Analog watchdog 2 flag (additional analog watchdog).
#define	ADC_FLAG_AWD3 ADC_ISR_AWD3
	ADC Analog watchdog 3 flag (additional analog watchdog).
#define	ADC_FLAG_JQOVF ADC_ISR_JQOVF
	ADC Injected Context Queue Overflow flag.
#define	ADC_FLAG_LDORDY ADC_ISR_LDORDY
	ADC LDO output voltage ready bit.
#define	IS_ADC_CONVERSIONDATAMGT(DATA)
	Verify the ADC data conversion setting.
#define	ADC_GET_RESOLUTION(__HANDLE__)
	Return resolution bits in CFGR register RES[1:0] field.
#define	ADC_CLEAR_ERRORCODE(__HANDLE__)
	Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define	ADC_IS_ENABLE(__HANDLE__)
	Verification of ADC state: enabled or disabled.
#define	ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)
	Check if conversion is on going on regular group.
#define	ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)
	Check if ADC clock mode is synchronous.
#define	ADC_STATE_CLR_SET MODIFY_REG
	Simultaneously clear and set specific bits of the handle State.
#define	IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)
	Verify that a given value is aligned with the ADC resolution range.
#define	IS_ADC_REGULAR_NB_CONV(__LENGTH__)
	Verify the length of the scheduled regular conversions group.
#define	IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER)
	Verify the number of scheduled regular conversions in discontinuous mode.
#define	IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
	Verify the ADC clock setting.
#define	IS_ADC_RESOLUTION(__RESOLUTION__)
	Verify the ADC resolution setting.
#define	IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__)
	Verify the ADC resolution setting when limited to 8 bits.
#define	IS_ADC_SCAN_MODE(__SCAN_MODE__)
	Verify the ADC scan mode.
#define	IS_ADC_EXTTRIG_EDGE(__EDGE__)
	Verify the ADC edge trigger setting for regular group.
#define	IS_ADC_EXTTRIG(__REGTRIG__)
	Verify the ADC regular conversions external trigger.
#define	IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
	Verify the ADC regular conversions check for converted data availability.
#define	IS_ADC_OVERRUN(__OVR__)
	Verify the ADC regular conversions overrun handling.
#define	IS_ADC_SAMPLE_TIME(__TIME__)
	Verify the ADC conversions sampling time.
#define	IS_ADC_REGULAR_RANK(__CHANNEL__)
	Verify the ADC regular channel setting.
#define	ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
	ADC stop time-out value.
#define	ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
#define	ADC_STAB_DELAY_US (10UL)
	ADC voltage regulator startup time.
#define	__HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
	Reset ADC handle state.
#define	__HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)
	Enable ADC interrupt.
#define	__HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)
	Disable ADC interrupt.
#define	__HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
	Checks if the specified ADC interrupt source is enabled or disabled.
#define	__HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)
	Check whether the specified ADC flag is set or not.
#define	__HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)
	Clear the specified ADC flag.
#define	__HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
	Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define	__HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
	Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define	__HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)
	Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define	__HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)
	Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define	__HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
	Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define	__HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)
	Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define	__HAL_ADC_COMMON_INSTANCE(__ADCx__)
	Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define	__HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
	Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define	__HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)
	Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define	__HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
	Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define	__HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define	__HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define	__HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define	__HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions
HAL_StatusTypeDef	HAL_ADC_Init (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
void	HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
	ADC MSP Initialization This function configures the hardware resources used in this example.
void	HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
	ADC MSP De-Initialization This function freeze the hardware resources used in this example.
HAL_StatusTypeDef	HAL_ADC_Start (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
HAL_StatusTypeDef	HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
HAL_StatusTypeDef	HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	HAL_ADC_Start_DMA (ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length)
HAL_StatusTypeDef	HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
uint32_t	HAL_ADC_GetValue (const ADC_HandleTypeDef *hadc)
void	HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
void	HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
void	HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
void	HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
void	HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	HAL_ADC_ConfigChannel (ADC_HandleTypeDef hadc, ADC_ChannelConfTypeDef sConfig)
HAL_StatusTypeDef	HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef hadc, ADC_AnalogWDGConfTypeDef AnalogWDGConfig)
uint32_t	HAL_ADC_GetState (const ADC_HandleTypeDef *hadc)
uint32_t	HAL_ADC_GetError (const ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
HAL_StatusTypeDef	ADC_Enable (ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef	ADC_Disable (ADC_HandleTypeDef *hadc)
void	ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
void	ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
void	ADC_DMAError (DMA_HandleTypeDef *hdma)
void	ADC_ConfigureBoostMode (ADC_HandleTypeDef *hadc)

Detailed Description

Header file of ADC HAL module.

Author: MCD Application Team

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h7xx_hal_adc.h.

Classes

Macros

Functions

Detailed Description