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stm32h7xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_dma_ex.h"
Include dependency graph for stm32h7xx_hal_dma.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  DMA_InitTypeDef
 DMA Configuration Structure definition. More...
struct  __DMA_HandleTypeDef
 DMA handle Structure definition. More...

Macros

#define HAL_DMA_ERROR_NONE   (0x00000000U)
 No error.
#define HAL_DMA_ERROR_TE   (0x00000001U)
 Transfer error.
#define HAL_DMA_ERROR_FE   (0x00000002U)
 FIFO error.
#define HAL_DMA_ERROR_DME   (0x00000004U)
 Direct Mode error.
#define HAL_DMA_ERROR_TIMEOUT   (0x00000020U)
 Timeout error.
#define HAL_DMA_ERROR_PARAM   (0x00000040U)
 Parameter error.
#define HAL_DMA_ERROR_NO_XFER   (0x00000080U)
 Abort requested with no Xfer ongoing.
#define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)
 Not supported mode.
#define HAL_DMA_ERROR_SYNC   (0x00000200U)
 DMAMUX sync overrun error.
#define HAL_DMA_ERROR_REQGEN   (0x00000400U)
 DMAMUX request generator overrun error.
#define HAL_DMA_ERROR_BUSY   (0x00000800U)
 DMA Busy error.
#define DMA_REQUEST_MEM2MEM   0U
 memory to memory transfer
#define DMA_REQUEST_GENERATOR0   1U
 DMAMUX1 request generator 0.
#define DMA_REQUEST_GENERATOR1   2U
 DMAMUX1 request generator 1.
#define DMA_REQUEST_GENERATOR2   3U
 DMAMUX1 request generator 2.
#define DMA_REQUEST_GENERATOR3   4U
 DMAMUX1 request generator 3.
#define DMA_REQUEST_GENERATOR4   5U
 DMAMUX1 request generator 4.
#define DMA_REQUEST_GENERATOR5   6U
 DMAMUX1 request generator 5.
#define DMA_REQUEST_GENERATOR6   7U
 DMAMUX1 request generator 6.
#define DMA_REQUEST_GENERATOR7   8U
 DMAMUX1 request generator 7.
#define DMA_REQUEST_ADC1   9U
 DMAMUX1 ADC1 request.
#define DMA_REQUEST_ADC2   10U
 DMAMUX1 ADC2 request.
#define DMA_REQUEST_TIM1_CH1   11U
 DMAMUX1 TIM1 CH1 request.
#define DMA_REQUEST_TIM1_CH2   12U
 DMAMUX1 TIM1 CH2 request.
#define DMA_REQUEST_TIM1_CH3   13U
 DMAMUX1 TIM1 CH3 request.
#define DMA_REQUEST_TIM1_CH4   14U
 DMAMUX1 TIM1 CH4 request.
#define DMA_REQUEST_TIM1_UP   15U
 DMAMUX1 TIM1 UP request.
#define DMA_REQUEST_TIM1_TRIG   16U
 DMAMUX1 TIM1 TRIG request.
#define DMA_REQUEST_TIM1_COM   17U
 DMAMUX1 TIM1 COM request.
#define DMA_REQUEST_TIM2_CH1   18U
 DMAMUX1 TIM2 CH1 request.
#define DMA_REQUEST_TIM2_CH2   19U
 DMAMUX1 TIM2 CH2 request.
#define DMA_REQUEST_TIM2_CH3   20U
 DMAMUX1 TIM2 CH3 request.
#define DMA_REQUEST_TIM2_CH4   21U
 DMAMUX1 TIM2 CH4 request.
#define DMA_REQUEST_TIM2_UP   22U
 DMAMUX1 TIM2 UP request.
#define DMA_REQUEST_TIM3_CH1   23U
 DMAMUX1 TIM3 CH1 request.
#define DMA_REQUEST_TIM3_CH2   24U
 DMAMUX1 TIM3 CH2 request.
#define DMA_REQUEST_TIM3_CH3   25U
 DMAMUX1 TIM3 CH3 request.
#define DMA_REQUEST_TIM3_CH4   26U
 DMAMUX1 TIM3 CH4 request.
#define DMA_REQUEST_TIM3_UP   27U
 DMAMUX1 TIM3 UP request.
#define DMA_REQUEST_TIM3_TRIG   28U
 DMAMUX1 TIM3 TRIG request.
#define DMA_REQUEST_TIM4_CH1   29U
 DMAMUX1 TIM4 CH1 request.
#define DMA_REQUEST_TIM4_CH2   30U
 DMAMUX1 TIM4 CH2 request.
#define DMA_REQUEST_TIM4_CH3   31U
 DMAMUX1 TIM4 CH3 request.
#define DMA_REQUEST_TIM4_UP   32U
 DMAMUX1 TIM4 UP request.
#define DMA_REQUEST_I2C1_RX   33U
 DMAMUX1 I2C1 RX request.
#define DMA_REQUEST_I2C1_TX   34U
 DMAMUX1 I2C1 TX request.
#define DMA_REQUEST_I2C2_RX   35U
 DMAMUX1 I2C2 RX request.
#define DMA_REQUEST_I2C2_TX   36U
 DMAMUX1 I2C2 TX request.
#define DMA_REQUEST_SPI1_RX   37U
 DMAMUX1 SPI1 RX request.
#define DMA_REQUEST_SPI1_TX   38U
 DMAMUX1 SPI1 TX request.
#define DMA_REQUEST_SPI2_RX   39U
 DMAMUX1 SPI2 RX request.
#define DMA_REQUEST_SPI2_TX   40U
 DMAMUX1 SPI2 TX request.
#define DMA_REQUEST_USART1_RX   41U
 DMAMUX1 USART1 RX request.
#define DMA_REQUEST_USART1_TX   42U
 DMAMUX1 USART1 TX request.
#define DMA_REQUEST_USART2_RX   43U
 DMAMUX1 USART2 RX request.
#define DMA_REQUEST_USART2_TX   44U
 DMAMUX1 USART2 TX request.
#define DMA_REQUEST_USART3_RX   45U
 DMAMUX1 USART3 RX request.
#define DMA_REQUEST_USART3_TX   46U
 DMAMUX1 USART3 TX request.
#define DMA_REQUEST_TIM8_CH1   47U
 DMAMUX1 TIM8 CH1 request.
#define DMA_REQUEST_TIM8_CH2   48U
 DMAMUX1 TIM8 CH2 request.
#define DMA_REQUEST_TIM8_CH3   49U
 DMAMUX1 TIM8 CH3 request.
#define DMA_REQUEST_TIM8_CH4   50U
 DMAMUX1 TIM8 CH4 request.
#define DMA_REQUEST_TIM8_UP   51U
 DMAMUX1 TIM8 UP request.
#define DMA_REQUEST_TIM8_TRIG   52U
 DMAMUX1 TIM8 TRIG request.
#define DMA_REQUEST_TIM8_COM   53U
 DMAMUX1 TIM8 COM request.
#define DMA_REQUEST_TIM5_CH1   55U
 DMAMUX1 TIM5 CH1 request.
#define DMA_REQUEST_TIM5_CH2   56U
 DMAMUX1 TIM5 CH2 request.
#define DMA_REQUEST_TIM5_CH3   57U
 DMAMUX1 TIM5 CH3 request.
#define DMA_REQUEST_TIM5_CH4   58U
 DMAMUX1 TIM5 CH4 request.
#define DMA_REQUEST_TIM5_UP   59U
 DMAMUX1 TIM5 UP request.
#define DMA_REQUEST_TIM5_TRIG   60U
 DMAMUX1 TIM5 TRIG request.
#define DMA_REQUEST_SPI3_RX   61U
 DMAMUX1 SPI3 RX request.
#define DMA_REQUEST_SPI3_TX   62U
 DMAMUX1 SPI3 TX request.
#define DMA_REQUEST_UART4_RX   63U
 DMAMUX1 UART4 RX request.
#define DMA_REQUEST_UART4_TX   64U
 DMAMUX1 UART4 TX request.
#define DMA_REQUEST_UART5_RX   65U
 DMAMUX1 UART5 RX request.
#define DMA_REQUEST_UART5_TX   66U
 DMAMUX1 UART5 TX request.
#define DMA_REQUEST_DAC1_CH1   67U
 DMAMUX1 DAC1 Channel 1 request.
#define DMA_REQUEST_DAC1_CH2   68U
 DMAMUX1 DAC1 Channel 2 request.
#define DMA_REQUEST_TIM6_UP   69U
 DMAMUX1 TIM6 UP request.
#define DMA_REQUEST_TIM7_UP   70U
 DMAMUX1 TIM7 UP request.
#define DMA_REQUEST_USART6_RX   71U
 DMAMUX1 USART6 RX request.
#define DMA_REQUEST_USART6_TX   72U
 DMAMUX1 USART6 TX request.
#define DMA_REQUEST_I2C3_RX   73U
 DMAMUX1 I2C3 RX request.
#define DMA_REQUEST_I2C3_TX   74U
 DMAMUX1 I2C3 TX request.
#define DMA_REQUEST_DCMI   75U
 DMAMUX1 DCMI request.
#define DMA_REQUEST_CRYP_IN   76U
 DMAMUX1 CRYP IN request.
#define DMA_REQUEST_CRYP_OUT   77U
 DMAMUX1 CRYP OUT request.
#define DMA_REQUEST_HASH_IN   78U
 DMAMUX1 HASH IN request.
#define DMA_REQUEST_UART7_RX   79U
 DMAMUX1 UART7 RX request.
#define DMA_REQUEST_UART7_TX   80U
 DMAMUX1 UART7 TX request.
#define DMA_REQUEST_UART8_RX   81U
 DMAMUX1 UART8 RX request.
#define DMA_REQUEST_UART8_TX   82U
 DMAMUX1 UART8 TX request.
#define DMA_REQUEST_SPI4_RX   83U
 DMAMUX1 SPI4 RX request.
#define DMA_REQUEST_SPI4_TX   84U
 DMAMUX1 SPI4 TX request.
#define DMA_REQUEST_SPI5_RX   85U
 DMAMUX1 SPI5 RX request.
#define DMA_REQUEST_SPI5_TX   86U
 DMAMUX1 SPI5 TX request.
#define DMA_REQUEST_SAI1_A   87U
 DMAMUX1 SAI1 A request.
#define DMA_REQUEST_SAI1_B   88U
 DMAMUX1 SAI1 B request.
#define DMA_REQUEST_SWPMI_RX   91U
 DMAMUX1 SWPMI RX request.
#define DMA_REQUEST_SWPMI_TX   92U
 DMAMUX1 SWPMI TX request.
#define DMA_REQUEST_SPDIF_RX_DT   93U
 DMAMUX1 SPDIF RXDT request.
#define DMA_REQUEST_SPDIF_RX_CS   94U
 DMAMUX1 SPDIF RXCS request.
#define DMA_REQUEST_DFSDM1_FLT0   101U
 DMAMUX1 DFSDM Filter0 request.
#define DMA_REQUEST_DFSDM1_FLT1   102U
 DMAMUX1 DFSDM Filter1 request.
#define DMA_REQUEST_DFSDM1_FLT2   103U
 DMAMUX1 DFSDM Filter2 request.
#define DMA_REQUEST_DFSDM1_FLT3   104U
 DMAMUX1 DFSDM Filter3 request.
#define DMA_REQUEST_TIM15_CH1   105U
 DMAMUX1 TIM15 CH1 request.
#define DMA_REQUEST_TIM15_UP   106U
 DMAMUX1 TIM15 UP request.
#define DMA_REQUEST_TIM15_TRIG   107U
 DMAMUX1 TIM15 TRIG request.
#define DMA_REQUEST_TIM15_COM   108U
 DMAMUX1 TIM15 COM request.
#define DMA_REQUEST_TIM16_CH1   109U
 DMAMUX1 TIM16 CH1 request.
#define DMA_REQUEST_TIM16_UP   110U
 DMAMUX1 TIM16 UP request.
#define DMA_REQUEST_TIM17_CH1   111U
 DMAMUX1 TIM17 CH1 request.
#define DMA_REQUEST_TIM17_UP   112U
 DMAMUX1 TIM17 UP request.
#define BDMA_REQUEST_MEM2MEM   0U
 memory to memory transfer
#define BDMA_REQUEST_GENERATOR0   1U
 DMAMUX2 request generator 0.
#define BDMA_REQUEST_GENERATOR1   2U
 DMAMUX2 request generator 1.
#define BDMA_REQUEST_GENERATOR2   3U
 DMAMUX2 request generator 2.
#define BDMA_REQUEST_GENERATOR3   4U
 DMAMUX2 request generator 3.
#define BDMA_REQUEST_GENERATOR4   5U
 DMAMUX2 request generator 4.
#define BDMA_REQUEST_GENERATOR5   6U
 DMAMUX2 request generator 5.
#define BDMA_REQUEST_GENERATOR6   7U
 DMAMUX2 request generator 6.
#define BDMA_REQUEST_GENERATOR7   8U
 DMAMUX2 request generator 7.
#define BDMA_REQUEST_LPUART1_RX   9U
 DMAMUX2 LP_UART1_RX request.
#define BDMA_REQUEST_LPUART1_TX   10U
 DMAMUX2 LP_UART1_TX request.
#define BDMA_REQUEST_SPI6_RX   11U
 DMAMUX2 SPI6 RX request.
#define BDMA_REQUEST_SPI6_TX   12U
 DMAMUX2 SPI6 TX request.
#define BDMA_REQUEST_I2C4_RX   13U
 DMAMUX2 I2C4 RX request.
#define BDMA_REQUEST_I2C4_TX   14U
 DMAMUX2 I2C4 TX request.
#define DMA_PERIPH_TO_MEMORY   ((uint32_t)0x00000000U)
 Peripheral to memory direction.
#define DMA_MEMORY_TO_PERIPH   ((uint32_t)DMA_SxCR_DIR_0)
 Memory to peripheral direction.
#define DMA_MEMORY_TO_MEMORY   ((uint32_t)DMA_SxCR_DIR_1)
 Memory to memory direction.
#define DMA_PINC_ENABLE   ((uint32_t)DMA_SxCR_PINC)
 Peripheral increment mode enable.
#define DMA_PINC_DISABLE   ((uint32_t)0x00000000U)
 Peripheral increment mode disable.
#define DMA_MINC_ENABLE   ((uint32_t)DMA_SxCR_MINC)
 Memory increment mode enable.
#define DMA_MINC_DISABLE   ((uint32_t)0x00000000U)
 Memory increment mode disable.
#define DMA_PDATAALIGN_BYTE   ((uint32_t)0x00000000U)
 Peripheral data alignment: Byte.
#define DMA_PDATAALIGN_HALFWORD   ((uint32_t)DMA_SxCR_PSIZE_0)
 Peripheral data alignment: HalfWord.
#define DMA_PDATAALIGN_WORD   ((uint32_t)DMA_SxCR_PSIZE_1)
 Peripheral data alignment: Word.
#define DMA_MDATAALIGN_BYTE   ((uint32_t)0x00000000U)
 Memory data alignment: Byte.
#define DMA_MDATAALIGN_HALFWORD   ((uint32_t)DMA_SxCR_MSIZE_0)
 Memory data alignment: HalfWord.
#define DMA_MDATAALIGN_WORD   ((uint32_t)DMA_SxCR_MSIZE_1)
 Memory data alignment: Word.
#define DMA_NORMAL   ((uint32_t)0x00000000U)
 Normal mode.
#define DMA_CIRCULAR   ((uint32_t)DMA_SxCR_CIRC)
 Circular mode.
#define DMA_PFCTRL   ((uint32_t)DMA_SxCR_PFCTRL)
 Peripheral flow control mode.
#define DMA_DOUBLE_BUFFER_M0   ((uint32_t)DMA_SxCR_DBM)
 Double buffer mode with first target memory M0.
#define DMA_DOUBLE_BUFFER_M1   ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))
 Double buffer mode with first target memory M1.
#define DMA_PRIORITY_LOW   ((uint32_t)0x00000000U)
 Priority level: Low.
#define DMA_PRIORITY_MEDIUM   ((uint32_t)DMA_SxCR_PL_0)
 Priority level: Medium.
#define DMA_PRIORITY_HIGH   ((uint32_t)DMA_SxCR_PL_1)
 Priority level: High.
#define DMA_PRIORITY_VERY_HIGH   ((uint32_t)DMA_SxCR_PL)
 Priority level: Very High.
#define DMA_FIFOMODE_DISABLE   ((uint32_t)0x00000000U)
 FIFO mode disable.
#define DMA_FIFOMODE_ENABLE   ((uint32_t)DMA_SxFCR_DMDIS)
 FIFO mode enable.
#define DMA_FIFO_THRESHOLD_1QUARTERFULL   ((uint32_t)0x00000000U)
 FIFO threshold 1 quart full configuration.
#define DMA_FIFO_THRESHOLD_HALFFULL   ((uint32_t)DMA_SxFCR_FTH_0)
 FIFO threshold half full configuration.
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL   ((uint32_t)DMA_SxFCR_FTH_1)
 FIFO threshold 3 quarts full configuration.
#define DMA_FIFO_THRESHOLD_FULL   ((uint32_t)DMA_SxFCR_FTH)
 FIFO threshold full configuration.
#define DMA_MBURST_SINGLE   ((uint32_t)0x00000000U)
#define DMA_MBURST_INC4   ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8   ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16   ((uint32_t)DMA_SxCR_MBURST)
#define DMA_PBURST_SINGLE   ((uint32_t)0x00000000U)
#define DMA_PBURST_INC4   ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8   ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16   ((uint32_t)DMA_SxCR_PBURST)
#define DMA_IT_TC   ((uint32_t)DMA_SxCR_TCIE)
#define DMA_IT_HT   ((uint32_t)DMA_SxCR_HTIE)
#define DMA_IT_TE   ((uint32_t)DMA_SxCR_TEIE)
#define DMA_IT_DME   ((uint32_t)DMA_SxCR_DMEIE)
#define DMA_IT_FE   ((uint32_t)0x00000080U)
#define DMA_FLAG_FEIF0_4   ((uint32_t)0x00000001U)
#define DMA_FLAG_DMEIF0_4   ((uint32_t)0x00000004U)
#define DMA_FLAG_TEIF0_4   ((uint32_t)0x00000008U)
#define DMA_FLAG_HTIF0_4   ((uint32_t)0x00000010U)
#define DMA_FLAG_TCIF0_4   ((uint32_t)0x00000020U)
#define DMA_FLAG_FEIF1_5   ((uint32_t)0x00000040U)
#define DMA_FLAG_DMEIF1_5   ((uint32_t)0x00000100U)
#define DMA_FLAG_TEIF1_5   ((uint32_t)0x00000200U)
#define DMA_FLAG_HTIF1_5   ((uint32_t)0x00000400U)
#define DMA_FLAG_TCIF1_5   ((uint32_t)0x00000800U)
#define DMA_FLAG_FEIF2_6   ((uint32_t)0x00010000U)
#define DMA_FLAG_DMEIF2_6   ((uint32_t)0x00040000U)
#define DMA_FLAG_TEIF2_6   ((uint32_t)0x00080000U)
#define DMA_FLAG_HTIF2_6   ((uint32_t)0x00100000U)
#define DMA_FLAG_TCIF2_6   ((uint32_t)0x00200000U)
#define DMA_FLAG_FEIF3_7   ((uint32_t)0x00400000U)
#define DMA_FLAG_DMEIF3_7   ((uint32_t)0x01000000U)
#define DMA_FLAG_TEIF3_7   ((uint32_t)0x02000000U)
#define DMA_FLAG_HTIF3_7   ((uint32_t)0x04000000U)
#define DMA_FLAG_TCIF3_7   ((uint32_t)0x08000000U)
#define BDMA_FLAG_GL0   ((uint32_t)0x00000001)
#define BDMA_FLAG_TC0   ((uint32_t)0x00000002)
#define BDMA_FLAG_HT0   ((uint32_t)0x00000004)
#define BDMA_FLAG_TE0   ((uint32_t)0x00000008)
#define BDMA_FLAG_GL1   ((uint32_t)0x00000010)
#define BDMA_FLAG_TC1   ((uint32_t)0x00000020)
#define BDMA_FLAG_HT1   ((uint32_t)0x00000040)
#define BDMA_FLAG_TE1   ((uint32_t)0x00000080)
#define BDMA_FLAG_GL2   ((uint32_t)0x00000100)
#define BDMA_FLAG_TC2   ((uint32_t)0x00000200)
#define BDMA_FLAG_HT2   ((uint32_t)0x00000400)
#define BDMA_FLAG_TE2   ((uint32_t)0x00000800)
#define BDMA_FLAG_GL3   ((uint32_t)0x00001000)
#define BDMA_FLAG_TC3   ((uint32_t)0x00002000)
#define BDMA_FLAG_HT3   ((uint32_t)0x00004000)
#define BDMA_FLAG_TE3   ((uint32_t)0x00008000)
#define BDMA_FLAG_GL4   ((uint32_t)0x00010000)
#define BDMA_FLAG_TC4   ((uint32_t)0x00020000)
#define BDMA_FLAG_HT4   ((uint32_t)0x00040000)
#define BDMA_FLAG_TE4   ((uint32_t)0x00080000)
#define BDMA_FLAG_GL5   ((uint32_t)0x00100000)
#define BDMA_FLAG_TC5   ((uint32_t)0x00200000)
#define BDMA_FLAG_HT5   ((uint32_t)0x00400000)
#define BDMA_FLAG_TE5   ((uint32_t)0x00800000)
#define BDMA_FLAG_GL6   ((uint32_t)0x01000000)
#define BDMA_FLAG_TC6   ((uint32_t)0x02000000)
#define BDMA_FLAG_HT6   ((uint32_t)0x04000000)
#define BDMA_FLAG_TE6   ((uint32_t)0x08000000)
#define BDMA_FLAG_GL7   ((uint32_t)0x10000000)
#define BDMA_FLAG_TC7   ((uint32_t)0x20000000)
#define BDMA_FLAG_HT7   ((uint32_t)0x40000000)
#define BDMA_FLAG_TE7   ((uint32_t)0x80000000)
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__)
 Reset DMA handle state.
#define __HAL_DMA_GET_FS(__HANDLE__)
 Return the current DMA Stream FIFO filled level.
#define __HAL_DMA_ENABLE(__HANDLE__)
 Enable the specified DMA Stream.
#define __HAL_DMA_DISABLE(__HANDLE__)
 Disable the specified DMA Stream.
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
 Return the current DMA Stream transfer complete flag.
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
 Return the current DMA Stream half transfer complete flag.
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
 Return the current DMA Stream transfer error flag.
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
 Return the current DMA Stream FIFO error flag.
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
 Return the current DMA Stream direct mode error flag.
#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)
 Returns the current BDMA Channel Global interrupt flag.
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
 Get the DMA Stream pending flags.
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
 Clear the DMA Stream pending flags.
#define DMA_TO_BDMA_IT(__DMA_IT__)
#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
 Enable the specified DMA Stream interrupts.
#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
 Disable the specified DMA Stream interrupts.
#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
 Check whether the specified DMA Stream interrupt is enabled or not.
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__)
 Writes the number of data units to be transferred on the DMA Stream.
#define __HAL_DMA_GET_COUNTER(__HANDLE__)
 Returns the number of remaining data units in the current DMAy Streamx transfer.
#define IS_DMA_REQUEST(REQUEST)
#define IS_BDMA_REQUEST(REQUEST)
#define IS_DMA_DIRECTION(DIRECTION)
#define IS_DMA_BUFFER_SIZE(SIZE)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define IS_DMA_MEMORY_INC_STATE(STATE)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define IS_DMA_MODE(MODE)
#define IS_DMA_PRIORITY(PRIORITY)
#define IS_DMA_FIFO_MODE_STATE(STATE)
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define IS_DMA_MEMORY_BURST(BURST)
#define IS_DMA_PERIPHERAL_BURST(BURST)

Typedefs

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef
 DMA handle Structure definition.

Enumerations

enum  HAL_DMA_StateTypeDef {
  HAL_DMA_STATE_RESET = 0x00U , HAL_DMA_STATE_READY = 0x01U , HAL_DMA_STATE_BUSY = 0x02U , HAL_DMA_STATE_ERROR = 0x03U ,
  HAL_DMA_STATE_ABORT = 0x04U
}
 HAL DMA State structures definition. More...
enum  HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U , HAL_DMA_HALF_TRANSFER = 0x01U }
 HAL DMA Transfer complete level structure definition. More...
enum  HAL_DMA_CallbackIDTypeDef {
  HAL_DMA_XFER_CPLT_CB_ID = 0x00U , HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U , HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U , HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U ,
  HAL_DMA_XFER_ERROR_CB_ID = 0x04U , HAL_DMA_XFER_ABORT_CB_ID = 0x05U , HAL_DMA_XFER_ALL_CB_ID = 0x06U
}
 HAL DMA Callbacks IDs structure definition. More...

Functions

HAL_StatusTypeDef HAL_DMA_Init (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_StatusTypeDef HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_StatusTypeDef HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
void HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_DMA_StateTypeDef HAL_DMA_GetState (const DMA_HandleTypeDef *hdma)
uint32_t HAL_DMA_GetError (const DMA_HandleTypeDef *hdma)

Detailed Description

Header file of DMA HAL module.

Author
MCD Application Team
Attention

Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h7xx_hal_dma.h.