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Cal STAR — firmware, DAQ server, and engine design
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Header file of UART HAL module. More...
Go to the source code of this file.
Classes | |
| struct | UART_InitTypeDef |
| UART Init Structure definition. More... | |
| struct | UART_AdvFeatureInitTypeDef |
| UART Advanced Features initialization structure definition. More... | |
| struct | __UART_HandleTypeDef |
| UART handle Structure definition. More... | |
Macros | |
| #define | HAL_UART_STATE_RESET 0x00000000U |
| Peripheral is not initialized Value is allowed for gState and RxState. | |
| #define | HAL_UART_STATE_READY 0x00000020U |
| Peripheral Initialized and ready for use Value is allowed for gState and RxState. | |
| #define | HAL_UART_STATE_BUSY 0x00000024U |
| an internal process is ongoing Value is allowed for gState only | |
| #define | HAL_UART_STATE_BUSY_TX 0x00000021U |
| Data Transmission process is ongoing Value is allowed for gState only. | |
| #define | HAL_UART_STATE_BUSY_RX 0x00000022U |
| Data Reception process is ongoing Value is allowed for RxState only. | |
| #define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U |
| Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState.Value is result of combination (Or) between gState and RxState values. | |
| #define | HAL_UART_STATE_TIMEOUT 0x000000A0U |
| Timeout state Value is allowed for gState only. | |
| #define | HAL_UART_STATE_ERROR 0x000000E0U |
| Error Value is allowed for gState only. | |
| #define | HAL_UART_ERROR_NONE (0x00000000U) |
| No error. | |
| #define | HAL_UART_ERROR_PE (0x00000001U) |
| Parity error. | |
| #define | HAL_UART_ERROR_NE (0x00000002U) |
| Noise error. | |
| #define | HAL_UART_ERROR_FE (0x00000004U) |
| Frame error. | |
| #define | HAL_UART_ERROR_ORE (0x00000008U) |
| Overrun error. | |
| #define | HAL_UART_ERROR_DMA (0x00000010U) |
| DMA transfer error. | |
| #define | HAL_UART_ERROR_RTO (0x00000020U) |
| Receiver Timeout error. | |
| #define | UART_STOPBITS_0_5 USART_CR2_STOP_0 |
| UART frame with 0.5 stop bit. | |
| #define | UART_STOPBITS_1 0x00000000U |
| UART frame with 1 stop bit. | |
| #define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) |
| UART frame with 1.5 stop bits. | |
| #define | UART_STOPBITS_2 USART_CR2_STOP_1 |
| UART frame with 2 stop bits. | |
| #define | UART_PARITY_NONE 0x00000000U |
| No parity. | |
| #define | UART_PARITY_EVEN USART_CR1_PCE |
| Even parity. | |
| #define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) |
| Odd parity. | |
| #define | UART_HWCONTROL_NONE 0x00000000U |
| No hardware control. | |
| #define | UART_HWCONTROL_RTS USART_CR3_RTSE |
| Request To Send. | |
| #define | UART_HWCONTROL_CTS USART_CR3_CTSE |
| Clear To Send. | |
| #define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) |
| Request and Clear To Send. | |
| #define | UART_MODE_RX USART_CR1_RE |
| RX mode. | |
| #define | UART_MODE_TX USART_CR1_TE |
| TX mode. | |
| #define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) |
| RX and TX mode. | |
| #define | UART_STATE_DISABLE 0x00000000U |
| UART disabled. | |
| #define | UART_STATE_ENABLE USART_CR1_UE |
| UART enabled. | |
| #define | UART_OVERSAMPLING_16 0x00000000U |
| Oversampling by 16. | |
| #define | UART_OVERSAMPLING_8 USART_CR1_OVER8 |
| Oversampling by 8. | |
| #define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U |
| One-bit sampling disable. | |
| #define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT |
| One-bit sampling enable. | |
| #define | UART_PRESCALER_DIV1 0x00000000U |
| fclk_pres = fclk | |
| #define | UART_PRESCALER_DIV2 0x00000001U |
| fclk_pres = fclk/2 | |
| #define | UART_PRESCALER_DIV4 0x00000002U |
| fclk_pres = fclk/4 | |
| #define | UART_PRESCALER_DIV6 0x00000003U |
| fclk_pres = fclk/6 | |
| #define | UART_PRESCALER_DIV8 0x00000004U |
| fclk_pres = fclk/8 | |
| #define | UART_PRESCALER_DIV10 0x00000005U |
| fclk_pres = fclk/10 | |
| #define | UART_PRESCALER_DIV12 0x00000006U |
| fclk_pres = fclk/12 | |
| #define | UART_PRESCALER_DIV16 0x00000007U |
| fclk_pres = fclk/16 | |
| #define | UART_PRESCALER_DIV32 0x00000008U |
| fclk_pres = fclk/32 | |
| #define | UART_PRESCALER_DIV64 0x00000009U |
| fclk_pres = fclk/64 | |
| #define | UART_PRESCALER_DIV128 0x0000000AU |
| fclk_pres = fclk/128 | |
| #define | UART_PRESCALER_DIV256 0x0000000BU |
| fclk_pres = fclk/256 | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U |
| Auto Baud rate detection on start bit. | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 |
| Auto Baud rate detection on falling edge. | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 |
| Auto Baud rate detection on 0x7F frame detection. | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE |
| Auto Baud rate detection on 0x55 frame detection. | |
| #define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U |
| UART Receiver Timeout disable. | |
| #define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN |
| UART Receiver Timeout enable. | |
| #define | UART_LIN_DISABLE 0x00000000U |
| Local Interconnect Network disable. | |
| #define | UART_LIN_ENABLE USART_CR2_LINEN |
| Local Interconnect Network enable. | |
| #define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U |
| LIN 10-bit break detection length. | |
| #define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL |
| LIN 11-bit break detection length. | |
| #define | UART_DMA_TX_DISABLE 0x00000000U |
| UART DMA TX disabled. | |
| #define | UART_DMA_TX_ENABLE USART_CR3_DMAT |
| UART DMA TX enabled. | |
| #define | UART_DMA_RX_DISABLE 0x00000000U |
| UART DMA RX disabled. | |
| #define | UART_DMA_RX_ENABLE USART_CR3_DMAR |
| UART DMA RX enabled. | |
| #define | UART_HALF_DUPLEX_DISABLE 0x00000000U |
| UART half-duplex disabled. | |
| #define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL |
| UART half-duplex enabled. | |
| #define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U |
| UART wake-up on idle line. | |
| #define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE |
| UART wake-up on address mark. | |
| #define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ |
| Auto-Baud Rate Request. | |
| #define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ |
| Send Break Request. | |
| #define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ |
| Mute Mode Request. | |
| #define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ |
| Receive Data flush Request. | |
| #define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ |
| Transmit data flush Request. | |
| #define | UART_ADVFEATURE_NO_INIT 0x00000000U |
| No advanced feature initialization. | |
| #define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U |
| TX pin active level inversion. | |
| #define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U |
| RX pin active level inversion. | |
| #define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U |
| Binary data inversion. | |
| #define | UART_ADVFEATURE_SWAP_INIT 0x00000008U |
| TX/RX pins swap. | |
| #define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U |
| RX overrun disable. | |
| #define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U |
| DMA disable on Reception Error. | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U |
| Auto Baud rate detection initialization. | |
| #define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U |
| Most significant bit sent/received first. | |
| #define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U |
| TX pin active level inversion disable. | |
| #define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV |
| TX pin active level inversion enable. | |
| #define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U |
| RX pin active level inversion disable. | |
| #define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV |
| RX pin active level inversion enable. | |
| #define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U |
| Binary data inversion disable. | |
| #define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV |
| Binary data inversion enable. | |
| #define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U |
| TX/RX pins swap disable. | |
| #define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP |
| TX/RX pins swap enable. | |
| #define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U |
| RX overrun enable. | |
| #define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS |
| RX overrun disable. | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U |
| RX Auto Baud rate detection enable. | |
| #define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN |
| RX Auto Baud rate detection disable. | |
| #define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U |
| DMA enable on Reception Error. | |
| #define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE |
| DMA disable on Reception Error. | |
| #define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U |
| Most significant bit sent/received first disable. | |
| #define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST |
| Most significant bit sent/received first enable. | |
| #define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U |
| UART stop mode disable. | |
| #define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM |
| UART stop mode enable. | |
| #define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U |
| UART mute mode disable. | |
| #define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME |
| UART mute mode enable. | |
| #define | UART_CR2_ADDRESS_LSB_POS 24U |
| UART address-matching LSB position in CR2 register. | |
| #define | UART_WAKEUP_ON_ADDRESS 0x00000000U |
| UART wake-up on address. | |
| #define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 |
| UART wake-up on start bit. | |
| #define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS |
| UART wake-up on receive data register not empty or RXFIFO is not empty. | |
| #define | UART_DE_POLARITY_HIGH 0x00000000U |
| Driver enable signal is active high. | |
| #define | UART_DE_POLARITY_LOW USART_CR3_DEP |
| Driver enable signal is active low. | |
| #define | UART_CR1_DEAT_ADDRESS_LSB_POS 21U |
| UART Driver Enable assertion time LSB position in CR1 register. | |
| #define | UART_CR1_DEDT_ADDRESS_LSB_POS 16U |
| UART Driver Enable de-assertion time LSB position in CR1 register. | |
| #define | UART_IT_MASK 0x001FU |
| UART interruptions flags mask. | |
| #define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU |
| UART polling-based communications time-out value. | |
| #define | UART_FLAG_TXFT USART_ISR_TXFT |
| UART TXFIFO threshold flag. | |
| #define | UART_FLAG_RXFT USART_ISR_RXFT |
| UART RXFIFO threshold flag. | |
| #define | UART_FLAG_RXFF USART_ISR_RXFF |
| UART RXFIFO Full flag. | |
| #define | UART_FLAG_TXFE USART_ISR_TXFE |
| UART TXFIFO Empty flag. | |
| #define | UART_FLAG_REACK USART_ISR_REACK |
| UART receive enable acknowledge flag. | |
| #define | UART_FLAG_TEACK USART_ISR_TEACK |
| UART transmit enable acknowledge flag. | |
| #define | UART_FLAG_WUF USART_ISR_WUF |
| UART wake-up from stop mode flag. | |
| #define | UART_FLAG_RWU USART_ISR_RWU |
| UART receiver wake-up from mute mode flag. | |
| #define | UART_FLAG_SBKF USART_ISR_SBKF |
| UART send break flag. | |
| #define | UART_FLAG_CMF USART_ISR_CMF |
| UART character match flag. | |
| #define | UART_FLAG_BUSY USART_ISR_BUSY |
| UART busy flag. | |
| #define | UART_FLAG_ABRF USART_ISR_ABRF |
| UART auto Baud rate flag. | |
| #define | UART_FLAG_ABRE USART_ISR_ABRE |
| UART auto Baud rate error. | |
| #define | UART_FLAG_RTOF USART_ISR_RTOF |
| UART receiver timeout flag. | |
| #define | UART_FLAG_CTS USART_ISR_CTS |
| UART clear to send flag. | |
| #define | UART_FLAG_CTSIF USART_ISR_CTSIF |
| UART clear to send interrupt flag. | |
| #define | UART_FLAG_LBDF USART_ISR_LBDF |
| UART LIN break detection flag. | |
| #define | UART_FLAG_TXE USART_ISR_TXE_TXFNF |
| UART transmit data register empty. | |
| #define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF |
| UART TXFIFO not full. | |
| #define | UART_FLAG_TC USART_ISR_TC |
| UART transmission complete. | |
| #define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE |
| UART read data register not empty. | |
| #define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE |
| UART RXFIFO not empty. | |
| #define | UART_FLAG_IDLE USART_ISR_IDLE |
| UART idle flag. | |
| #define | UART_FLAG_ORE USART_ISR_ORE |
| UART overrun error. | |
| #define | UART_FLAG_NE USART_ISR_NE |
| UART noise error. | |
| #define | UART_FLAG_FE USART_ISR_FE |
| UART frame error. | |
| #define | UART_FLAG_PE USART_ISR_PE |
| UART parity error. | |
| #define | UART_IT_PE 0x0028U |
| UART parity error interruption. | |
| #define | UART_IT_TXE 0x0727U |
| UART transmit data register empty interruption. | |
| #define | UART_IT_TXFNF 0x0727U |
| UART TX FIFO not full interruption. | |
| #define | UART_IT_TC 0x0626U |
| UART transmission complete interruption. | |
| #define | UART_IT_RXNE 0x0525U |
| UART read data register not empty interruption. | |
| #define | UART_IT_RXFNE 0x0525U |
| UART RXFIFO not empty interruption. | |
| #define | UART_IT_IDLE 0x0424U |
| UART idle interruption. | |
| #define | UART_IT_LBD 0x0846U |
| UART LIN break detection interruption. | |
| #define | UART_IT_CTS 0x096AU |
| UART CTS interruption. | |
| #define | UART_IT_CM 0x112EU |
| UART character match interruption. | |
| #define | UART_IT_WUF 0x1476U |
| UART wake-up from stop mode interruption. | |
| #define | UART_IT_RXFF 0x183FU |
| UART RXFIFO full interruption. | |
| #define | UART_IT_TXFE 0x173EU |
| UART TXFIFO empty interruption. | |
| #define | UART_IT_RXFT 0x1A7CU |
| UART RXFIFO threshold reached interruption. | |
| #define | UART_IT_TXFT 0x1B77U |
| UART TXFIFO threshold reached interruption. | |
| #define | UART_IT_RTO 0x0B3AU |
| UART receiver timeout interruption. | |
| #define | UART_IT_ERR 0x0060U |
| UART error interruption. | |
| #define | UART_IT_ORE 0x0300U |
| UART overrun error interruption. | |
| #define | UART_IT_NE 0x0200U |
| UART noise error interruption. | |
| #define | UART_IT_FE 0x0100U |
| UART frame error interruption. | |
| #define | UART_CLEAR_PEF USART_ICR_PECF |
| Parity Error Clear Flag. | |
| #define | UART_CLEAR_FEF USART_ICR_FECF |
| Framing Error Clear Flag. | |
| #define | UART_CLEAR_NEF USART_ICR_NECF |
| Noise Error detected Clear Flag. | |
| #define | UART_CLEAR_OREF USART_ICR_ORECF |
| Overrun Error Clear Flag. | |
| #define | UART_CLEAR_IDLEF USART_ICR_IDLECF |
| IDLE line detected Clear Flag. | |
| #define | UART_CLEAR_TXFECF USART_ICR_TXFECF |
| TXFIFO empty clear flag. | |
| #define | UART_CLEAR_TCF USART_ICR_TCCF |
| Transmission Complete Clear Flag. | |
| #define | UART_CLEAR_LBDF USART_ICR_LBDCF |
| LIN Break Detection Clear Flag. | |
| #define | UART_CLEAR_CTSF USART_ICR_CTSCF |
| CTS Interrupt Clear Flag. | |
| #define | UART_CLEAR_CMF USART_ICR_CMCF |
| Character Match Clear Flag. | |
| #define | UART_CLEAR_WUF USART_ICR_WUCF |
| Wake Up from stop mode Clear Flag. | |
| #define | UART_CLEAR_RTOF USART_ICR_RTOCF |
| UART receiver timeout clear flag. | |
| #define | HAL_UART_RECEPTION_STANDARD (0x00000000U) |
| Standard reception. | |
| #define | HAL_UART_RECEPTION_TOIDLE (0x00000001U) |
| Reception till completion or IDLE event. | |
| #define | HAL_UART_RECEPTION_TORTO (0x00000002U) |
| Reception till completion or RTO event. | |
| #define | HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) |
| Reception till completion or CM event. | |
| #define | HAL_UART_RXEVENT_TC (0x00000000U) |
| RxEvent linked to Transfer Complete event. | |
| #define | HAL_UART_RXEVENT_HT (0x00000001U) |
| RxEvent linked to Half Transfer event. | |
| #define | HAL_UART_RXEVENT_IDLE (0x00000002U) |
| RxEvent linked to IDLE event. | |
| #define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) |
| Reset UART handle states. | |
| #define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) |
| Flush the UART Data registers. | |
| #define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) |
| Clear the specified UART pending flag. | |
| #define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
| Clear the UART PE pending flag. | |
| #define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) |
| Clear the UART FE pending flag. | |
| #define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) |
| Clear the UART NE pending flag. | |
| #define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) |
| Clear the UART ORE pending flag. | |
| #define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) |
| Clear the UART IDLE pending flag. | |
| #define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) |
| Clear the UART TX FIFO empty clear flag. | |
| #define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) |
| Check whether the specified UART flag is set or not. | |
| #define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) |
| Enable the specified UART interrupt. | |
| #define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) |
| Disable the specified UART interrupt. | |
| #define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) |
| Check whether the specified UART interrupt has occurred or not. | |
| #define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) |
| Check whether the specified UART interrupt source is enabled or not. | |
| #define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) |
| Clear the specified UART ISR flag, in setting the proper ICR register flag. | |
| #define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) |
| Set a specific UART request flag. | |
| #define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) |
| Enable the UART one bit sample method. | |
| #define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) |
| Disable the UART one bit sample method. | |
| #define | __HAL_UART_ENABLE(__HANDLE__) |
| Enable UART. | |
| #define | __HAL_UART_DISABLE(__HANDLE__) |
| Disable UART. | |
| #define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) |
| Enable CTS flow control. | |
| #define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) |
| Disable CTS flow control. | |
| #define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) |
| Enable RTS flow control. | |
| #define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) |
| Disable RTS flow control. | |
| #define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) |
| Get UART clock division factor from clock prescaler value. | |
| #define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) |
| BRR division operation to set BRR register with LPUART. | |
| #define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) |
| BRR division operation to set BRR register in 8-bit oversampling mode. | |
| #define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) |
| BRR division operation to set BRR register in 16-bit oversampling mode. | |
| #define | UART_INSTANCE_LOWPOWER(__HANDLE__) |
| Check whether or not UART instance is Low Power UART. | |
| #define | IS_UART_BAUDRATE(__BAUDRATE__) |
| Check UART Baud rate. | |
| #define | IS_UART_ASSERTIONTIME(__TIME__) |
| Check UART assertion time. | |
| #define | IS_UART_DEASSERTIONTIME(__TIME__) |
| Check UART deassertion time. | |
| #define | IS_UART_STOPBITS(__STOPBITS__) |
| Ensure that UART frame number of stop bits is valid. | |
| #define | IS_LPUART_STOPBITS(__STOPBITS__) |
| Ensure that LPUART frame number of stop bits is valid. | |
| #define | IS_UART_PARITY(__PARITY__) |
| Ensure that UART frame parity is valid. | |
| #define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__) |
| Ensure that UART hardware flow control is valid. | |
| #define | IS_UART_MODE(__MODE__) |
| Ensure that UART communication mode is valid. | |
| #define | IS_UART_STATE(__STATE__) |
| Ensure that UART state is valid. | |
| #define | IS_UART_OVERSAMPLING(__SAMPLING__) |
| Ensure that UART oversampling is valid. | |
| #define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) |
| Ensure that UART frame sampling is valid. | |
| #define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) |
| Ensure that UART auto Baud rate detection mode is valid. | |
| #define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) |
| Ensure that UART receiver timeout setting is valid. | |
| #define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) |
| Check the receiver timeout value. | |
| #define | IS_UART_LIN(__LIN__) |
| Ensure that UART LIN state is valid. | |
| #define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) |
| Ensure that UART LIN break detection length is valid. | |
| #define | IS_UART_DMA_TX(__DMATX__) |
| Ensure that UART DMA TX state is valid. | |
| #define | IS_UART_DMA_RX(__DMARX__) |
| Ensure that UART DMA RX state is valid. | |
| #define | IS_UART_HALF_DUPLEX(__HDSEL__) |
| Ensure that UART half-duplex state is valid. | |
| #define | IS_UART_WAKEUPMETHOD(__WAKEUP__) |
| Ensure that UART wake-up method is valid. | |
| #define | IS_UART_REQUEST_PARAMETER(__PARAM__) |
| Ensure that UART request parameter is valid. | |
| #define | IS_UART_ADVFEATURE_INIT(__INIT__) |
| Ensure that UART advanced features initialization is valid. | |
| #define | IS_UART_ADVFEATURE_TXINV(__TXINV__) |
| Ensure that UART frame TX inversion setting is valid. | |
| #define | IS_UART_ADVFEATURE_RXINV(__RXINV__) |
| Ensure that UART frame RX inversion setting is valid. | |
| #define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__) |
| Ensure that UART frame data inversion setting is valid. | |
| #define | IS_UART_ADVFEATURE_SWAP(__SWAP__) |
| Ensure that UART frame RX/TX pins swap setting is valid. | |
| #define | IS_UART_OVERRUN(__OVERRUN__) |
| Ensure that UART frame overrun setting is valid. | |
| #define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) |
| Ensure that UART auto Baud rate state is valid. | |
| #define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) |
| Ensure that UART DMA enabling or disabling on error setting is valid. | |
| #define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) |
| Ensure that UART frame MSB first setting is valid. | |
| #define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) |
| Ensure that UART stop mode state is valid. | |
| #define | IS_UART_MUTE_MODE(__MUTE__) |
| Ensure that UART mute mode state is valid. | |
| #define | IS_UART_WAKEUP_SELECTION(__WAKE__) |
| Ensure that UART wake-up selection is valid. | |
| #define | IS_UART_DE_POLARITY(__POLARITY__) |
| Ensure that UART driver enable polarity is valid. | |
| #define | IS_UART_PRESCALER(__CLOCKPRESCALER__) |
| Ensure that UART Prescaler is valid. | |
Typedefs | |
| typedef uint32_t | HAL_UART_StateTypeDef |
| HAL UART State definition. | |
| typedef uint32_t | HAL_UART_RxTypeTypeDef |
| HAL UART Reception type definition. | |
| typedef uint32_t | HAL_UART_RxEventTypeTypeDef |
| HAL UART Rx Event type definition. | |
| typedef struct __UART_HandleTypeDef | UART_HandleTypeDef |
| UART handle Structure definition. | |
Enumerations | |
| enum | UART_ClockSourceTypeDef { UART_CLOCKSOURCE_D2PCLK1 = 0x00U , UART_CLOCKSOURCE_D2PCLK2 = 0x01U , UART_CLOCKSOURCE_D3PCLK1 = 0x02U , UART_CLOCKSOURCE_PLL2 = 0x04U , UART_CLOCKSOURCE_PLL3 = 0x08U , UART_CLOCKSOURCE_HSI = 0x10U , UART_CLOCKSOURCE_CSI = 0x20U , UART_CLOCKSOURCE_LSE = 0x40U , UART_CLOCKSOURCE_UNDEFINED = 0x80U } |
| UART clock sources definition. More... | |
Variables | |
| const uint16_t | UARTPrescTable [12] |
Header file of UART HAL module.
Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
Definition in file stm32h7xx_hal_uart.h.