Public Attributes
__IOM uint32_t	CACR
	Offset: 0x0 (R/W) L1 Cache Control Register.
__IOM uint32_t	ITCMCR
	Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register.
__IOM uint32_t	DTCMCR
	Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers.

Detailed Description

Definition at line 560 of file core_starmc1.h.

The documentation for this struct was generated from the following file:

Public Attributes